Overview
The LC72121 and the LC72121M and the LC72121V are
high input sensitivity (20 mVrms at 130 MHz) PLL
frequency synthesizers for 3 V systems. These ICs are
serial data (CCB) compatible with the LC72131, and
feature the improved input sensitivity and lower spurious
radiation (provided by a redesigned ground system)
required in high-performance AM/FM tuners.
Functions
High-speed programmable divider
-- FMIN: 10 to 160 MHz ... Pulse swallower technique
(With built-in divide-by-2
prescaler)
-- AMIN: 2 to 40 MHz ... Pulse swallower technique
0.5 to 10 MHz ... Direct division technique
IF counter
-- IFIN: 0.4 to 12 MHz ... For AM and FM IF counting
Reference frequency
-- One of 12 reference frequencies can be selected
(using a 4.5 or 7.2 MHz crystal element)
1, 3, 5, 9, 10, 3.125, 6.25, 12.5, 15, 25, 50, or 100
kHz
Phase comparator
-- Supports dead zone control.
-- Built-in unlocked state detection circuit
-- Built-in deadlock clear circuit
An MOS transistor for an active low-pass filter is built
in.
I/O ports
-- Output-only ports: 4 pins
-- I/O ports: 2 pins
-- Supports the output of a clock time base signal.
Operating ranges
-- Supply voltage: 2.7 to 3.6 V
-- Operating temperature: 40 to 85C
Package
-- DIP22S, MFP24S, SSOP24
Comparison with the LC72131/M
-- Serial data compatible (CCB)
-- Identical pin functions
-- Two V
SS
pins were added.
-- The DIP version is pin compatible (V
SS
pins were
inserted as the DIP22S NC pins.)
-- The MFP product provides a modified pin
assignment (The MFP20 package was replaced by
an MFP24 package, and extra V
SS
pins were added.)
-- The SSOP24 is a newly developed package that has
the same pin assignment as the MFP24S product.
CMOS IC
70398RM (OT) No. 5815-1/22
Preliminary
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
PLL Frequency Synthesizers for Electronic Tuning
LC72121, 72121M, 72121V
Ordering number : EN
*
5815A
CCB is a trademark of SANYO ELECTRIC CO., LTD.
CCB is SANYO's original bus format and all the bus
addresses are controlled by SANYO.
Package Dimensions
unit: mm
3059-DIP22S
unit: mm
3112-MFP24S
unit: mm
3175A-SSOP24
No. 5815-2/22
LC72121, 72121M, 72121V
SANYO: DIP22S
[LC72121]
SANYO: MFP24S
[LC72121M]
SANYO: SSOP24
[LC72121V]
Pin Assignments
Top view
No. 5815-3/22
LC72121, 72121M, 72121V
Block Diagram
No. 5815-4/22
LC72121, 72121M, 72121V
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
DD
max
V
DD
0.3 to +7.0
V
V
IN
1 max
CE, DI, CL, AIN
0.3 to +7.0
V
Maximum input voltage
V
IN
2 max
XIN, FMIN, AMIN, IFIN
0.3 to V
DD
+0.3
V
V
IN
3 max
IO1, IO2
0.3 to +15
V
V
O
1 max
DO
0.3 to +7.0
V
Maximum output voltage
V
O
2 max
XOUT, PD
0.3 to V
DD
+0.3
V
V
O
3 max
BO1 to BO4, IO1, IO2, AOUT
0.3 to +15
V
Maximum output current
I
O
1 max
DO, AOUT
0 to +6.0
mA
I
O
2 max
BO1 to BO4, IO1, IO2
0 to +10.0
mA
DIP22S:
350
mW
Allowable power dissipation
Pd max
(Ta
85C)
MFP24S:
200
mW
SSOP24:
150
mW
Operating temperature
Topr
40 to +85
C
Storage temperature
Tstg
55 to +125
C
Specifications
Absolute Maximum Ratings
at Ta = 25C, V
SSd
= V
SSa
= V
SSX
= 0 V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
DD
V
DD
2.7
3.6
V
Input high-level voltage
V
IH
1
CE, DI, CL
0.7 V
DD
6.5
V
V
IH
2
IO1, IO2
0.7 V
DD
13
V
Input low-level voltage
V
IL
CE, DI, CL, IO1, IO2
0
0.3 V
DD
V
Output voltage
V
O
1
DO
0
6.5
V
V
O
2
BO1 to BO4, IO1, IO2, AOUT
0
13
V
f
IN
1
XIN: V
IN
1
1
8
MHz
f
IN
2
FMIN: V
IN
2
10
160
MHz
Input frequency
f
IN
3
AMIN (SNS = 1): V
IN
3
2
40
MHz
f
IN
4
AMIN (SNS = 0): V
IN
4
0.5
10
MHz
f
IN
5
IFIN: V
IN
5
0.4
12
MHz
V
IN
1
XIN: f
IN
1
200
800
mVrms
V
IN
2-1
FMIN: f = 10 to 130 MHz
20
800
mVrms
V
IN
2-2
FMIN: f = 130 to 160 MHz
40
800
mVrms
Input amplitude
V
IN
3
AMIN (SNS = 1): f
IN
3
40
800
mVrms
V
IN
4
AMIN (SNS = 0): f
IN
4
40
800
mVrms
V
IN
5-1
IFIN: f
IN
5, IFS = 1
40
800
mVrms
V
IN
5-2
IFIN: f
IN
5, IFS = 0
70
800
mVrms
Guaranteed crystal oscillator frequency
Xtal
XIN, XOUT:
*
1
4.5
MHz
XIN, XOUT:
*
2
7.2
MHz
Allowable Operating Ranges
at Ta = 40 to +85C, V
SSd
= V
SSa
= V
SSX
= 0 V
Notes: 1. Recommended value for CI for the crystal oscillator element: CI < 120
2. Recommended value for CI for the crystal oscillator element: CI < 70
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Rf1
XIN
1
M
Internal feedback resistance
Rf2
FMIN
500
k
Rf3
AMIN
500
k
Rf4
IFIN
250
k
Internal pull-down resistance
Rpd1
FMIN
100
200
400
k
Rpd2
AMIN
100
200
400
k
Hysteresis
V
HIS
CE, DI, CL
0.1 V
DD
V
Output high-level voltage
V
OH
1
PD: I
O
= 1 mA
V
DD
1.0
V
Electrical Characteristics
in the Allowable Operating Ranges
Continued on next page.
No. 5815-5/22
LC72121, 72121M, 72121V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
V
OL
1
PD: I
O
= 1 mA
1.0
V
V
OL
2
BO1 to BO4, IO1, IO2: I
O
= 1 mA
0.2
V
Output low-level voltage
BO1 to BO4, IO1, IO2: I
O
= 8 mA
1.6
V
V
OL
3
DO: I
O
= 5 mA
1.0
V
V
OL
4
AOUT: I
O
= 1 mA, AIN = 1.3 V
0.5
V
I
IH
1
CE, DI, CL: V
I
= 6.5 V
5.0
A
I
IH
2
IO1, IO2: V
I
= 13 V
5.0
A
Input high-level current
I
IH
3
XIN: V
I
= V
DD
1.3
8
A
I
IH
4
FMIN, AMIN: V
I
= V
DD
2.5
15
A
I
IH
5
IFIN: V
I
= V
DD
5.0
30
A
I
IH
6
AIN: V
I
= 6.5 V
200
nA
I
IL
1
CE, DI, CL: V
I
= 0 V
5.0
A
I
IL
2
IO1, IO2: V
I
= 0 V
5.0
A
Input low-level current
I
IL
3
XIN: V
I
= 0 V
1.3
8
A
I
IL
4
FMIN, AMIN: V
I
= 0 V
2.5
15
A
I
IL
5
IFIN: V
I
= 0 V
5.0
30
A
I
IL
6
AIN: V
I
= 0 V
200
nA
Output off leakage current
I
OFF
1
BO1 to BO4, IO1, IO2, AOUT: V
O
= 13 V
5.0
A
I
OFF
2
DO: V
O
= 6.5 V
5.0
A
High-level 3-state off leakage current
I
OFFH
PD: V
O
= V
DD
0.01
200
nA
Low-level 3-state off leakage current
I
OFFL
PD: V
O
= 0 V
0.01
200
nA
Input capacitance
C
IN
FMIN
6
pF
I
DD
1
V
DD
: Xtal = 7.2 MHz, f
IN
2 = 130 MHz,
2.5
6
mA
V
IN
2 = 20 mVrms
Supply current
V
DD
: PLL block stopped (PLL inhibit mode)
I
DD
2
Crystal oscillator operating
0.3
mA
(crystal frequency: 7.2 MHz)
I
DD
3
V
DD
: PLL block stopped, crystal oscillator
10
A
stopped
Continued from preceding page.
Pin Descriptions
Pin
Pin No.
Type
Function
Equivalent circuit
name
LC72121
Xtal
Crystal oscillator element connections (4.5 or 7.2 MHz)
XIN
XOUT
1
22
1
24
LC72121M
LC72121V
Local
oscillator
signal input
FMIN is selected when DVS in the serial data is set to 1.
Input frequency: 10 to 160 MHz
The signal is passed through an internal divide-by-two prescaler and
then input to the swallow counter.
The divisor can be set to a value in the range 272 to 65535. Since
the internal divide-by-two prescaler is used, the actual divisor will be
twice the set value.
FMIN
16
17
Local
oscillator
signal input
AMIN is selected when DVS in the serial data is set to 0.
When SNS in the serial data is set to 1:
Input frequency: 2 to 40 MHz
The signal is input to the swallow counter directly.
The divisor can be set to a value in the range 272 to 65535. The
set value becomes the actual divisor.
When SNS in the serial data is set to 0:
Input frequency: 0.5 to 10 MHz
The signal is input to a 12-bit programmable divider directly.
The divisor can be set to a value in the range 4 to 4095. The set
value becomes the actual divisor.
AMIN
15
16
Continued on next page.
No. 5815-6/22
LC72121, 72121M, 72121V
Continued from preceding page.
Pin
Pin No.
Type
Function
Equivalent circuit
name
LC72121
Chip enable
This pin must be set high to enable serial data input (DI) or serial
data output (DO).
CE
3
3
LC72121M
LC72121V
Input data
Input for serial data transferred from the controller
DI
4
4
Clock
Clock used for data synchronization for serial data input (DI) and
serial data output (DO).
CL
5
5
Output data
Output for serial data transmitted to the controller. The content of the
data transmitted is determined by DOC0 through DOC2.
DO
6
6
Power supply
LC72121 power supply (V
DD
2.7 to 3.6 V)
The power on reset circuit operates when power is first applied.
----
V
DD
17
18
Ground
Ground for the crystal oscillator circuit
----
V
SSX
2
2
Ground
Ground for the low-pass filter MOS transistor
----
V
SSa
21
22
Ground
Ground for the LC72121 digital systems other than those that use
V
SSa
or V
SSX
.
----
V
SSd
14
15
I/O port
Shared function I/O ports
The pin function is determined by IOC1 and IOC2 in the serial data.
When the data value 0: Input port
When the data value 1: Output port
When specified to function as an input port:
The input pin state is reported to the controller through the DO pin.
When the input state is low: The data will be 0:
When the input state is high: The data will be 1:
When specified to function as an output port:
The output state is determined by IO1 and IO2 in the serial data.
When the data value is 0: The output state will be the open circuit
state.
When the data value is 1: The output state will be a low level.
These pins are set to input mode after a power on reset.
IO1
IO2
11
13
11
14
Output port
Output-only ports
The output state is determined by BO1 through BO4 in the serial
data.
When the data value is 0: The output state will be the open circuit
state.
When the data value is 1: The output state will be a low level.
A time base signal (8 Hz) is output from BO1 when TBC in the serial
data is set to 1.
BO1
BO2
BO3
BO4
7
8
9
10
7
8
9
10
Charge pump
output
PLL charge pump output
A high level is output when the frequency of the local oscillator signal
divided by N is higher than the reference frequency, and a low level
is output when that frequency is lower. This pin goes to the high-
impedance state when the frequencies match.
PD
18
19
Low-pass filter
amplifier
transistor
Connections for the MOS transistor used for the PLL active low-pass
filter.
AIN
AOUT
19
20
20
21
IF counter
The input frequency range is 0.4 to 12 MHz
The signal is passed directly to the IF counter.
The result is output, MSB first, through the DO pin.
Four measurement periods are supported: 4, 8, 32, and 64 ms.
IFIN
12
13
12
23
NC
--
NC pin
No connection
----
Procedures for Input and Output of Serial Data
This product uses the CCB (Computer Control Bus), which is Sanyo's audio product serial bus format, for data input and
output. This product adopts an 8-bit address CCB format.
No. 5815-7/22
LC72121, 72121M, 72121V
I/O mode
Address
Function
B0
B1
B2
B3
A0
A1
A2
A3
Control data input (serial data input) mode
1
IN1 (82)
0
0
0
1
0
1
0
0
24 bits of data are input.
See the "DI Control Data (serial data input)" section for details on the
content of the input data.
Control data input (serial data input) mode
2
IN2 (92)
1
0
0
1
0
1
0
0
24 bits of data are input.
See the "DI Control Data (serial data input)" section for details on the
content of the input data.
Data output (serial data output) mode
3
OUT (A2)
0
1
0
1
0
1
0
0
The number of bits output is equal to the number of clock cycles.
See the "DO Control Data (serial data output)" section for details on the
content of the output data.
CL: Normally high
CL: Normally low
I/O mode determined
Structure of the DI Control Data (serial data input)
IN1 mode
IN2 mode
No. 5815-8/22
LC72121, 72121M, 72121V
No. 5815-9/22
LC72121, 72121M, 72121V
DI Control Data
No.
Control block/data
Function
Related data
1
Programmable
divider data
P0 to P15
DVS, SNS
Specifies the divisor for the programmable divider.
This is a binary value in which P15 is the MSB. The LSB changes depending on DVS and SNS.
(
*
: don't care)
*
LSB: When P4 is the LSB, P0 to P3 are ignored.
2
Reference divider
data
R0 to R3
XS
Reference frequency selection
*
PLL INHIBIT mode
In this mode, the programmable divider and the IF counter block are stopped, the FMIN, AMIN, and IFIN
pins are pulled down to ground, and the charge pump output goes to the high-impedance state.
Crystal oscillator element selection data
XS = 0: 4.5 MHz
XS = 1: 7.2 MHz
Note that 7.2 MHz is selected after a power on reset.
3
IF counter control
data
CTE
GT0, GT1
IFS
IF counter measurement start command data
CTE = 1: Starts the counter
CTE = 0: Resets the counter
Determines the IF counter measurement time.
DVS
SNS
LSB
Set divisor (N)
Actual divisor
1
*
P0
272 to 65535
Twice the set value
0
1
P0
272 to 65535
The set value
0
0
P4
4 to 4095
The set value
GT1
GT0
Measurement time
Wait time
0
0
4 ms
3 to 4 ms
0
1
8
3 to 4
1
0
32
7 to 8
1
1
64
7 to 8
R3
R2
R1
R0
Reference frequency
0
0
0
0
100
kHz
0
0
0
1
50
0
0
1
0
25
0
0
1
1
25
0
1
0
0
12.5
0
1
0
1
6.25
0
1
1
0
3.125
0
1
1
1
3.125
1
0
0
0
10
1
0
0
1
9
1
0
1
0
5
1
0
1
1
1
1
1
0
0
3
1
1
0
1
15
1
1
1
0
PLL INHIBIT + Xtal OSC STOP
1
1
1
1
PLL INHIBIT
These pins select the signal input to the programmable divider (FMIN or AMIN) and switch the input
frequency range.
*
See the "Structure of the Programmable Divider" section for details.
*
See the "Structure of the IF Counter" section for details.
DVS
SNS
Input pin
Frequency range accepted by the input pin
1
*
FMIN
10 to 160 MHz
0
1
AMIN
2 to 40 MHz
0
0
AMIN
0.5 to 10 MHz
(
*
: don't care)
Continued on next page.
No.
Control block/data
Function
Related data
No. 5815-10/22
LC72121, 72121M, 72121V
Continued from preceding page.
4
I/O port setup data
IOC1,IOC2
Specifies input or output for the shared function I/O pins (IO1 and IO2).
Data = 0: Input port
Data = 1: Output port
5
Output port data
BO1 to BO4
IO1,IO2
Determines the output state of the BO1 through BO4, IO1, and IO2 output ports.
Data = 0: Open
Data = 1: Low level
The data is reset to 0, setting the pins to the open state, after a power on reset.
IOC1
IOC2
6
DO pin control data
DOC0
DOC1
DOC2
Determines the DO pin output.
The open state is selected after a power on reset.
*
1. end-UC: IF counter measurement end check
(1)When end-UC is selected and an IF count is started (by switching CTE from 0 to 1), the DO pin
automatically goes to the open state.
(2)When the IF counter measurement period completes, the DO pin goes to the low level, allowing
applications to test for the completion of the count period.
(3)The DO pin is set to the open state by performing a serial data input or output operation (when the CE
pin is set high).
*
2. The DO pin will go to the open state if the corresponding IO pin is set up to be an output port.
Note: During the data input period (the period that CE is high in IN1 or IN2 mode), the DO pin goes to the
open state regardless of the DO pin control data (DOC0 to DOC2). During the data output period (the
period that CE is high in OUT mode) the DO pin state reflects the internal DO serial data in
synchronization with the CL clock, regardless of the DO pin control data (DOC0 to DOC2).
UL0, UL1
CTE
IOC1
IOC2
7
Unlocked state
detection data
UL0, UL1
Selects the width of the phase error (E) detected for PLL lock state discrimination. The state is taken to
be unlocked if a phase error in excess of the detection width occurs.
*
When the PLL is unlocked, the DO pin goes low and UL in the serial data output is set to 0.
Dead zone width: DZA < DZB < DZC < DZD
DOC0
DOC1
DOC2
8
Phase comparator
control data
DZ0, DZ1
Controls the phase comparator dead zone
DOC2
DOC1
DOC0
DO pin state
0
0
0
Open
0
0
1
Low when the PLL is unlocked
0
1
0
end-UC
*
1
0
1
1
Open
1
0
0
Open
1
0
1
The IO1 pin state
*
2
1
1
0
The IO2 pin state
*
2
1
1
1
Open
UL1
UL0
E detection width
Detection output
0
0
Stopped
Open
0
1
0
E is output directly
1
0
0.55 s
E is extended by 1 to 2 ms
1
1
1.11 s
E is extended by 1 to 2 ms
DZ1
DZ
Dead zone mode
0
0
DZA
0
1
DZB
1
0
DZC
1
1
DZD
Continued on next page.
No.
Control block/data
Function
Related data
No. 5815-11/22
LC72121, 72121M, 72121V
Continued from preceding page.
No.
Control block/data
Function
Related data
9
Clock time base
TBC
Setting the TBC bit to 1 causes an 8-Hz clock time base signal with a 40% duty to be output from the
BO1 pin. (The BO1 data will be ignored.)
BO1
10
Charge pump
control data
DLC
Forcibly controls the charge pump output.
*
If the circuit deadlocks due to the VCO control voltage (Vtune) being 0 and the VCO being stopped,
applications can get out of the deadlocked state by setting the charge pump output to low and setting
Vtune to V
CC
. (Deadlock clear circuit)
11
IF counter control
data
IFS
This data is normally set to 1. Setting this data to 0 sets the circuit to reduced input sensitivity mode, in
which the sensitivity is reduced by about 10 to 30 mV rms.
*
See the "IF Counter Operation" section for details.
1
I/O port data
12, I1
Data latched from the I/O port IO pin states.
These bits reflect the pin states regardless of the I/O port mode (input or output).
The data is latched at the point the circuit enters data output mode (OUT mode).
I1
The IO1 pin state
H : 1
I2
The IO2 pin state
L : 0
IOC1
IOC2
12
Test data
TEST0 to 2
Test data
TEST0
TEST1
All these bits must be set to 0.
TEST2
All these bits are set to 0 after a power on reset.
13
DNC
This bit must be set to 0.
DLC
Charge pump output
0
Normal operation
1
Forced to low
Structure of the DO Output Data (serial data output)
OUT mode
DO Output Data
2
PLL unlocked state
data
UL
Indicates the state of the unlocked state detection circuit.
UL
0: When the PLL is unlocked.
UL
1: When the PLL is locked or in the detection disabled mode.
UL0
UL1
3
IF counter binary
data
C19 to C0
Indicates the value of the IF counter (20-bit binary counter).
C19
MSB of the binary counter
C0
LSB of the binary counter
CTE
GT0
GT1
Serial Data Input (IN1/IN2) t
SU
, t
HD
, t
EL
, t
ES
, t
EH
0.75 s t
LC
< 0.75 s
CL: Normal (high)
No. 5815-12/22
LC72121, 72121M, 72121V
CL: Normal (low)
Serial Data Output (Out) t
SU
, t
HD
, t
EL
, t
ES
, t
EH
0.75 s t
DC
, t
DH
< 0.35 s
CL: Normal (high)
CL: Normal (low)
Note:
The data conversion times (t
DC
and t
DH
) depend on the value of the pull-up resistor and the printed circuit board capacitance since the DO pin is an
n-channel open-drain circuit.
Serial Data Timing
No. 5815-13/22
LC72121, 72121M, 72121V
When CL is Stopped at the Low Level
When CL is Stopped at the High Level
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Data setup time
t
SU
DI, CL
0.75
s
Data hold time
t
HD
DI, CL
0.75
s
Clock low level time
t
CL
CL
0.75
s
Clock high level time
t
CH
CL
0.75
s
CE wait time
t
EL
CE, CL
0.75
s
CE setup time
t
ES
CE, CL
0.75
s
CE hold time
t
EH
CE, CL
0.75
s
Data latch change time
t
LC
0.75
s
Data output time
t
DC
DO, CL These values differ depending on the value of the pull-up
0.35
s
t
DH
DO, CE resistor used and the printed circuit board capacitance.
0.35
s
Structure of the Programmable Divider
Sample Programmable Divider Divisor Calculations
For FM with a step size of 50 kHz (DVS = 1, SNS = *: FMIN selected)
FM RF = 90.0 MHz (IF +10.7 MHz)
FM VCO = 100.7 MHz
PLL fref = 25 kHz (R0 = 0, R1 = 1, R2 = 0, R3 = 0)
100.7 MHz (FM VCO)
25 kHz (fref)
2 (for the FMIN 1/2 prescaler) 2014
07DE (hexadecimal)
*
: Don't care
No. 5815-14/22
LC72121, 72121M, 72121V
DVS
SNS
Input pin
Set divisor
Actual divisor
Input frequency range
A
1
*
FMIN
272 to 65535
Twice the set value
10 to 160 MHz
B
0
1
AMIN
272 to 65535
The set value
2 to 40 MHz
C
0
0
AMIN
4 to 4095
The set value
0.5 to 10 MHz
For SW with a step size of 5 kHz (DVS = 0, SNS = 1: AMIN high-speed operation selected)
SW RF = 21.75 MHz (IF +450 kHz)
SW VCO = 22.20 MHz
PLL fref = 5 kHz (R0 = 0, R1 = 1, R2 = 0, R3 = 1)
22.2 MHz (SW VCO)
5 kHz (fref) = 4440
1158 (hexadecimal)
For MW with a step size of 9 kHz (DVS = 0, SNS = 0: AMIN low-speed operation selected)
MW RF = 1008 kHz (IF +450 kHz)
WM VCO = 1458 kHz
PLL fref =9 kHz (R0 = 1, R1 = 0, R2 = 0, R3 = 1)
1458 (MW VCO)
9 kHz (fref) = 162
0A2 (hexadecimal)
Structure of the IF Counter
The LC72121 IF counter is a 20-bit binary counter, and takes the IF signal from the IFIN pin as its input. The result of
the count can be read out serially, MSB first, from the DO pin.
The IF frequency (Fc) is measured by determining how many pulses were input to the IF counter in the stipulated
measurement time, GT.
C
Fc =---- (C = Fc
x
GT)
C: Counted value (the number of pulses)
GT
No. 5815-15/22
LC72121, 72121M, 72121V
GT1
GT0
Measurement time
Measurement time (GT)
Wait time (t
WU
)
0
0
4 ms
3 to 4 ms
0
1
8
3 to 4 ms
1
0
32
7 to 8 ms
1
1
64
7 to 8 ms
IF Counter Frequency Measurement Examples
When the measurement time (GT) is 32 ms and the counted value (C) is 53980 (hexadecimal) or 342,400 decimal.
IF frequency (F
C
) = 342400
32 ms = 10.7 MHz
When the measurement time (GT) is 8 ms and the counted value (C) is E10 (hexadecimal) or 3600 decimal.
IF frequency (F
C
) = 3600
8 ms = 450 kHz
IF Counter Operation
Applications must first, before starting an IF count operation reset the IF counter by setting CTE in the serial data to 0.
The IF counter operation is started setting CTE in the serial data from 0 to 1. Although the serial data is latched by
dropping the CE pin from high to low, the IF signal input to the IFIN pin must be provided within the wait time from the
point CE goes low. Next, the readout of the IF counter after measurement is complete must be performed while CTE is
still 1, since the counter will be reset if CTE is set to 0.
Note: If IF counting is used, applications must determine whether or not the IF IC SD (station detect) signal is present in
the microcontroller software, and perform the IF count only if that signal is asserted. This is because auto-search
techniques that use IF counting only are subject to incorrect stopping at points where there is no station due to IF
buffer leakage.
Note that the LC72121 input sensitivity can be controlled with the IFS bit in the serial data.
Reduced sensitivity mode (IFS = 0) must be selected when this IC is used in conjunction with an IF IC that does
not provide an SD output and auto-search is implemented using only IF counting.
IFIN Minimum Sensitivity Standard
No. 5815-16/22
LC72121, 72121M, 72121V
IFS data
0.4
f < 0.5
0.5
f < 0.8
8
f
12
1(Normal mode)
40 mVrms (0.1 to 3 mVrms)
40 mVrms
40 mVrms (1 to 10 mVrms)
0 (Degraded sensitivity mode)
70 mVrms (10 to 15 mVrms)
70 mVrms
70 Vrms (30 to 40 mVrms)
Input frequency : f [MHz]
Note: Values in parentheses are actual performance values that are provided for reference purposes.
Unlocked State Detection Timing
Unlocked state detection timing
Unlocked state detection is performed during the reference frequency (fref) period (interval). This means that a period
at least as long as the period of the reference frequency is required to recognize the locked/unlocked state. However,
applications must wait at least twice the period of the reference frequency immediately after changing the divisor (N)
before checking the locked/unlocked state.
No. 5815-17/22
LC72121, 72121M, 72121V
Figure 1 Unlocked State Detection Timing
For example, if fref is 1 kHz (a period of 1 ms) applications must wait at least 2 ms after the divisor N is changed
before performing a locked/unlocked check.
Figure 2 Circuit Structure
Figure 3 Combining with Software
Outputting the unlocked state data in the serial data
At the point of data output 1 in figure 3, the unlocked state data will indicate the unlocked state, since the VCO
frequency is not stable (locked) yet. In cases such as this, the application should wait at least one whole period and then
check again whether or not the frequency has stabilized with the data output 2 operation in the figure. Applications can
implement even more reliable recognition of the locked state by performing several more checks of the state and
requiring that the locked state be detected sequentially.
<Flowchart for Lock Detection>
Directly outputting the unlocked state to the DO pin
Since the unlocked state (high level when locked, low when unlocked) is output from the DO pin, applications can
check for the locked state by waiting at least two reference frequency periods after changing the divisor N. However, in
this case also, even more reliable recognition of the locked state can be achieved by performing several checks of the
state and requiring that the locked state be detected sequentially.
Wait at least 2 reference frequency periods.
Valid output data is acquired by using an interval of at
least one reference frequency period.
*
: Even more reliable recognition of the locked state
can be achieved by performing several checks of the
state and requiring that the locked state be detected
sequentially.
Divisor N changed (data input)
Data output (1)
Data output (2)
No. 5815-18/22
LC72121, 72121M, 72121V
Locked state check
YES
NO
A10180
Clock Time Base Usage Notes
When using the clock time base output function, the output pin (BO1) pull-up resistor must have a value of over 100 k
.
The use of a Schmitt input in the microcontroller that accepts this signal is recommended to reduce chattering. This is to
prevent degradation of the VCO C/N characteristics when combining with a loop filter that uses the internal transistor
provided to form a low-pass filter. Although the ground for the clock time base output pin (V
SSd
) and the ground for the
transistor (V
SSa
) are isolated internally on the chip, applications must take care to avoid ground loops and minimize
current fluctuations in the time base pin to prevent degradation of the low-pass filter characteristics.
No. 5815-19/22
LC72121, 72121M, 72121V
Pin States after a Power on Reset
Sample Application Circuit
(Using the DIP22S package)
No. 5815-20/22
LC72121, 72121M, 72121V
Since this is a high-impedance circuit,
it is susceptible to noise. Therefore,
lines in the printed circuit board
pattern should be made as short as
possible and it should be surrounded
by the ground pattern.
Other Items
Notes on the phase comparator dead zone
When the charge pump is used with one of the ON/ON modes, correction pulses are generated from the charge pump
even if the PLL is locked. As a result, it is easy for the loop to become unstable, and special care is required in
application design. The following problems can occur if an ON/ON mode is used.
-- Sidebands may be created by reference frequency leakage.
-- Sidebands may be created by low-frequency leakage due to the correction pulse envelope.
Although the loop is more stable when a dead zone is present (i.e. when an OFF/OFF mode is used), a dead zone
makes it more difficult to achieve excellent C/N characteristics. On the other hand, while it is easy to achieve good C/N
characteristics when there is no dead zone, achieving good loop stability is difficult. Accordingly, the DZA and DZB
settings, in which there is no dead zone, can be effective in situations where a signal-to-noise ratio of 90 to 100 dB or
higher is required in FM reception, or where it is desirable to increase the pilot margin in AM stereo reception.
However, if such a high signal-to-noise ratio is not required for FM reception, if an adequate pilot margin can be
acquired in AM stereo reception, or if AM stereo is not required, then either DZC or DZD, in which there is a dead
zone, should be chosen.
Dead Zone
As shown in figure 1, the phase comparator compares a reference frequency (fr) with fp. As shown in figure 2, the phase
comparator's characteristics consist of an output voltage (V) that is proportional to the phase difference . However, due
to internal circuit delay and other factors, an actual circuit has a region (the dead zone, B) where the circuit cannot
actually compare the phases. To implement a receiver with a high S/N ratio, it is desirable that this region be as small as
possible. However, it is often desirable to have the dead zone be slightly wider in popularly-priced models. This is
because in certain cases, such as when there is a strong RF input, popularly-priced models can suffer from mixer to VCO
RF leakage that modulates the VCO. When the dead zone is small, the circuit outputs signals to correct this modulation
and this output further modulates the VCO. This further modulation may then generate beats and the RF signal.
Notes on the FMIN, AMIN, and IFIN pins
Coupling capacitors should be placed as close to their pin as possible. A capacitance of about 100 pF is desirable for
these capacitors. In particular, if the IFIN pin coupling capacitor is not held under 1000 pF, the time to reach the bias
level may become excessive and incorrect counts may result due to the relationship with the wait time.
Notes on IF counting
Use the SD signal in conjunction with IF counting
When counting the IF frequency, the microcontroller must determine the presence or absence of the IF IC SD (station
detect) signal and turn on the IF counter buffer output and execute the IF count only if there is an SD signal. Auto-
search techniques that only use the IF counter are subject to incorrect stopping at points where there is no station due to
IF buffer leakage.
No. 5815-21/22
LC72121, 72121M, 72121V
DZ1
DZ0
Dead zone mode
Charge pump
Dead zone
0
0
DZA
ON/ON
0s
0
1
DZB
ON/ON
0s
1
0
DZC
OFF/OFF
+0s
1
1
DZD
OFF/OFF
+ +0s
Figure 1
Figure 2
PS No. 5815-22/22
LC72121, 72121M, 72121V
This catalog provides information as of July, 1998. Specifications and information herein are subject to change
without notice.
s
No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
s
Anyone purchasing any products described or contained herein for an above-mentioned use shall:
Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
s
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
DO pin usage
The DO pin can be used for IF counter count completion checking and as an unlock detection output in addition to its
use in data output mode. It is also possible to have the DO pin reflect the state of an input pin to input that state to the
microcontroller.
Power supply pins
Capacitors must be inserted between the power supply V
DD
and V
SS
pins for noise exclusion. These capacitors must be
placed as close as possible to the V
DD
and V
SS
pins.
VCO setup
Applications must be designed so that the VCO (local oscillator) does not stop, even if the control voltage (Vtune) goes
to 0 V. If it is possible for the oscillator to stop, the application must use the control data (DLC) to temporarily force
Vtune to V
CC
to prevent deadlock from occurring. (Deadlock clear circuit)
Front end connection example
Since this product (and the LC72131 as well) is designed with the relatively high resistance of 200 k
for the pull-
down (on) resistors built in to the FMIN and AMIN pins, a common AM/FM local oscillator buffer can be used as
shown in the following circuit.
PD pin
Note that the charge pump output voltage is reduced when this IC, which is a 3-V system, is used to replace the
LC72131, which is a 5-V system. This means that since the loop gain is reduced, the loop filter constants, the lock time
(SD wait time), and other related parameters must be reevaluated in the end product design.
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