Overview
The LC72707E is a data demodulation IC for receiving
FM multiplex broadcasts for mobile receivers in the
DARC format. In conjunction with a bandpass filter IC
(either the LV3400M or the LV3403M), the LC72707E
can form a compact yet high-functionality FM multiplex
reception system. This IC provides built-in DRIS system
data processing decoder for Digital DJ CO.,LTD. Since
supporting all the FM multiplex frame structures (methods
A, A', B, and C) in the ITU-R recommendations, this IC is
optimal for use in radios for FM multiplex system.
Note that a contract with Digital Incorporated is required
to evaluate this IC and to produce end products that
support DRIS.
Applications
Receivers for DARC format mobile receiver FM
multiplex broadcasts
FM multiplex receiver for the worldwide DRIS system
of Digital DJ Incorporated.
Functions
MSK delay detection circuit based on a 1T delay
Error correction function based on a 2T delay (in the
MSK detector stage)
Digital PLL based clock regeneration circuit
Shift-register type 1T and 2T delay circuits
Block and frame synchronization detection circuit
Serial control data transfer based support for the A, B,
and C FM multiplex frame structures
Function for setting the number of allowable BIC errors,
the number of synchronization protection.
Error correction using (272, 190) codes
Layer 4 CRC code checking circuit
On-chip frame memory and memory control circuit for
vertical correction
7.2-MHz crystal oscillator circuit
Conforms to the DRIS format of Digital DJ Incorporated
Package Dimensions
unit: mm
3148-QFP44MA
CMOS IC
51598RM (OT) No. 5970-1/15
SANYO: QFP44MA
[LC72706E]
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
FM Multiplex Receiver IC Supporting
All Worldwide Standards
LC72707E
Ordering number : EN5970
CCB is a trademark of SANYO ELECTRIC CO., LTD.
CCB is SANYO's original bus format and all the bus
addresses are controlled by SANYO.
DRIS is an abbreviation of Digital DJ Radio
Information Services.
DRIS is an FM multiplex broadcasts mobil receiving
system which supports not only one-to-multiplex
transmission but one-to-one information trans
mission.
No. 5970-2/15
LC72707E
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
DD
max
0.3 to +7.0
V
Input voltage
V
IN
1
CE, CL, DI, RST, STNBY
0.3 to +7.0
V
V
IN
2
Pins other than V
IN
1
0.3 to V
DD
+0.3
V
Output voltage
V
OUT
1
DO
0.3 to +7.0
V
V
OUT
2
Pins other than V
OUT
1
0.3 to V
DD
+0.3
V
Output current
I
OUT
BLOCK, FLOCK, DO
0 to 4.0
mA
Allowable power dissipation
Pd max
Ta
85C
400
mW
Operating temperature
Topr
40 to +85
C
Storage temperature
Tstg
55 to +125
C
Specifications
Absolute Maximum Ratings
at Ta = 25C, V
SS
= 0 V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
DD
2.7
5.5
V
Input high-level voltage
V
IH
1
CL, CE, DI, RST, STNBY
0.7 V
DD
5.5
V
V
IH
2
MSK
0.7 V
DD
V
DD
V
Input low-level voltage
V
IL
1
Applies to the same pins as V
IH
1
V
SS
0.3 V
DD
V
V
IL
2
Applies to the same pins as V
IH
2
V
SS
0.3 V
DD
V
Oscillator frequency
F
OSC
This IC operates at frequencies within a
7.2
MHz
250 ppm precision.
With a capacitance-coupled sine wave input
V
XI
to X
IN
400
1500
mVrms
Input sensitivity
V
DD
= +4.5 V to 5.5 V
With a capacitance-coupled sine wave input
V
XI
to X
IN
400
900
mVrms
V
DD
= +2.7 V to 3.6 V
[Serial I/O
*
]
Clock low-level time
t
CL
CL
0.7
s
Clock high-level time
t
CH
CL
0.7
s
Data setup time
t
SU
CL, DI
0.7
s
Data hold time
t
HD
CL, DI
0.7
s
CE wait time
t
EL
CL, CE
0.7
s
CE setup time
t
ES
CL, CE
0.7
s
CE hold time
t
EH
CL, CE
0.7
s
Data latch change time
t
LC
CE
0.7
s
Data output time
t
DD0
DO, CL
277
555
ns
Layer 4 CRC change time
t
CRC
CRC4, CL
0.7
s
Allowable Operating Ranges
at Ta = 40 to 85C, V
SS
= 0 V
Note
*
: See the serial data timing chart.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
V
OH
1
I
O
= 1 mA, FLICK
V
DD
1.0
V
Output high-level voltage
V
OH
2
I
O
= 2 mA, BLOCK, FLOCK, INT, CLK16,
V
DD
0.4
V
DATA
V
OL
1
I
O
= 1 mA, applies to the same pins as V
OH
1
1.0
V
Output low-level voltage
V
OL
2
I
O
= 2 mA, applies to the same pins as V
OH
2
0.4
V
V
OL
3
I
O
= 2 mA, DO
0.4
V
Input high-level current
I
IH
1
V
IN
= 5.5 V, CE, CL, DI, RST, STNBY
1.0
A
I
IH
2
V
IN
= V
DD
, input pins other than I
IH
1
1.0
A
Input low-level current
I
IL
V
IN
= V
SS
, MSK, CL, CE, DI, RST, STNBY,
1
A
TP0 to TP8, TPC1 to 2, TOSEL1 to 2, TEST
Output off leakage current
I
OFF
V
O
= V
DD
, DO
5
A
Hysteresis voltage
V
HIS
MSK, CL, CE, DI, RST, STNBY
0.1 V
DD
V
Internal feedback resistor
R
f
X
IN
, X
OUT
1.0
M
Current drain
I
DD
16
25
mA
Electrical Characteristics (1)
at V
DD
= +4.5 to +5.5 V, in the allowable operating ranges
1T delay
Clock
regeneration
2T delay
LPF
LPF
MSK
correction
PN
decoding
Synchronization
regeneration
Timing
control
Error
correction
Layer 2 CRC
Output control
(CPU interface)
DRIS processing
Layer 4 CRC
Memory array
RST
STNBY
VDD
GND
1/2
Data
Address
7.2MHz
XIN
XOUT
FILCK
CRC4
CL
CE
DI
DO
INT
FLOCK
BLOCK
DATA
CLK16
MSK signal input
A08950
No. 5970-3/15
LC72707E
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
V
OH
1
I
O
= 0.5 mA, FLICK
V
DD
1.0
V
Output high-level voltage
V
OH
2
I
O
= 1 mA, BLOCK, FLOCK, INT, CLK16,
V
DD
0.4
V
DATA
V
OL
1
I
O
= 0.5 mA, applies to the same pins as V
OH
1
1.0
V
Output low-level voltage
V
OL
2
I
O
= 1 mA, applies to the same pins as V
OH
2
0.4
V
V
OL
3
I
O
= 1 mA, DO
0.4
V
Input high-level current
I
IH
1
V
IN
= 5.5 V, CE, CL, DI, RST, STNBY
1.0
A
I
IH
2
V
IN
= V
DD
, input pins other than I
IH
1
1.0
A
Input low-level current
I
IL
V
IN
= V
SS
, MSK, CL, CE, DI, RST, STNBY,
1
A
TP0 to TP8, TPC1 to 2, TOSEL1 to 2, TEST
Output off leakage current
I
OFF
V
O
= V
DD
, DO
1
A
Hysteresis voltage
VHIS
MSK, CL, CE, DI, RST, STNBY
0.1 V
DD
V
Internal feedback resistor
R
f
X
IN
, X
OUT
2.5
M
Current drain
I
DD
8
12
mA
Electrical Characteristics (2)
at V
DD
= +2.7 to +3.6 V, in the allowable operating ranges
Block Diagram
Pin Assignment
LC72707E
No. 5970-4/15
LC72707E
Pin Functions
Pin No.
Pin Name
Function
I/O
Circuit type
MSK
7
76-kHz MSK signal input (from the LV3400M/03M)
Input
Input
CL
CE
DI
26
27
28
CCB serial interface
Clock input
Data control input
Data input
RST
STNBY
TEST
32
30
44
System reset input (active low)
Standby mode (active high)
Test (Must be connected to ground during normal operation.)
TP0
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TPC1
TPC2
TOSEL1
TOSEL2
9
12
13
14
15
16
17
18
19
6
8
20
21
Must be connected to either V
DD
or V
SS
.
Output
Output
FLICK
4
Reference clock output for the LV3400M/03M
CLK16
DATA
10
11
Clock regeneration monitor
Demodulated data monitor
BLOCK
FLOCK
CRC4
INT
23
22
24
25
Outputs a high level during block synchronization.
Outputs a high level during frame synchronization.
Layer 4 CRCC check result output
External CPU interrupt signal
IC0
IC1
IC2
IC3
IC4
IC5
IC6
IC7
34
35
36
37
39
41
42
43
Internal connections. These pins must be left open.
DO
29
Data output used by the CCB serial interface
Input
Output
XIN
XOUT
1
2
System clock generation crystal oscillator element connections
--
--
V
DD
V
SS
5, 31, 38
3, 33, 40
Power supply (+2.7 to 5.5 V)
Ground
Data I/O Techniques
CCB Technique
Sanyo audio ICs input and output data using the Sanyo CCB (computer control bus) standard, which is a serial bus
format. This IC uses an 8-bit address CCB and uses the following addresses.
Data Input Timing
No. 5970-5/15
LC72707E
I/O mode
Address
Function
B0
B1
B2
B3
A0
A1
A2
A3
Input
0
1
0
1
1
1
1
1
16-bit control data input
Output
1
1
0
1
1
1
1
1
Data output for the input clock (CL)
Input
0
0
1
1
1
1
1
1
Data input (in 8-bit units) for the layer 4 CRC check circuit
Data Output Timing
Note:The DO pin is normally left open.
Since the DO pin is an n-channel open drain pin, the time required for the data to change from the low level to the high level depends on the value of
the pull-up resistor.
I/O mode determined
Internal data latching
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