Ordering number : EN6037
40299RM (OT) No. 6037-1/8
Overview
The LC72723 is an RDS (Radio Data System) signal
demodulation IC. This IC integrates a bandpass filter, the
demodulation circuit, and buffer RAM on a single chip
and can read out RDS data in slave mode operation with
the provision of an external clock input. It also supports
master mode, in which the data is read out in
synchronization with an RDS clock output provided by the
IC itself.
Functions
Bandpass filter: Switched capacitor filter (SCF)
RDS demodulation: Functions include 57kHz carrier
regeneration, clock regeneration, biphase decoding, and
differential decoding
Buffer RAM: Stores 128 bits (about 100 ms) of data.
Data output: Output can be switched between master
mode and slave mode readout.
RDS ID detection: Supports ID reset
Standby control: Stops the crystal oscillator.
Fully adjustment free.
Ratings
Operating supply voltage: 4.5 to 5.5 V
Operating temperature: 40 to 85C
Packages: DIP16 and MFP16
Package Dimensions
unit: mm
3006B-DIP16
unit: mm
3035A-MFP16
LC72723, LC72723M
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
RDS Demodulation IC
CMOS IC
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
1
8
16
9
3.0
3.4
3.65max
19.2
0.71
2.54
1.2
0.25
0.48
7.62
6.4
SANYO: DIP16
[LC72723]
1
16
8
9
10.1
0.15
0.605
1.27
0.35
0.1
1.8max
1.5
0.625
4.4
5.15
6.4
SANYO: MFP16
[LC72723M]
Pin Assignment (DIP16/MFP16)
No. 6037-2/8
LC72723, LC72723M
Block Diagram
No. 6037-3/8
LC72723, LC72723M
Pin Descriptions
Pin No.
Pin
Function
I/O
Pin circuit type
Reference voltage output (Vdda/2)
Output
1
VREF
Base band (multiplex) signal input
Input
2
MPXIN
Subcarrier output (filter output)
Output
5
FLOUT
Subcarrier input (comparator input)
Input
6
CIN
Analog system power supply (+5 V)
--
--
3
Vdda
Analog system ground
--
--
4
Vssa
Crystal element output (4.332 MHz)
Output
8
XOUT
RDS data output
Output
14
RDDA
RDS clock output (master mode)
RDS clock input (slave mode)
I/O
15
RDCL
RDS ID/ready output (Active low)
Output
--
--
--
--
16
RDS-ID/READY
Digital system power supply (+5 V)
11
Vddd
Digital system ground
10
Vssd
Test input
7
TEST
Crystal element input (or external reference signal input)
Input
9
XIN
Readout mode setting (0: master, 1: slave)
12
MODE
RDS ID and RAM reset (Active high logic)
13
RST
No. 6037-4/8
LC72723, LC72723M
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
DD
max
Vddd, Vdda
*
0.3 to 7.0
V
V
IN
1 max
TEST, MODE, RST
0.3 to +7.0
V
Maximum input voltage
V
IN
2 max
XIN, RDCL
0.3 to Vddd + 0.3
V
V
IN
3 max
MPXIN, CIN
0.3 to Vdda + 0.3
V
Vo1 max
RDS-ID (READY)
0.3 to +7.0
V
Maximum output voltage
Vo2 max
XOUT, RDDA, RDCL
0.3 to Vddd + 0.3
V
Vo3 max
FLOUT
0.3 to Vdda + 0.3
V
Maximum output current
Io1 max
XOUT, FLOUT, RDDA, RDCL
+3.0
mA
Io2 max
RDSID (READY)
+20.0
mA
Allowable power dissipation
Pd max
(Ta
85C)
DIP16 : 300
mW
MFP16 : 140
mW
Operating temperature
Topr
40 to +85
C
Storage temperature
Tstg
55 to +125
C
Specifications
Absolute Maximum Ratings
at Ta = 25C, Vssd = Vssa = 0 V
*
: Note that Vdda must be less than or equal to Vddd + 0.3 V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
DD
Vddd, Vdda: Vddd = Vdda
4.5
5.0
5.5
V
High-level input voltage
V
IH
1
TEST, MODE, RST
07 Vddd
6.5
V
V
IH
2
RDCL
0.7 Vddd
Vddd
V
Low-level input voltage
V
IL
TEST, MODE, RST, RDCL
0
0.3 Vddd
V
Output voltage
Vo1
RDDA, RDCL
Vddd
V
Vo2
RDSID (READY)
6.5
V
V
IN
1
MPXIN
f = 57 2 KHz
50
mVrms
Input amplitude
V
IN
2
100% modulation, composite
100
mVrms
VX
IN
XIN
400
1500
mVrms
Guaranteed oscillator operating range
Xtal
XIN, XOUT: C1
120
4.332
MHz
Crystal oscillator frequency deviation
TXtal
XIN, XOUT: Fo = 4.332 MHz
100
ppm
RDCL setup time
t
CS
RDCL, RDDA
0
s
RDCL high-level time
t
CH
RDCL
0.75
s
RDCL low-level time
t
CL
RDCL
0.75
s
Data output time
t
DC
RDCL, RDDA
0.75
S
READY output time
t
RC
RDCL, READY
0.75
s
READY low-level time
t
RL
READY
107
ms
Allowable Operating Ranges
at Ta = 40 to +85C, Vssd = Vssa = 0 V, Vddd = Vdda
No. 6037-5/8
LC72723, LC72723M
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Input resistance
Rmpxin
MPXIN-Vssa: f = 57 KHz
23
K
Rcin
CIN-Vssa: f = 57 KHz
100
K
Internal feedback resistance
Rf
XIN
1.0
M
Center frequency
fc
FLOUT
56.5
57.0
57.5
KHz
3dB bandwidth
BW3dB
FLOUT
2.5
3.0
3.5
KHz
Gain
Gain
MPXIN-FLOUT: f = 57 KHz
28
31
34
dB
Att1
FLOUT:
f = 7 KHz
30
dB
Stop band attenuation
Att2
FLOUT: f < 45 KHz, f > 70 KHz
40
dB
Att3
FLOUT: f < 20 KHz
50
dB
Reference voltage output
Vref
Vref: Vdda = 5 V
2.5
V
Hysteresis
V
HIS
TEST, MODE, RST, RDCL
0.1 Vddd
V
Low-level output voltage
V
OL1
RDDA, RDCL : I = 2 mA
0.4
V
V
OL2
RDS-ID (READY): I = 8 mA
0.4
V
High-level output voltage
V
OH
RDDA, RDCL : I = 2 mA
Vddd 0.4
V
High-level input current
I
IH
1
TEST, MODE, RST, RDCL : V
I
= 6.5 V
5.0
A
I
IH
2
XIN: V
I
= Vddd
2.0
11
A
Low-level input current
I
IL
1
TEST, MODE, RST, RDCL : V
I
= 0 V
5.0
A
I
IL
2
XIN: V
I
= 0 V
2.0
11
A
Output off leakage current
I
OFF
RDS-ID (READY): V
O
= 6.5 V
5.0
A
Current drain
Idd
Vddd + Vdda
8
mA
Electrical Characteristics
at Ta = 40 to +85C, Vssd = Vssa = 0 V, Vddd = Vdda
Inputs and Outputs
Note: The RDS-ID (READY) pin is an n-channel open-drain output, and data is read out by connecting a pull-up resistor.
TEST
MODE
Circuit operating mode
RDCL pin
RDS-ID/READY pin
0
0
Master mode
Clock output
RDS-ID output
0
1
Slave mode
Clock input
READY output
1
0
Standby mode (crystal oscillator stopped)
--
--
1
1
IC test mode (Cannot be set by users.)
--
--
RST pin
RST = 0
Normal operation
RST = 1
The RDS-ID and demodulation circuits are cleared, and (in slave mode) the READY state and memory are cleared.
RDS ID/READY pin
Master mode RDS-ID output (active low)
Slave mode
Readout data ready output (active low)
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