Ordering number : ENN6124

D2200RM (OT) No. 6124-1/17

Overview

The LC73815M is a telephone IC that integrates on a
single chip both an FSK modem, which receives pre-call
reporting services such as caller ID and performs other
data send/receive functions, and a DTMF receiver circuit
that can handle remote control functions for telephone
answering machine applications.

Applications

Pre-call reporting services, such as Caller ID, reception,
other data send/receive functions, and remote control of
telephone answering machine applications.

Features

· FSK modem (1200 bps)
· Circuit that automatically generates the start and stop

bits used during FSK modulation

· Circuit that automatically generates the continuous mark

signal at the start of transmission in FSK modulation
mode

· Circuit that automatically inserts the idle bits (5 or more

bits) used in FSK modulation mode

· Built-in clock synchronous I/O shift register
· Detection of all 16 DTMF signals

· Digital guard timer circuits for the DTMF signal

detection signal pins

· Operating voltage range: 4.5 to 5.5 V
· Low-power mode that can contribute to energy savings
· 36-pin package (MFP-36S)

Package Dimensions

unit: mm

3129-MFP36S

0.25

15.3

0.85

0.4

0.8

2.5max

2.25

0.1

7.9

9.2

10.5

0.65

SANYO: MFP36S

[LC73815M]

LC73815M

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

FSK 1200 Baud Modem and DTMF Receiver

CMOS IC

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

Parameter

Symbol

Conditions

Ratings

Unit

Maximum supply voltage

max

0.3 to +7.0

Maximum input voltage

max

0.3 to V

+ 0.3

Maximum input current

max

10 to +10

Allowable power dissipation

Pd max

70°C

250

Operating temperature

Topr

30 to +70

°C

Storage temperature

Tstg

40 to +125

°C

Specifications

Absolute Maximum Ratings

at Ta = 25°C, V

= 0 V

No. 6124-2/17

LC73815M

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

Supply voltage

4.5

5.0

5.5

(OP1)

= 5.0 V, when the DTMF receiver is used.

5.5

Operating current drain

(OP2)

= 5.0 V, during FSK reception

7.5

(OP3)

= 5.0 V, during FSK transmission

7.5

Quiescent current

(ST)

RES pin = low

µA

Oscillator frequency

OSC

3.5757965

3.579545

3.583125

MHz

Allowable Operating Ranges

at Ta = 30 to +70°C, V

= 0 V

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

High-level input voltage

Pins other than ACK and RES

0.7 V

IHS

The ACK and RES input pins

0.8 V

Low-level input voltage

Pins other than ACK and RES

0.3 V

ILS

The ACK and RES input pins

0.2 V

Input leakage current

= V

µA

= GND

µA

High-level output current

OUT

= V

0.4 V

0.8

0.4

Low-level output current

OUT

= 0.4 V

1.0

2.5

DC Electrical Characteristics

at Ta = 25°C, V

= 5 V, V

= 0 V

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

Input signal detection level

FSK reception

dBm

Reception data transmission speed

FSK

1188

1200

1212

baud

Reception frequency

FSK (Mark)

1180

1250

1320

FSK (Space)

2070

2150

2280

ACK

MHz

Shift register data shift speed

CKL

500

CKH

500

External oscillator input

EXTOI

0.5

Vrms

B/V = H

FSK (Mark)

1200

FSK transmission frequency

(BELL202) FSK (Space)

2204

B/V = L

FSK (Mark)

1300

(V.23)

FSK (Space)

2101

FSK output amplitude

0.5

0.8

Vp-p

Transfer rate

1200

bps

FSK modulation delay time

DDEM

See the timing chart.

0.83

Data output setup time

SDATA

See the timing chart.

0.42

0.83

DR output setup time

SDR

See the timing chart.

2.2

3.3

µs

ACK - DATA setup time

SCKD

See the timing chart.

300

ACK - DR setup time

SCKDR

See the timing chart.

1.1

9.0

µs

AC Electrical Characteristics 1 (FSK reception/transmission)

at Ta = 25°C, V

= 5 V, V

= 0 V, f

OSC

= 3.579545 MHz

Conditions: For the dBm ratings, 0 dBm is defined to be a 1 mW output into a 600

load.

No. 6124-3/17

LC73815M

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

Input signal detection level

1, 2, 3, 5, 6, 9

dBm

Allowable twist

2, 3, 6, 9, 11

±10

Frequency detection band

2, 3, 5, 9

±1.5% ±2 Hz

Frequency non-detection band

2, 3, 5

±3.5

Allowable third tone

2, 3, 4, 5, 9, 10

Allowable dial tone

2, 3, 4, 5, 8, 9, 10

Allowable noise

2, 3, 4, 5, 7, 9, 10

Input signal invalid time

REC

See the timing chart.

Input signal valid time

REC

See the timing chart.

Interdigit pause invalid time

See the timing chart.

Interdigit pause valid time

See the timing chart.

Guard time

(Present)

GDP

See the timing chart.

(Absent)

GDA

See the timing chart.

Input signal

(Present)

See the timing chart.

detection time

(Absent)

See the timing chart.

0.5

AC Electrical Characteristics 2 (DTMF reception)

at Ta = 25°C, V

= 5 V, V

= 0 V, f

OSC

= 3.579545 MHz

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

Input offset voltage

+25

Input offset current

±100

Power supply rejection ratio

PSRR

1 kHz

Common-mode rejection ratio

CMRR

Open loop voltage gain

0 dB bandwidth

1.5

MHz

Maximum output voltage

100 k

0.5

Vp-p

Allowable load capacitance

100

Allowable load resistance

Common-mode input voltage range

No load

3.0

Vp-p

Input Amplifier Characteristics

at Ta = 25°C, V

= 5 V, V

= 0 V, f

OSC

= 3.579545 MHz

Conditions

1. The 0 dBm level is defined to be a 1 mW output into a 600

load.

2. All combinations of the 16 DTMF signals.
3. A 40 ms DTMF signal period, and a 40 ms pause period
4. The nominal frequencies are used for DTMF signals.
5. The signal levels of the low group and high group signals are identical.
6. The tolerance for DTMF signal frequency is within ±1.5% or ±2 Hz.
7. Gaussian noise with a band of 0 to 3 kHz
8. Dial tone pair of 350 and 440 Hz
9. The error ratio is under 1 error in 10,000 operations.
10. Referenced to the frequency component with the lowest level in the DTMF signal.
11. Twist: the ratio of the high group tone level to the low group tone level

Note: This IC contains a Switched Capacitor Filter (SCF) circuit on chip.

Since the internal SCF clock frequency is OSC/56 (= 63.92 kHz), a power supply related noise whose frequency is OSC/56 multiplied by some integer

3 kHz will prevent the ratings shown above from being achieved.

Therefore, care must be taken for the power supply related noise.

No. 6124-4/17

LC73815M

Pin Functions

Pin No.

I/O

Function

Differential operational amplifier noninverting input

Differential operational amplifier inverting input

Differential operational amplifier output

AGND

IC internal analog ground output

FSKOUT

FSK signal output. This is an npn transistor emitter-follower output.

AGCO

Connect to pin 8 through a capacitor. Make no other connections to this pin.

FSKIN

Connect to pin 7 through a capacitor. Make no other connections to this pin.

AGND

IC internal analog ground input

TESTI

IC test input. This pin must be tied low during normal operation.

B/V

Transmission FSK frequency switching input (Bell 202, V.23)
High: Bell 202, Low: V.23

OSCIN

Connect a 3.579545 MHz oscillator element between these pins. An external 3.579545 MHz may also be supplied.

OSCOUT

(Consult oscillator element manufacturers concerning the combination of their products with this IC.)

Ground

Power supply. Connect a capacitor of at least 0.1 µF between this pin and GND.

S/R

FSK send/receive mode switching input. High: Send, Low: Receive.

F/D

FSK modem/DTMF receiver operating mode switching input.
High: FSK modem, Low DTMF receiver.

DATA

I/O

Serial output of the FSK or DTMF received data in synchronization with the ACK input pin.
Also used for serial input of FSK transmission data.

ACK

Synchronization clock input for serial data readout and write.

In DTMF receiver mode (EST), a high level indicates the presence of a valid DTMF signal. Monitor this pin (or the STD
pin), and, after an appropriate wait period has passed, read out the data by applying four pulses to the ACK pin. Note that
the received DTMF data is latched internally to the IC on the rising edge of this pin.

EST/DR

In FSK reception mode (DR), this pin outputs a high level when the received data is valid, and goes low after the received
data has been read out by applying pulse inputs to the ACK pin.
In FSK transmission mode (DR), this pin indicates the input ready state for transmission data. A high level indicates that
the IC is ready to accept the input of transmission data.

In DTMF receiver mode (STD), a high level indicates the presence of a valid DTMF signal. The rise of this signal occurs

STD/DR

later than that of the EST signal. However, this signal is not sensitive to burst waveforms.
In FSK mode, this pin functions identically to pin 26.

RDO

FSK demodulated signal output

RES

Reset input. Apply a low level to this pin when power is first applied and after low-power mode. At least 1 µs of low-level
input is required for the reset operation.

This input controls DR during FSK reception. DR is invalid if this input is high in FSK reception mode. If this pin is low
(note that it is pulled down internally) DR is enabled. This pin also functions to select continuous mark signal generation

DRCNT

at the start of transmission mode in FSK transmission mode.
Low: If the S/R pin is high, continuous mark signals are generated automatically. FSK data will be output following the
continuous mark signals generated after the CPU inputs another FSK data to this pin.
High: FSK is not output until the CPU inputs the next FSK data, even if the S/R pin is set high.

TEST01

IC test output pin

32, 33

TEST02

IC test output pin

35, 36

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