Ordering number : EN
*
5965
40299RM (OT) No. 5965-1/25
Overview
The LC74792/JM is a CMOS IC that provides PDC, VPS,
and UDT data acquisition functions. The LC74792/JM
supports microprocessor control of its operating modes
and microprocessor read out of data acquired in any of its
operating modes.
Features
VPS data acquisition (5 or 11 to 15 bytes)
VPS: Video Program System
PDC (8/30/2) data acquisition (13 to 25 bytes)
PDC: Program Delivery Control
UDT (8/30/1) data acquisition (13 to 25 bytes)
UDT: Unified Date and Time
Header (X/00) data acquisition (14 to 45 bytes)
Status display (8/30/1, 8/30/2) data acquisition (26 to
45 bytes)
Automatic VPS/PDC discrimination mode
Built-in AFC and sync separator circuits
Synchronization discrimination circuit
Package Dimensions
unit: mm
3067-DIP24S
unit: mm
3112-MFP24S
0.48
3.25
3.3
3.9max
0.51min
21.2
0.81
1.78
0.25
7.62
6.4
1
12
24
13
0.95
Preliminary
SANYO: DIP24S
[LC74792]
1
12
24
13
12.6
0.8
1.0
0.15
0.35
5.4
6.35
7.6
0.625
1.8max
1.5
0.1
SANYO: MFP24S
[LC74792JM]
LC74792, 74792JM
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
VPS / PDC Slicer IC
CMOS IC
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
Pin Assignment
No. 5965-2/25
LC74792, 74792JM
No. 5965-3/25
LC74792, 74792JM
Pin Functions
Pin No.
Pin
Function
Description
1
V
SS
1
Ground
Digital system ground
2
Xtal
IN
Crystal oscillator connections
Connections for the crystal element and capacitors that form the crystal oscillator. Also
3
Xtal
OUT
used for external clock input (fsc, 2fsc, or 4fsc).
4
CTRL1
Crystal element switching
Switches between external clock input mode and crystal oscillator mode. Set this pin low
for crystal oscillator, and high for external clock input.
5
CS
Enable input pin
Enable input pin (hysteresis input)
6
SIO
Data input/output pin
Data input/output pin (hysteresis input)
7
SCLK
Clock input pin
Clock input pin (hysteresis input)
External synchronizing signal presence/absence discrimination status output.
8
SYNC
JDG
External synchronizing signal
A high level is output when synchronizing signals are present.
discrimination output
This pin outputs the crystal oscillator clock when the RST pin is low.
(This reset state output can be disabled with command input.)
9
Hout
Horizontal synchronizing signal output
Horizontal synchronizing signal output
10
V
SS
2
Ground
Ground. (VCO circuit ground)
11
CP
OUT
Charge pump output
Charge pump output. Connect a low-pass filter to this pin.
12
VCO
IN
Oscillator control voltage input
VCO oscillation control voltage input
13
VCOR
Oscillator range adjustment
VCO oscillation range adjustment resistor connection
14
DAV
Data acquisition output
Outputs a low level when PDC/VPS data has been discriminated
15
V
DD
2
Power supply (+5 V)
Power supply (+5 V) (VCO system power supply)
16
SYN
IN
Sync separator circuit input
Internal sync separator circuit video signal input
17
SEPC
Slice level output
Slice level verification
18
SEP
OUT
Composite synchronizing signal output
Internal sync separator circuit composite synchronizing signal output
Inputs the vertical synchronizing signal by integrating the SEP
OUT
pin output signal.
19
SEP
IN
Vertical synchronizing signal input
Applications must connect the SEP
OUT
pin to this pin through an integration circuit. If
unused, connect this pin to VDD1. (This pin is enabled when CTRL2 is high.)
Vertical synchronizing signal output
20
Vout
Vertical synchronizing signal output
This pin outputs the VCO clock when the RST pin is low.
(This reset state output can be disabled with command input.)
Controls whether or not the VSYNC vertical synchronizing signal is input to the SEP
IN
21
CTRL2
SEP
IN
input control
input.
When low: The VSYNC signal is not input. (The internal vertical separation circuit is used.)
When high: The VSYNC signal is input.
22
CDLR
Clock phase adjustment
Connection for the clock phase adjustment resistor
23
RST
Reset input
System reset input.
A pull-up resistor is built in. (This input has hysteresis characteristics.)
24
V
DD
1
Power supply (+5 V)
Power supply. (+5 V: digital system power supply)
No. 5965-4/25
LC74792, 74792JM
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
V
DD
max
V
DD
1 and V
DD
2
V
SS
0.3 to V
SS
+ 7.0
V
Input voltage
V
IN
All input pins
V
SS
0.3 to V
DD
1 + 0.3
V
Output voltage
V
OUT
SIO, SYNCJDG, SEPOUT, DAV, HOUT, and VOUT
V
SS
0.3 to V
DD
1 + 0.3
V
Allowable power dissipation
Pd max
Ta = 25C
350
mW
Operating temperature
Topr
30 to +70
C
Storage temperature
Tstg
40 to +125
C
Specifications
Absolute Maximum Ratings
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
DD
1
V
DD
1 and V
DD
2
4.5
5.0
5.5
V
V
IH
1
CS, SIO and SCLK
0.8 V
DD
1
5.5
V
High-level input voltage
V
IH
2
RST
0.8 V
DD
1
V
DD
1 + 0.3
V
V
IH
3
CTRL1 and CTRL2
0.7 V
DD
1
V
DD
1 + 0.3
V
Low-level input voltage
V
IL
1
RST, CS, SIO and SCLK
V
SS
0.3
0.2 V
DD
1
V
V
IL
2
CTRL1 and CTRL2
V
SS
0.3
0.3 V
DD
1
V
Pull-up resistance
R
PU
RST
25
50
90
k
Composite video signal input voltage
V
IN
1
SYN
IN
V
DD
1 = 5 V
1.5
2.0
2.5
Vp-p
Input voltage
V
IN
2
Xtal
IN
(in external clock input mode)
V
DD
1 = 5 V
0.10
5.0
Vp-p
fin = fsc, 2fsc, or 4fsc
F
OSC
1
The Xtal
IN
and Xtal
OUT
oscillator pins (4fsc: PAL)
17.734
MHz
Oscillator frequency
F
OSC
2
The Xtal
IN
and Xtal
OUT
oscillator pins (2fsc: PAL)
8.867
MHz
F
OSC
3
The Xtal
IN
and Xtal
OUT
oscillator pins (fsc: PAL)
4.433
MHz
Recommended Operating Conditions
Note that adequate measure must be taken to prevent noise from entering the Xtal
IN
pin when it is used in clock input mode.
No. 5965-5/25
LC74792, 74792JM
Parameter
Symbol
Applicable pins
Conditions
Ratings
Unit
min
typ
max
Output off leakage current
Ileak2
DAV and SIO
1
A
High-level output voltage
V
OH
1
SEPOUT, CPOUT, SYNCJDG,
V
DD
1 = 4.5 V,
3.5
V
HOUT, and VOUT
I
OH
= 1.0 mA
V
OL
1
SEPOUT, CPOUT, SYNCJDG,
V
DD
1 = 4.5 V
1.0
V
Low-level output voltage
DAV, HOUT, and VOUT
I
OL
= 1.0 mA
V
OL
2
SIO
V
DD
1 = 5.0 V
0.4
V
I
OL
= 3.0 mA
I
IH
RST, SIO, SCLK, CTRL1, CTRL2,
V
IN
= V
DD
1
1
A
Input current
VCOIN
I
IL
SIO, SCLK, CTRL1, CTRL2,
V
IN
= V
SS
1
1
A
VCOIN
With all outputs open
Operating current drain
I
DD
1
V
DD
1 and V
DD
2
and a 17.734 MHz
40
mA
crystal
Electrical Characteristics
at Ta = 30 to +70C, V
DD
1 = 5 V unless otherwise specified.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Minimum input pulse width
tw (sclk)
SCLK
200
ns
tw (cs)
CS pin (while CS = "H")
1
s
Data setup time
tsu (cs)
CS
200
ns
tsu (sin)
SIN
200
ns
Data setup time
th (cs)
CS
2
s
th (sin)
SIN
200
ns
1-word write time
tword
8-bit data write time
4.2
s
twt
RAM data write time
1
s
Timing Characteristics
[Write] (Refer to Figure 1)
at Ta = 30 to +70C, V
DD
1 = 50.5 V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
t
CKCY
SCLK
2
s
Minimum input pulse width
t
CKL
SCLK
1
s
t
CKH
SCLK
1
s
Data setup time
t
ICK
SCLK
10
s
Output delay time
t
CKO
SIO
0.5
s
[Read] (Refer to Figure 2) (in case of N-ch open-drain type)
at Ta = 30 to +70C, V
DD
1 = 50.5 V
Note: In case of CMOS output type, depends on OSD timing.
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