Overview
The LC74794 and LC74794M are CMOS LSIs for on-
screen display, a function that displays characters and
patterns on a TV screen under microprocessor control.
They feature a built-in PDC/VPS/UDT interface circuit.
These LSIs support 12
18 dot characters and can display
12 lines by 24 characters of text.
Features
Display format: 24 characters by 12 rows (Up to 288
characters)
Character format: 12 (horizontal)
18 (vertical) dots
Character sizes: Three sizes each in the horizontal and
vertical directions
Characters in font: 128
Initial display positions: 64 horizontal positions and 64
vertical positions
Blinking: Specifiable in character units
Blinking types: Two periods supported: 1.0 second and
0.5 second
Blanking: Over the whole font (12
18 dots)
Background color
-- Background coloring: 8 colors (internal synchronization
mode): 4fsc
-- Background coloring: 6 colors (internal synchronization
mode): 2fsc
-- Blue background only: NTSC
Line background color
-- Can be set for 3 lines
-- Line background coloring: 8 colors (internal synchro-
nization mode): 4fsc
-- Line background coloring: 6 colors (internal synchro-
nization mode): 2fsc
External control input: 8-bit serial input format
On-chip sync separator and AFC circuits
PDC/VPS/UDT interface circuit
Composite video output in the PAL or NTSC format
Package Dimensions
unit: mm
3196-DIP30SD
unit: mm
3216A-MFP30S
CMOS LSI
Ordering number : EN
*
5557
22897HA (OT)/No. 5557-1/30
Preliminary
SANYO: DIP30SD
[LC74794]
SANYO: MFP30S
[LC74794M]
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
On-Screen Display Controller LSI
LC74794, 74794M
Pin Assignment
No. 5557-2/30
LC74794, 74794M
Pin Functions
Pin no.
Pin
Function
Notes
1
V
SS
1
Ground
Ground connection (digital system ground)
2
Xtal
IN
Crystal oscillator
These pins are used either to connect a crystal and capacitor to form an external crystal
3
Xtal
OUT
(MUTE input)
oscillator to generate internal synchronizing signals, or to input an external clock signal (2fsc
(MUTE)
or 4fsc). As a mask option, the XtalOUT pin can be set to function as the MUTE input pin.
When the MUTE pin is set low, the video output is held at the pedestal level. (A pull-up
resistor is built in so the input has hysteresis characteristics.)
Switches the mode between external clock input and crystal oscillator operation. A low level
4
CTRL1
Crystal oscillator input switching
selects crystal oscillator operation and a high level selects external clock input. As a mask
(CHABLK) (CHABLK output)
option, the CTRL1 input pin can be set to function as the CHABLK (character border)
output. This is a 3-value output.
5
CS2
Enable input 2
PDC/VPS data output enable input. Data output is enabled by a low-level input. (A pull-up
resistor is built in so the input has hysteresis characteristics.)
6
SCLK2
Clock input 2
Clock input for PDC/VPS data output
(A pull-up resistor is built in so the input has hysteresis characteristics.)
7
DOUT
Data output
PDC/VPS data output
(This is either an n-channel open-drain output or a CMOS output.)
Outputs the state of the external synchronizing signal presence/absence judgment.
8
SYNC
JDG
External synchronizing signal judgment
Outputs a high level when synchronizing signals are present.
output
Outputs the crystal oscillator clock when CS1 is low and RST is low. (This signal is not
output on command resets.)
Continued on next page.
No. 5557-3/30
LC74794, 74794M
Continued from preceding page.
Pin no.
Pin
Function
Notes
Enable input for OSD serial data input
9
CS1
Enable input 1
Serial data input is enabled by a low-level input.
(A pull-up resistor is built in so the input has hysteresis characteristics.)
10
SCLK1
Clock input 1
Serial data clock input
(A pull-up resistor is built in so the input has hysteresis characteristics.)
11
SIN1
Data input 1
Serial data input (A pull-up resistor is built in so the input has hysteresis characteristics.)
12
V
DD
2
Power supply
Composite video signal level adjustment power supply (analog system power supply)
13
CP
OUT
Charge pump output
The charge pump output. Connect a low-pass filter to this pin.
14
VCO
IN
Oscillator control voltage input
VCO control voltage input
15
V
SS
3
Ground
Ground (VCO ground)
16
V
DD
3
Power supply (+5 V)
Power supply (+5 V: VCO power supply)
17
VCO
R
Oscillator range adjustment
Connection for the VCO range adjustment resistor
18
DAV
Data present output
Outputs a low level when PDC/VPS data has been received.
19
CV
OUT
Video signal output
Composite video signal output
20
V
SS
2
Ground
Ground (analog system ground)
21
CV
IN
Video signal input
Composite video signal input
22
CV
CR
Video signal input
SECAM chrominance signal input
23
V
DD
1
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
24
SYN
IN
Sync separator circuit input
Internal sync separator circuit video signal input
25
SEPC
Sync separator circuit adjustment
Internal sync separator circuit adjustment input
Composite synchronizing signal output for the built-in sync separator circuit. Can be
26
SEP
OUT
Composite synchronizing signal output
switched to function as an output for the signal (high or ST. pulse) due to MOD0 by setting
SEL0 high.
Inputs the vertical synchronizing signal created by integrating the SEP
OUT
pin output
27
SEP
IN
Vertical synchronizing signal input
signal.
An integration circuit must be connected to the SEP
OUT
pin. This pin must be tied to V
DD
1
if unused.
28
CDLR
Background color phase adjustment
Background color phase adjustment resistor connection
29
RST
Reset input
System reset input
A pull-up resistor is built in so the input has hysteresis characteristics.
30
V
DD
1
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
No. 5557-4/30
LC74794, 74794M
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
V
DD
V
DD
1 and V
DD
2
V
SS
0.3 to V
SS
+ 7.0
V
Input voltage
V
IN
All input pins
V
SS
0.3 to V
DD
+ 0.3
V
Output voltage
V
OUT
DAV, DOUT, SEP
OUT
, and SYNC
JDG
V
SS
0.3 to V
DD
+ 0.3
V
Allowable power dissipation
Pd max
350
mW
Operating temperature
Topr
30 to +70
C
Storage temperature
Tstg
40 to +125
C
Specifications
Absolute Maximum Ratings
at Ta = 25C
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
DD
1
V
DD
1 and V
DD
2
4.5
5.0
5.5
V
V
DD
2
V
DD
2
5.5
5.0
1.27 V
DD
1
V
V
IH
1
RST, CS1, CS2, SIN1, SCLK1, SCLK2,
0.8 V
DD
1
V
DD
1 + 0.3
V
Input high-level voltage
and MUTE
V
IH
2
CTRL1
0.7 V
DD
1
V
DD
1 + 0.3
V
V
IL
1
RST, CS1, CS2, SIN1, SCLK1, SCLK2,
V
SS
0.3
0.2 V
DD
1
V
Input low-level voltage
and MUTE
V
IL
2
CTRL1
V
SS
0.3
0.3 V
DD
1
V
Pull-up resistance
R
PU
RST, CS1, CS2, SIN1, SCLK1, SCLK2,
25
50
90
k
and MUTE
Composite video signal input voltage
V
IN
1
CV
IN
and CV
CR
; V
DD
1 = 5 V
2.0
Vp-p
V
IN
2
SYN
IN
; V
DD
1 = 5 V
1.5
2.0
2.5
Vp-p
Input voltage
V
IN
3
Xtal
IN
(in external clock input mode)
0.10
5.0
Vp-p
fin = 2 fsc or 4 fsc ; V
DD
1 = 5 V
Oscillator frequency
F
OSC
1
Xtal
IN
and Xtal
OUT
oscillator pins (2 fsc: PAL)
8.867
MHz
F
OSC
2
Xtal
IN
and Xtal
OUT
oscillator pins (4 fsc: PAL)
17.734
MHz
Allowable Operating Ranges
at Ta = 30 to +70C
Note: When the Xtal
IN
pin is used in clock input mode, extreme care must be taken to prevent noise from entering the input signal.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Input off leakage current
I
leak
1
CV
IN
and CV
CR
1
A
Output off leakage current
I
leak
2
CV
OUT
1
A
Output high-level voltage
V
OH
1
DAV, DOUT, SEP
OUT
, CP
OUT
, SYNC
JDG
;
3.5
V
V
DD
1 = 4.5 V, I
OH
= 1.0 mA
Output low-level voltage
V
OL
1
DAV, DOUT, SEP
OUT
, CP
OUT
, SYNC
JDG
;
1.0
V
V
DD
1 = 4.5 V, I
OL
= 1.0 mA
CHABLK ; V
DD
1 = 5.0 V
H
3.3
5.0
V
Three-value output voltage
V
O
M
1.8
2.3
V
L
0
0.8
V
RST, CS1, CS2, SIN, SCLK1, SCLK2,
I
IH
CTRL1, MUTE, SEP
IN
, and VCO
IN
1
A
Input current
V
IN
= V
DD
1
I
IL
CTRL1, SEP
IN
, and VCO
IN
; V
IN
= V
SS
1
1
A
I
DD
1
V
DD
1; with all outputs open
40
mA
Operating current drain
Xtal : 17.734 MHz, VCO : 27 MHz
I
DD
2
V
DD
2; V
DD
2 = 5 V
20
mA
CV
OUT
; V
DD
1 = 5.0 V
0.80
V
SYNC level
V
SN
V
DD
2 = 5.0 V
1.00
V
1.30
V
CV
OUT
; V
DD
1 = 5.0 V
1.37
V
Pedestal level
V
PD
V
DD
2 = 5.0 V
1.57
V
1.87
V
CV
OUT
; V
DD
1 = 5.0 V
1.07
V
Color burst low level
V
CBL
V
DD
2 = 5.0 V
1.27
V
1.57
V
Electrical Characteristics
at Ta = 30 to +70C, V
DD
1 = 5 V unless otherwise specified.
Continued on next page.
No. 5557-5/30
LC74794, 74794M
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
CV
OUT
; V
DD
1 = 5.0 V
1.67
V
Color burst high level
V
CBH
V
DD
2 = 5.0 V
1.87
V
2.17
V
CV
OUT
; V
DD
1 = 5.0 V
1.23 (1.16)
V
Background color low level
V
RSL
V
DD
2 = 5.0 V
1.43 (1.36)
V
1.73 (1.66)
V
CV
OUT
; V
DD
1 = 5.0 V
2.37 (2.01)
V
Background color high level
V
RSH
V
DD
2 = 5.0 V
2.57 (2.21)
V
2.87 (2.51)
V
CV
OUT
; V
DD
1 = 5.0 V
1.50
V
Frame level 0
V
BK
0
V
DD
2 = 5.0 V
1.70
V
2.00
V
CV
OUT
; V
DD
1 = 5.0 V
2.08
V
Frame level 1
V
BK
1
V
DD
2 = 5.0 V
2.28
V
2.58
V
CV
OUT
; V
DD
1 = 5.0 V
2.65
V
Character level
V
CHA
V
DD
2 = 5.0 V
2.85
V
3.15
V
Continued from preceding page.
Notes:
When the sync level is 0.8 V.
When the sync level is 1.0 V.
When the sync level is 1.3 V.
The values in parentheses for the background color high and low levels are the values for a blue background.
Note: Timings follow those for OSD write when the CMOS output circuit is used.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Minimum input pulse width
t
W(SCLK)
SCLK1
200
ns
t
W(CS1)
CS1 (The period when CS1 is high)
1
s
Data setup time
t
SU(CS1)
CS1
200
ns
t
SU(SIN)
SIN1
200
ns
Data hold time
t
h(CS1)
CS1
2
s
t
h(SIN)
SIN1
200
ns
One word write time
t
word
The time to write 8 bits of data
4.2
s
t
wt
The RAM data write time
1
s
Timing Characteristics
at Ta = 30 to +70C, V
DD
1 = 5 0.5 V
OSD write (See Figure 1.)
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
t
CKCY
SCLK2
2
s
Minimum input pulse width
t
CKL
SCLK2
1
s
t
CKH
SCLK2
1
s
Setup time
t
ICK
SCLK2
10
s
Output delay time
t
CKO
DOUT
0.5
s
PDC/VPS reads (For the n-channel open-drain output circuit. See Figure 2.)
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