Overview
The LC74798 and LC74798M are on-screen display
controller CMOS ICs that display characters and patterns
on the TV screen under microprocessor control. These ICs
include a built-in PDC/VPS/UDT interface circuit.
Features
Display format: 24 characters by 12 rows (Up to 288
characters)
Character format: 12 (horizontal)
18 (vertical) dots
Character sizes: Three sizes each in the horizontal and
vertical directions
Characters in font: 128
Initial display positions: 64 horizontal positions and
64 vertical positions
Blinking: Specifiable in character units
Blinking types: Two periods supported: 1.0 second and
0.5 second
Blanking: Over the whole font (12
18 dots)
Background color
-- 8 colors (internal synchronization mode): 4fSC
-- 6 colors (internal synchronization mode): 2fSC
-- Blue background only: NTSC
Line background color
-- Three lines can be set up.
-- 8 line background colors (in internal synchronization
mode): 4fSC
-- 6 line background colors (in internal synchronization
mode): 2fSC
External control input: 8-bit serial input format
On-chip sync separator and AFC circuits
On-chip PDC/VPS/UDT interface circuit
Video outputs: PAL and NTSC format composite video
outputs
Package: DIP30SD (400 mil)
MFP30S (375 mil)
Package Dimensions
unit: mm
3193-DIP30SD
unit: mm
3216-MFP30S
CMOS IC
51898RM (OT) No. 5833-1/32
SANYO: DIP30SD
[LC74798]
SANYO: MFP30S
[LC74798M]
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
On-Screen Display Controller IC
LC74798, 74798M
Ordering number : EN5833
Pin Assignment
No. 5833-2/32
LC74798, 74798M
No. 5833-3/32
LC74798, 74798M
Pin Descriptions
Pin No.
Pin name
Function
Notes
Ground
Ground connection (digital system ground)
1
V
SS
1
Crystal oscillator
(MUTE input)
These pins are used either to connect the crystal and capacitors used to form an external
crystal oscillator circuit to generate the internal synchronizing signals, or to input an
external clock signal (2fsc or 4fsc). As a mask option, the Xtal
OUT
pin can be set to
function as the MUTE input pin. When this pin is set low, the video output is held at the
pedestal level. (A pull-up resistor is built in and the input has hysteresis characteristics.)
Crystal oscillator input switching
(CHABLK output)
Switches the mode between external clock input and crystal oscillator operation. A low
level selects crystal oscillator operation and a high level selects external clock input. As a
mask option, the CTRL1 input pin can be set to function as the CHABLK (character
frame) output. This is a 3-value output.
2
Xtal
IN
3
Xtal
OUT
(MUTE)
4
CTRL1
(CHABLK)
Enable input 2
Enable input for the PDC/VPS data output. Data output is enabled when this input is low.
A pull-up resistor is built in and the input has hysteresis characteristics.
5
CS2
Clock input 2
Clock input for the PDC/VPS data output.
A pull-up resistor is built in and the input has hysteresis characteristics.
6
SCLK2
Data output
PDC/VPS data output.
(This can be either an n-channel open-drain output or a CMOS output.)
7
DOUT
External synchronizing signal judgment
output
Outputs the state of the external synchronizing signal presence/absence judgment.
Outputs a high level when synchronizing signals are present.
Outputs the crystal oscillator clock when CS1 and RST are low.
(This signal is not output on command resets.)
8
SYNC
JDG
Enable input 1
Enable input for the OSD serial data input.
Serial data input is enabled when this pin is low.
A pull-up resistor is built in and the input has hysteresis characteristics.
9
CS1
Clock input 1
Serial data input enable pin.
A pull-up resistor is built in and the input has hysteresis characteristics.
10
SCLK1
Data input 1
Serial data input. A pull-up resistor is built in and the input has hysteresis characteristics.
11
SIN1
Power supply
Composite video signal level adjustment power supply (analog system power supply)
12
V
DD
2
Charge pump output
Charge pump output. Connect a low-pass filter to this pin.
13
CP
OUT
Oscillator control voltage input
VCO oscillator control voltage input. (For data slicing)
14
VCOIN
Ground
Ground (VCO ground)
15
V
SS
3
Oscillator range adjustment
VCO oscillator range adjustment resistor connection
16
VCO
R
Oscillator control voltage input 2
VCO oscillator control voltage input. For character display.
17
VCO
IN
2
Power supply (+5 V)
Power supply (+5 V: VCO power supply)
18
V
DD
3
Video signal output
Composite video signal output
19
CV
OUT
Ground
Ground (analog system ground)
20
V
SS
2
Video signal input
Composite video signal input
21
CV
IN
Video signal input
SECAM chrominance signal input
22
CV
CR
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
23
V
DD
1
Sync separator circuit input
Video signal input to the internal sync separator circuit
24
SYN
IN
Sync separator circuit adjustment
Internal sync separator circuit adjustment
25
SEPC
Composite synchronizing signal output
Internal sync separator circuit composite synchronizing signal output. Can be switched to
function as a signal (high, low, or ST. pulse) output by the MOD0 setting when SEL0 is
high.
26
SEP
OUT
Vertical synchronizing signal input
Inputs the vertical synchronizing signal created by integrating the SEP
OUT
pin output
signal.
An integration circuit must be connected between this pin and the SEP
OUT
pin. This pin
must be tied to V
DD
1 if unused. This pin is valid when CTL3 is set high.
27
SEP
IN
Background color phase adjustment
Background color phase adjustment resistor connection
28
CDLR
Reset input
System reset input.
A pull-up resistor is built in and the input has hysteresis characteristics.
29
RST
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
30
V
DD
1
Note
*
: A capacitor of at least 2000 pF must be connected between the V
DD
1 power supply and V
SS
1.
No. 5833-4/32
LC74798, 74798M
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
DD
max
V
DD
1 and V
DD
2
V
SS
0.3 to V
SS
+ 7.0
V
Maximum input voltage
V
IN
All input pins
V
SS
0.3 to V
DD
+ 0.3
V
Maximum output voltage
V
OUT
D
OUT
, SEP
OUT
, SYNC
JDG
V
SS
0.3 to V
DD
+ 0.3
V
Allowable power dissipation
Pd max
Ta = 25C
350
mW
Operating temperature
Topr
30 to +70
C
Storage temperature
Tstg
40 to +125
C
Specifications
Absolute Maximum Ratings
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
DD
1
V
DD
1 and V
DD
2
4.5
5.0
5.5
V
V
DD
2
V
DD
2
4.5
5.0
1.27 V
DD
1
V
Input high-level voltage
V
IH
1
RST, CS1, CS2, SIN1, SCLK1, SCLK2, MUTE
0.8 V
DD
1
V
DD
1 + 0.3
V
V
IH
2
CTRL1
0.7 V
DD
1
V
DD
1 + 0.3
V
Input low-level voltage
V
IL
1
RST, CS1, CS2, SIN1, SCLK1, SCLK2, MUTE
V
SS
0.3
0.2 V
DD
1
V
V
IL
2
CTRL1
V
SS
0.3
0.3 V
DD
1
V
Pull-up resistance
R
PU
RST, CS1, CS2, SIN1, SCLK1, SCLK2, MUTE
25
50
90
k
Applies to pins set up by options.
Composite video signal input
V
IN
1
CV
IN
and CV
CR
: V
DD
1 = 5 V
2.0
Vp-p
voltage
V
IN
2
SYN
IN
: V
DD
1 = 5 V
1.5
2.0
2.5
Vp-p
Input voltage
V
IN
3
Xtal
IN
(when used for external clock input)
0.10
5.0
Vp-p
f
IN
= 2fsc or 4fsc: V
DD
1 = 5 V
Oscillator frequencies
F
OSC
1
Xtal
IN
and Xtal
OUT
oscillator pins (2fsc : PAL)
8.867
MHz
Xtal
IN
and Xtal
OUT
oscillator pins (4fsc : PAL)
17.734
MHz
Allowable Operating Ranges
Note: Applications must be especially cautious about noise when using the Xtal
IN
input pin in clock input mode.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Input off leakage current
I
leak
1
CV
IN
and CV
CR
1
A
Output off leakage current
I
leak
2
CV
OUT
1
A
Output high-level voltage
V
OH
1
D
OUT
, SEP
OUT
, CP
OUT
, and SYNC
JDG
3.5
V
V
DD
1 = 4.5 V, I
OH
= 1.0 mA
Output low-level voltage
V
OL
1
D
OUT
, SEP
OUT
, CP
OUT
, and SYNC
JDG
1.0
V
V
DD
1 = 4.5 V, I
OL
= 1.0 mA
H
3.3
5.0
V
Three-value output voltage
V
O
CHABLK: V
DD
1 = 5.0 V
M
1.8
2.3
V
L
0
0.8
V
I
IH
RST, CS1, CS2, SIN, SCLK1, SCLK2, CTRL1, MUTE,
1
A
Input current
SEP
IN
, VCOIN, and VCOIN2, V
IN
= V
DD
1
I
IL
CTRL1, SEP
IN
, VCOIN, and VCOIN2, V
IN
= V
SS
1
1
A
I
DD
1
V
DD
1: With all outputs open
40
mA
Operating mode current drain
Xtal : 17.734 MHz, VCO : 27 MHz
I
DD
2
V
DD
2 : V
DD
2 = 5 V
20
mA
CV
OUT
: V
DD
1 = 5.0 V,
(1)
0.80
V
SYNC level
V
SN
V
DD
2 = 5.0 V
(2)
1.00
V
(3)
1.40
V
CV
OUT
: V
DD
1 = 5.0 V,
(1)
1.37
V
Pedestal level
V
PD
V
DD
2 = 5.0 V
(2)
1.57
V
(3)
1.97
V
CV
OUT
: V
DD
1 = 5.0 V,
(1)
1.07
V
Color burst low level
V
CBL
V
DD
2 = 5.0 V
(2)
1.27
V
(3)
1.67
V
CV
OUT
: V
DD
1 = 5.0 V,
(1)
1.67
V
Color burst high level
V
CBH
V
DD
2 = 5.0 V
(2)
1.87
V
(3)
2.27
V
Electrical Characteristics
at Ta = 30 to +70C, V
DD
1 = 5 V unless otherwise specified.
Continued on next page.
No. 5833-5/32
LC74798, 74798M
Continued from preceding page.
Notes: (1): When the sync level = 0.8 V
(2): When the sync level = 1.0 V
(3): When the sync level = 1.4 V
The values in parentheses for the background high and low levels are for blue background mode.
Note: The OSD timing applies when the CMOS output circuit type is used.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
CV
OUT
: V
DD
1 = 5.0 V,
(1)
1.23 (1.16)
V
Background color low level
V
RSL
V
DD
2 = 5.0 V
(2)
1.43 (1.36)
V
(3)
1.83 (1.76)
V
CV
OUT
: V
DD
1 = 5.0 V,
(1)
2.37 (2.01)
V
Background color high level
V
RSH
V
DD
2 = 5.0 V
(2)
2.57 (2.21)
V
(3)
2.97 (2.61)
V
CV
OUT
: V
DD
1 = 5.0 V,
(1)
1.50
V
Frame level 0
V
BK
0
V
DD
2 = 5.0 V
(2)
1.70
V
(3)
2.10
V
CV
OUT
: V
DD
1 = 5.0 V,
(1)
2.08
V
Frame level 1
V
BK
1
V
DD
2 = 5.0 V
(2)
2.28
V
(3)
2.68
V
CV
OUT
: V
DD
1 = 5.0 V,
(1)
2.65
V
Character level
V
CHA
V
DD
2 = 5.0 V
(2)
2.85
V
(3)
3.25
V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
OSD write (See figure 1.)
Minimum input pulse width
t
W (SCLK)
SCLK1
200
ns
t
W (CS1)
CS1 (The period when CS1 is high)
1
s
Data setup time
t
SU (CS1)
CS1
200
ns
t
SU (SIN)
SIN1
200
ns
Data hold time
t
h (CS1)
CS1
2
s
t
h (SIN)
SIN1
200
ns
One word write time
t
word
The 8-bit data write time
4.2
s
t
wt
The RAM data write time
1
s
PDC/VPS write (For the n-channel open-drain output circuit type. See figure 2)
t
CKCY
SCLK2
2
s
Minimum input pulse width
t
CKL
SCLK2
1
s
t
CKH
SCLK2
1
s
Setup time
t
ICK
SCLK2
10
s
Output delay time
t
CKO
DOUT
0.5
s
Timing Characteristics
at Ta = 30 to +70C, V
DD
1 = 5 0.5 V
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