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Электронный компонент: LC7527E

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Overview
The LC7527E is a microprocessor controllable seven-band
graphic equalizer LSI that does not require the use of
external semiconductor inductors (simulated inductors).
Functions
Left and right channel seven-band graphic equalizers
Each band operates in 2 dB steps.
Each band has a maximum boost of +12 dB and a
maximum cut of 12 dB for a total of 13 settings.
Independent left and right channel operation
Serial data input supports CCB format communications
with the system controller.
CMOS LSI with a 12 V breakdown voltage
Features
This LSI, in conjunction with a control microprocessor,
can implement in two chips, an electronic graphic
equalizer with the following features.
-- One touch gain control for each band
-- One touch memory setting recall allows users to
select desired frequency characteristics for each
track.
-- Since the LC7527E includes band filter amplifiers
on chip, capacitors are the only external components
required in application systems.
-- Minimal switching noise due to the use of a Silicon
gate CMOS process.
Package Dimensions
unit: mm
3159-QFP64E
CMOS LSI
O3096HA(OT)/90894TH (OT) 4466-1/11
SANYO: QFP64E
[LC7527E]
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
Graphic Equalizer System
LC7527E
Ordering number : EN4466B
CCB is a trademark of SANYO ELECTRIC CO., LTD.
CCB is SANYO's original bus format and all the bus
addresses are controlled by SANYO.
No. 4466-2/11
LC7527E
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
DD
-V
EE
max
AV
DD
, AV
EE
, DV
DD
, DV
EE
*
12
V
V
IN
max1
CL, DI, CE
V
SS
0.3 to V
DD
+ 0.3
V
Maximum input voltage
V
IN
max2
LIN1, LIN2, RIN1, RIN2
V
EE
0.3 to V
DD
+ 0.3
V
V
IN
max3
S1
V
EE
0.3 to V
DD
+ 0.3
V
Allowable power dissipation
Pd max
Ta
85C
280
mW
Operating temperature
Topr
40 to +85
C
Storage temperature
Tstg
50 to +125
C
Specifications
Absolute Maximum Ratings
at Ta = 25C, V
SS
= 0 V
Note:
*
6 V
V
EE
V
SS
V
DD
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
V
DD
AV
DD
, DV
DD
5
V
Supply voltage
V
EE
AV
EE
, DV
EE
5
V
V
DD
-V
EE
AV
DD
, AV
EE
, DV
DD
, DV
EE
8.0
11.0
V
Input high level voltage
V
IH
CL, DI, CE
3.0
V
DD
V
Input low level voltage
V
IL
CL, DI, CE
V
SS
1.0
V
Input amplitude voltage
V
IN
1
LIN1, LIN2, RIN1, RIN2
V
EE
V
DD
Vp-p
V
IN
2
S1
V
EE
V
DD
V
Clock pulse width
t
W
CL
1
s
Setup time
tsetup
CL, DI, CE
1
s
Hold time
t
HOLD
CL, DI, CE
1
s
Operating frequency
fopg
CL
500
kHz
Allowable Operating Ranges
at Ta = 25C, V
SS
= 0 V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
THD (1)
V
OUT
= 1 Vrms, FLAT, f = 20 kHz
0.01
0.05
%
THD (2)
V
OUT
= 1 Vrms, FLAT, f = 1 kHz
0.001
0.005
%
Total harmonic distortion
THD (3)
V
OUT
= 300 mVrms, FLAT, f = 20 kHz
0.042
0.2
%
with all bands at full boost
THD (4)
V
OUT
= 300 mVrms, FLAT, f = 1 kHz
0.045
0.2
%
with all bands at full boost
Crosstalk
CT
V
OUT
= 1 Vrms, f = 20 kHz, FLAT, Rg = 1 k
58
dB
Setting error
B
with other bands flat
2
+2
dB
Current drain
I
DD
V
DD
-V
EE
= 11 V
30
mA
Analog switch off leakage current
I
OFF
LIN1, LIN2, RIN1, RIN2
10
A
Electrical Characteristics
at Ta = 25C, V
DD
= 5 V, V
EE
= 5 V, V
SS
= 0 V
Electrical Characteristics Test Circuit
Pin Assignment
No. 4466-3/11
LC7527E
No.
Unit (F)
C29, C30,
10
C31, C32
No.
Unit (
)
R1, R3,
7.5 k
R4, R6
R2, R5
1 M
No.
Unit (F)
C1, C28
0.94
C2, C27
0.034
C3, C26
0.377
C4, C25
0.0133
C5, C24
0.1506
C6, C23
5390 p
C7, C22
0.057
C8, C21
2156 p
C9, C20
0.0242
C10, C19
867 p
C11, C18
9200 p
C12, C17
3322 p
C13, C16
3770 p
C14, C15
1330 p
No. 4466-4/11
LC7527E
Pin Functions
Pin
Pin No.
Circuit type
Function
Lf1C1
Lf1C2
Lf1C3
Rf1C1
Rf1C2
Rf1C3
Lf2C1
Lf2C2
Lf2C3
Rf2C1
Rf2C2
Rf2C3
Lf3C1
Lf3C2
Lf3C3
Rf3C1
Rf3C2
Rf3C3
Lf4C1
Lf4C2
Lf4C3
Rf4C1
Rf4C2
Rf4C3
Lf5C1
Lf5C2
Lf5C3
Rf5C1
Rf5C2
Rf5C3
Lf6C1
Lf6C2
Lf6C3
Rf6C1
Rf6C2
Rf6C3
Lf7C1
Lf7C2
Lf7C3
Rf7C1
Rf7C2
Rf7C3
AV
DD
AV
EE
DV
DD
DV
EE
V
SS
62
63
64
51
50
49
1
2
3
48
47
46
4
5
6
45
44
43
7
8
9
42
41
40
10
11
12
39
38
37
13
14
15
36
35
34
17
18
19
32
31
30
23
56
22
57
28
Left channel f1 band control block
External capacitor connections
Right channel f1 band control block
External capacitor connections
Left channel f2 band control block
External capacitor connections
Right channel f2 band control block
External capacitor connections
Left channel f3 band control block
External capacitor connections
Right channel f3 band control block
External capacitor connections
Left channel f4 band control block
External capacitor connections
Right channel f4 band control block
External capacitor connections
Left channel f5 band control block
External capacitor connections
Right channel f5 band control block
External capacitor connections
Left channel f6 band control block
External capacitor connections
Right channel f6 band control block
External capacitor connections
Left channel f7 band control block
External capacitor connections
Right channel f7 band control block
External capacitor connections
Power supply: +5 V typ. Audio signal power supply
Power supply: 5 V typ. Audio signal power supply
Power supply: +5 V typ. Logic signal power supply
Power supply: 5 V typ. Logic signal power supply
Power supply: 0 V
AV
DD
must be equal to DV
DD
, and AV
EE
must be equal to
DV
EE
.
Continued on next page.
No. 4466-5/11
LC7527E
Continued from preceding page.
Pin
Pin No.
Circuit type
Function
LVref
RVref
LIN1
LIN2
RIN1
RIN2
CE
CL
DI
S1
NC
NC
NC
NC
NC
NC
NC
58
55
59
60
54
53
27
25
26
24
16
20
21
29
33
52
61
Power supply: Analog ground
The impedance of the pattern connected to these pins should
be kept as low as possible.
LVref and RVref are not connected to the V
SS
pin.
Left channel audio signal input
IN1 is normally connected to an operational amplifier inverting
input.
IN2 is normally connected to an operational amplifier non-
inverting input.
Right channel audio signal input
IN1 is normally connected to an operational amplifier inverting
input.
IN2 is normally connected to an operational amplifier non-
inverting input.
Chip enable input. Internal data is latched when this pin goes
from high to low and the analog switches operate. Data
transfers are enabled when this pin is high.
Clock input. Schmitt inverter input circuit
Data input. Schmitt inverter input circuit
Dual chip system chip select input. By connecting S1 (this pin)
to either V
DD
or V
EE
, data input is enabled when the address
matches the corresponding address listed below.
S1 = V
DD
Address: 8C
S1 = V
EE
Address: 8D
No connection. Do not connect signals to these pins.