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Электронный компонент: LC75804

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Ordering number : ENN6266A
51003AS / D2599TH (OT) No. 6266-1/37
Overview
The LC75804E and LC75804W are 1/3 duty and 1/4 duty
LCD display drivers that can directly drive up to 300
segments and can control up to eight general-purpose
output ports. These products also incorporate a key scan
circuit that accepts input from up to 30 keys to reduce
printed circuit board wiring.
Features
Key input function for up to 30 keys (A key scan is
performed only when a key is pressed.)
1/3 duty and 1/4 duty drive schemes can be controlled
from serial data.
1/2 bias and 1/3 bias drive schemes can be controlled
from serial data.
Capable of driving up to 228 segments using 1/3 duty
and up to 300 segments using 1/4 duty.
Sleep mode and all segments off functions that are
controlled from serial data.
Segment output port/general-purpose output port
function switching that is controlled from serial data.
Serial data I/O supports CCB format communication
with the system controller.
Direct display of display data without the use of a
decoder provides high generality.
Independent V
LCD
for the LCD driver block (V
LCD
can
be set to in the range V
DD
0.5 to 6.0 volts.)
Provision of an on-chip voltage-detection type reset
circuit prevents incorrect displays.
RES pin provided for forcibly initializing the IC internal
circuits.
RC oscillator circuit.
Package Dimensions
unit: mm
3151A-QFP100E
unit: mm
3181C-SQFP100
20.0
23.2
14.0
17.2
0.15
0.8
(2.7)
3.0max
0.1
0.3
0.65
(0.58)
1
30
80
51
31
50
100
81
SANYO: QFP100E(QIP100E)
[LC75804E]
14.0
16.0
14.0
16.0
0.145
0.2
0.5
(1.0)
(1.4)
1.6max
0.1
0.5
1
25
26
50
51
75
76
100
SANYO: SQFP100
[LC75804W]
LC75804E, LC75804W
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
1/3, 1/4 Duty LCD Display Drivers
with Key Input Function
CMOS IC
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
CCB is a trademark of SANYO ELECTRIC CO., LTD.
CCB is SANYO's original bus format and all the bus
addresses are controlled by SANYO.
No. 6266-2/37
LC75804E, LC75804W
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
DD
max
V
DD
0.3 to +7.0
V
V
LCD
max
V
LCD
0.3 to +7.0
V
IN
1
CE, CL, DI, RES
0.3 to +7.0
Input voltage
V
IN
2
OSC,TEST
0.3 to V
DD
+0.3
V
V
IN
3
V
LCD
1, V
LCD
2, KI1 to KI5
0.3 to V
LCD
+0.3
V
OUT
1
DO
0.3 to +7.0
Output voltage
V
OUT
2
OSC
0.3 to V
DD
+0.3
V
V
OUT
3
S1 to S76, COM1 to COM4, KS1 to KS6, P1 to P8
0.3 to V
LCD
+0.3
I
OUT
1
S1 to S76
300
A
Output current
I
OUT
2
COM1 to COM4
3
I
OUT
3
KS1 to KS6
1
mA
I
OUT
4
P1 to P8
5
Allowable power dissipation
Pd max
Ta = 85C
200
mW
Operating temperature
Topr
40 to +85
C
Storage temperature
Tstg
55 to +125
C
Specifications
Absolute Maximum Ratings
at Ta=25C, V
SS
=0V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
DD
V
DD
4.5
6.0
V
V
LCD
V
LCD
V
DD
0.5
6.0
Input voltage
V
LCD
1
V
LCD
1
2/3 V
LCD
V
LCD
V
V
LCD
2
V
LCD
2
1/3 V
LCD
V
LCD
Input high level voltage
V
IH
1
CE, CL, DI, RES
0.8 V
DD
6.0
V
V
IH
2
KI1 to KI5
0.6 V
DD
V
LCD
Input low level voltage
V
IL
CE, CL, DI, RES, KI1 to KI5
0
0.2 V
DD
V
Recommended external resistance
R
OSC
OSC
39
k
Recommended external capacitance
C
OSC
OSC
1000
pF
Guaranteed oscillator range
f
OSC
OSC
19
38
76
kHz
Data setup time
t
ds
CL, DI
:Figure 2
160
ns
Data hold time
t
dh
CL, DI
:Figure 2
160
ns
CE wait time
t
cp
CE, CL
:Figure 2
160
ns
CE setup time
t
cs
CE, CL
:Figure 2
160
ns
CE hold time
t
ch
CE, CL
:Figure 2
160
ns
High level clock pulse width
t
H
CL
:Figure 2
160
ns
Low level clock pulse width
t
L
CL
:Figure 2
160
ns
Rise time
t
r
CE, CL, DI
:Figure 2
160
ns
Fall time
t
f
CE, CL, DI
:Figure 2
160
ns
DO output delay time
t
dc
DO R
PU
=4.7 k
, C
L
=10pF
*
1
:Figure 2
1.5
s
DO rise time
t
dr
DO R
PU
=4.7 k
, C
L
=10pF
*
1
:Figure 2
1.5
s
Allowable Operating Ranges
at Ta = 40 to +85C, V
SS
=0V
Note:
*
1. Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor R
PU
and the load capacitance C
L
.
No. 6266-3/37
LC75804E, LC75804W
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Hysteresis
V
H
CE, CL, DI, RES, KI1 to KI5
0.1 V
DD
V
Power-down detection voltage
V
DET
2.5
3.0
3.5
V
Input high level current
I
IH
CE, CL, DI, RES: V
I
= 6.0 V
5.0
A
Input low level current
I
IL
CE, CL, DI, RES: V
I
= 0 V
5.0
A
Input floating voltage
V
IF
KI1 to KI5
0.05 V
DD
V
Pull-down resistance
R
PD
KI1 to KI5: V
DD
= 5.0 V
50
100
250
k
Output off leakage current
I
OFFH
DO: VO = 6.0 V
6.0
A
V
OH
1
KS1 to KS6: I
O
= 500 A
V
LCD
1.0 V
LCD
0.5 V
LCD
0.2
Output high level voltage
V
OH
2
P1 to P8: I
O
= 1 mA
V
LCD
1.0
V
V
OH
3
S1 to S76: I
O
= 20 A
V
LCD
1.0
V
OH
4
COM1 to COM4: I
O
= 100 A
V
LCD
1.0
V
OL
1
KS1 to KS6: I
O
= 25 A
0.2
0.5
1.5
V
OL
2
P1 to P8: I
O
= 1 mA
1.0
Output low level voltage
V
OL
3
S1 to S76: I
O
= 20 A
1.0
V
V
OL
4
COM1 to COM4: I
O
= 100 A
1.0
V
OL
5
DO: I
O
= 1 mA
0.1
0.5
V
MID
1
COM1 to COM4: 1/2 bias, I
O
= 100 A
1/2 V
LCD
1.0
1/2 V
LCD
+ 1.0
V
MID
2
S1 to S76: 1/3 bias,I
O
= 20 A
2/3 V
LCD
1.0
2/3 V
LCD
+ 1.0
Output middle level voltage
*
2
V
MID
3
S1 to S76: 1/3 bias, I
O
= 20 A
1/3 V
LCD
1.0
1/3 V
LCD
+ 1.0
V
V
MID
4
COM1 to COM4: 1/3 bias,I
O
= 100 A
2/3 V
LCD
1.0
2/3 V
LCD
+ 1.0
V
MID
5
COM1 to COM4: 1/3 bias,I
O
= 100 A
1/3 V
LCD
1.0
1/3 V
LCD
+ 1.0
Oscillator frequency
fosc
OSC: R
OSC
= 39 k
, C
OSC
= 1000 pF
30.4
38
45.6
kHz
I
DD
1
V
DD
:Sleep mode
100
I
DD
2
V
DD
: V
DD
= 6.0 V, output open,fosc = 38 kHz
270
540
Current drain
I
LCD
1
V
LCD
: Sleep mode
5
A
I
LCD
2
V
LCD
: V
LCD
= 6.0 V, output open, 1/2 bias,
200
400
fosc = 38 kHz
I
LCD
3
V
LCD
: V
LCD
= 6.0 V, output open, 1/3 bias,
120
240
fosc = 38 kHz
Electrical Characteristics
for the Allowable Operating Ranges
Nete:
*
2. Excluding the bias voltage generation divider resistor built into V
LCD
1 and V
LCD
2. (See Figure 1.)
Figure 1
1. When CL is stopped at the low level
Figure 2
No. 6266-4/37
LC75804E, LC75804W
V
LCD
V
LCD
2
V
LCD
1
tdh
50%
VIH1
VIH1
VIL
VIL
VIH1
VIL
tdr
tdc
tch
tcs
tcp
tds
tr
CL
t
L
t H
tf
DO
DI
D1
D0
CE
2. When CL is stopped at the high level
50%
VIH1
VIL
tdh
VIH1
VIL
VIH1
VIL
tdr
tdc
tch
tcs
tcp
tds
tf
CL
t H
t L
tr
DO
DI
D1
D0
CE
To the common segment driver
Excluding these registors.
Pin Assignments
No. 6266-5/37
LC75804E, LC75804W
KI1
VDD
VLCD2
P4/S4
S10
S16
S21
S15
S34
S39
S44
S59
S58
S49
S50
S51
S52
S53
S54
S55
S56
S57
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
COM4/S74
COM3
COM2
COM1
KS1/S75
P3/S3
S9
P2/S2
P1/S1
DI
CL
LC75804E
(QFP100E)
S76/KS2
KS6
KS3
KS4
KS5
KI2
KI3
KI5
KI4
VLCD
VLCD1
VSS
TEST
RES
OSC
DO
S33
S32
S31
S30
S29
CE
51
80
50
81
31
100
30
(Top view)
(Top view)
1
P8/S8
P7/S7
P6/S6
P5/S5
S14
S20
S13
S12
S11
S19
S18
S17
S25
S24
S23
S22
S28
S27
S26
S38
S37
S36
S35
S43
S42
S41
S40
S48
S47
S46
S45
S55
S51
S52
S53
S54
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
COM4/S74
COM3
P5/S5
S11
P4/S4
P3/S3
P2/S2
P1/S1
LC75804W
(SQFP100)
COM1
S76/KS2
S75/KS1
KS3
COM2
KS4
KS5
KS6
KI2
KI1
KI4
KI3
S35
S34
S33
S32
S31
S29
S30
S27
S28
S26
DI
51
75
50
76
26
100
25
1
KI5
VLCD
VDD
VLCD2
VLCD1
VSS
OSC
TEST
RES
CE
DO
CL
S10
S9
P8/S8
P7/S7
P6/S6
S16
S22
S15
S14
S13
S12
S21
S20
S19
S18
S17
S25
S24
S23
S40
S39
S38
S37
S36
S45
S44
S43
S42
S41
S50
S49
S48
S47
S46