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Электронный компонент: LC75833E

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CMOS LSI
Ordering number : EN 5580A
33098HA(OT)/22897HA(OT) No. 5580-1/19
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
1/3 Duty General-Purpose
LCD Display Drivers
LC75833E, 75833W, 75833JE
Overview
The LC75833E, LC75833W, and LC75833JE are 1/3-duty
general-purpose LCD display drivers that can be used for
frequency display in electronic tuners under the control of
a microcontroller. The LC75833E and LC75833W can
drive an LCD with up to 105 segments directly, the
LC75833JE can drive an LCD with up to 93 segments
directly. The LC75833E and LC75833W and LC75833JE
can also control up to 8 general-purpose output ports.
Since the LC75833E, LC75833W, and LC75833JE use
separate power supply systems for the LCD drive block
and the logic block, the LCD driver block power-supply
voltage can be set to any voltage in the range 2.7 to 6.0
volts, regardless of the logic block power-supply voltage.
Features
Supports both 1/3 duty 1/2 bias and 1/3 duty 1/3 bias
LCD drive under serial data control.
LC75833E, LC75833W:
up to 105 segments
LC75833JE:
up to 93 segments
(without the S12, S23, S24, S35 segment output pins
from the LC75833E, LC75833W)
Serial data input supports CCB format communication
with the system controller.
Serial data control of the power-saving mode based
backup function and all the segments forced off function
Serial data control of switching between the segment
output port and the general-purpose output port
functions
High generality, since display data is displayed directly
without decoder intervention.
Independent V
LCD
for the LCD driver block (V
LCD
can
be set to any voltage in the range 2.7 to 6.0 volts,
regardless of the logic block power-supply voltage.)
The INH pin can force the display to the off state.
RC oscillator circuit
Package Dimensions
unit: mm
3156-QFP48E
unit: mm
3163A-SQFP48
unit: mm
3148-QFP44MA
CCB is a trademark of SANYO ELECTRIC CO., LTD.
CCB is SANYO's original bus format and all the bus
addresses are controlled by SANYO.
[LC75833W]
[LC75833E]
SANYO: QFP48E
[LC75833JE]
SANYO: SQFP48
SANYO: QIP44MA
Specifications
Absolute Maximum Ratings
at Ta = 25C, V
SS
= 0 V
Note: The LC75833JE does not have the S12, S23, S24, S35 output pins.
Allowable Operating Ranges
at Ta = 40 to +85C, V
SS
= 0 V
No. 5580-2/19
LC75833E, 75833W, 75833JE
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
DD
max
V
DD
0.3 to +7.0
V
V
LCD
max
VLCD
0.3 to +7.0
V
V
IN
1
CE, CL, DI, INH
0.3 to +7.0
V
Input voltage
V
IN
2
OSC
0.3 to V
DD
+ 0.3
V
V
IN
3
VLCD 1, VLCD 2
0.3 to V
LCD
+ 0.3
V
Output voltage
V
OUT
1
OSC
0.3 to V
DD
+ 0.3
V
V
OUT
2
S1 to S35, COM1 to COM3, P1 to P8
0.3 to V
LCD
+ 0.3
V
I
OUT
1
S1 to S35
300
A
Output current
I
OUT
2
COM1 to COM3
3
mA
I
OUT
3
P1 to P8
5
mA
Allowable power dissipation
Pd max
Ta = 85C
150
mW
Operating temperature
Topr
40 to +85
C
Storage temperature
Tstg
55 to +125
C
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
DD
V
DD
2.7
6.0
V
V
LCD
V
LCD
2.7
6.0
V
Input voltage
V
LCD
1
V
LCD
1
2/3 V
LCD
V
LCD
V
V
LCD
2
V
LCD
2
1/3 V
LCD
V
LCD
V
Input high-level voltage
V
IH
CE, CL, DI, INH
0.8 V
DD
6.0
V
Input low-level voltage
V
IL
CE, CL, DI, INH
0
0.2 V
DD
V
Recommended external resistance
R
OSC
OSC
39
k
Recommended external capacitance
C
OSC
OSC
1000
pF
Guaranteed oscillation range
f
OSC
OSC
19
38
76
kHz
Data setup time
t
ds
CL, DI: Figure 2
160
ns
Data hold time
t
dh
CL, DI: Figure 2
160
ns
CE wait time
t
cp
CE, CL: Figure 2
160
ns
CE setup time
t
cs
CE, CL: Figure 2
160
ns
CE hold time
t
ch
CE, CL: Figure 2
160
ns
High-level clock pulse width
t
H
CL: Figure 2
160
ns
Low-level clock pulse width
t
L
CL: Figure 2
160
ns
Rise time
t
r
CE, CL, DI: Figure 2
160
ns
Fall time
t
f
CE, CL, DI: Figure 2
160
ns
INH switching time
t
c
INH, CE: Figure 3
10
s
No. 5580-3/19
LC75833E, 75833W, 75833JE
Electrical Characteristics
for the Allowable Operating Ranges
Note:
*
1 Excluding the bias voltage generation divider resistors built in the VLCD1 and VLCD2. (See Figure 1.)
The LC75833JE does not have the S12, S23, S24, S35 output pins.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Hysteresis width
V
H
CE, CL, DI, INH
0.1 VDD
V
Input high level current
I
IH
CE, CL, DI, INH; V
I
= 6.0 V
5.0
A
Input low level current
I
IL
CE, CL, DI, INH; V
I
= 0 V
5.0
A
V
OH
1
S1 to S35; I
O
= 20 A
V
LCD
0.9
V
Output high-level voltage
V
OH
2
COM1 to COM3; I
O
= 100 A
V
LCD
0.9
V
V
OH
3
P1 to P8; I
O
= 1 mA
V
LCD
0.9
V
V
OL
1
S1 to S35; I
O
= 20 A
0.9
V
Output low-level voltage
V
OL
2
COM1 to COM3; I
O
= 100 A
0.9
V
V
OL
3
P1 to P8; I
O
= 1 mA
0.9
V
V
MID
1
COM1 to COM3; 1/2 bias,
1/2 V
LCD
0.9
1/2 V
LCD
+ 0.9
V
I
O
= 100 A
V
MID
2
S1 to S35; 1/3 bias,
2/3 V
LCD
0.9
2/3 V
LCD
+ 0.9
V
I
O
= 20 A
Output middle-level voltage
*
1
V
MID
3
S1 to S35; 1/3 bias,
1/3 V
LCD
0.9
1/3 V
LCD
+ 0.9
V
I
O
= 20 A
V
MID
4
COM1 to COM3; 1/3 bias,
2/3 V
LCD
0.9
2/3 V
LCD
+ 0.9
V
I
O
= 100 A
V
MID
5
COM1 to COM3; 1/3 bias,
1/3 V
LCD
0.9
1/3 V
LCD
+ 0.9
V
I
O
= 100 A
Oscillator frequency
f
OSC
OSC; R
OSC
= 39 k
C
OSC
= 1000 pF
30.4
38
45.6
kHz
I
DD
1
VDD; power saving mode
5
A
I
DD
2
VDD; V
DD
= 6.0 V, output open, fosc = 38 k Hz
250
500
A
I
LCD
1
VLCD; power saving mode
5
A
Current drain
I
LCD
2
VLCD; VLCD = 6.0 V, output open
100
200
A
1/2 bias, fosc = 38 k Hz
I
LCD
3
VLCD; VLCD = 6.0 V, output open
60
120
A
1/3 bias, fosc = 38 k Hz
2. When CL is stopped at the high level
Figure 2
No. 5580-4/19
LC75833E, 75833W, 75833JE
VLCD1
VLCD2
VLCD
VSS
A06550
To the common segments driver
Except these resistors
s
tH
tL
tr
tf
tds
tdh
tcp
tcs
tch
VIL
VIH
VIH
VIH
VIL
VIL
50%
CL
CE
DI
A06551
VIH
tL
tH
tf
tr
tds
tdh
tcp
tcs
tch
VIL
VIH
VIH
VIL
VIL
50%
CL
CE
DI
A06552
Figure 1
1. When CL is stopped at the low level
Pin Assignments
Block Diagram
Note: The LC75833JE does not have the S12, S23, S24, S35 output pins.
No. 5580-5/19
LC75833E, 75833W, 75833JE
COM2
37
COM3
VDD
VLCD
VLCD1
VLCD2
VSS
OSC
INH
CE
CL
DI
48
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
13
24
P1/S1
1
12
P2/S2
P3/S3
P4/S4
P5/S5
P6/S6
P7/S7
P8/S8
S9
S10
S11
S12
S25
25
36
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
COM1
LC75833E
LC75833W
A06549
34
COM3
VDD
VLCD
VLCD1
VLCD2
VSS
OSC
INH
CE
CL
DI
44
S25
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
12
22
P1/S1
1
11
P2/S2
P3/S3
P4/S4
P5/S5
P6/S6
P7/S7
P8/S8
S9
S10
S11
23
33
S26
S27
S28
S29
S30
S31
S32
S33
S34
COM1
COM2
LC75833JE
A06582
Common
driver
Address
detector
Clock
generator
Segment driver & latch
Shift register
INH
OSC
VDD
VLCD
VLCD1
VLCD2
VSS
DI
CL
CE
COM3
COM2
COM1
S35
S34
S9
S8/P8
S2/P2
S1/P1
A06553