Ordering number : EN6086
22299RM (OT) No. 6086-1/27
Overview
The LC75884E and LC75884W are 1/4 duty LCD display
drivers that can directly drive up to 220 segments and can
control up to four general-purpose output ports. These
products also incorporate a key scan circuit that accepts
input from up to 30 keys to reduce printed circuit board
wiring.
Features
Key input function for up to 30 keys (A key scan is
performed only when a key is pressed.)
1/4duty - 1/2bias and 1/4duty - 1/3bias drive schemes
can be controlled from serial data (up to 220 segments).
Sleep mode and all segments off functions that are
controlled from serial data.
Segment output port/general-purpose output port
function switching that is controlled from serial data.
Serial data I/O supports CCB format communication
with the system controller.
Direct display of display data without the use of a
decoder provides high generality.
Independent V
LCD
for the LCD driver block (V
LCD
can
be set to in the range V
DD
-0.5 to 6.0 volts.)
Provision of an on-chip voltage-detection type reset
circuit prevents incorrect displays.
RES pin provided for forcibly initializing the IC internal
circuits.
RC oscillator circuit.
Package Dimensions
unit: mm
QFP80E
unit: mm
SQFP80
0.15
1.6
14.0
17.2
0.8
1
24
25
40
41
64
65
80
21.6
0.8
3.0max
1.0
2.7
15.6
0.8
1.6
0.35
23.2
20.0
0.8
0.8
SANYO: QFP80E(QIP80E)
[LC75884E]
14.0
12.0
1.25
1.25
0.5
14.0
12.0
1.25
1.25
0.5
1
20
21
40
41
60
61
80
0.1
0.5
1.6max
1.4
0.5
0.2
0.135
SANYO: SQFP80
[LC75884W]
LC75884E, LC75884W
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
1/4 Duty LCD Display Drivers with Key Input Function
CMOS IC
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
CCB is a trademark of SANYO ELECTRIC CO., LTD.
CCB is SANYO's original bus format and all the bus
addresses are controlled by SANYO.
No. 6086-2/27
LC75884E, LC75884W
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
DD
max
V
DD
0.3 to +7.0
V
V
LCD
max
V
LCD
0.3 to +7.0
V
IN
1
CE, CL, DI, RES
0.3 to +7.0
Input voltage
V
IN
2
OSC,TEST
0.3 to V
DD
+0.3
V
V
IN
3
V
LCD
1, V
LCD
2, KI1 to KI5
0.3 to V
LCD
+0.3
V
OUT
1
DO
-0.3 to +7.0
Output voltage
V
OUT
2
OSC
0.3 to V
DD
+0.3
V
V
OUT
3
S1 to S55, COM1 to COM4, KS1 to KS6, P1 to P4
0.3 to V
LCD
+0.3
I
OUT
1
S1 to S55
300
A
Output current
I
OUT
2
COM1 to COM4
3
I
OUT
3
KS1 to KS6
1
mA
I
OUT
4
P1 to P4
5
Allowable power dissipation
Pd max
Ta = 85C
200
mW
Operating temperature
Topr
40 to +85
C
Storage temperature
Tstg
55 to +125
C
Specifications
Absolute Maximum Ratings
at Ta=25C, V
SS
=0V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
DD
V
DD
4.5
6.0
V
V
LCD
V
LCD
V
DD
0.5
6.0
Input voltage
V
LCD
1
V
LCD
1
2/3 V
LCD
V
LCD
V
V
LCD
2
V
LCD
2
1/3 V
LCD
V
LCD
Input high level voltage
V
IH
1
CE, CL, DI, RES
0.8 V
DD
6.0
V
V
IH
2
KI1 to KI5
0.6 V
DD
V
LCD
Input low level voltage
V
IL
CE, CL, DI, RES, KI1 to KI5
0
0.2 V
DD
V
Recommended external resistance
R
OSC
OSC
43
k
Recommended external capacitance
C
OSC
OSC
680
pF
Guaranteed oscillator range
f
OSC
OSC
25
50
100
kHz
Data setup time
t
ds
CL, DI
:Figure 2
160
ns
Data hold time
t
dh
CL, DI
:Figure 2
160
ns
CE wait time
t
cp
CE, CL
:Figure 2
160
ns
CE setup time
t
cs
CE, CL
:Figure 2
160
ns
CE hold time
t
ch
CE, CL
:Figure 2
160
ns
High level clock pulse width
t
H
CL
:Figure 2
160
ns
Low level clock pulse width
t
L
CL
:Figure 2
160
ns
Rise time
t
r
CE, CL, DI
:Figure 2
160
ns
Fall time
t
f
CE, CL, DI
:Figure 2
160
ns
DO output delay time
t
dc
DO R
PU
=4.7k
, C
L
=10pF
*
1
:Figure 2
1.5
s
DO rise time
t
dr
DO R
PU
=4.7k
, C
L
=10pF
*
1
:Figure 2
1.5
s
Allowable Operating Ranges
at Ta = 40 to +85C, V
SS
=0V
Note:
*
1. Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor R
PU
and the load capacitance C
L
.
No. 6086-3/27
LC75884E, LC75884W
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Hysteresis
V
H
CE, CL, DI, RES, KI1 to KI5
0.1 V
DD
V
Power-down detection voltage
V
DET
2.5
3.0
3.5
V
Input high level current
I
IH
CE, CL, DI, RES: V
I
= 6.0V
5.0
A
Input low level current
I
IL
CE, CL, DI, RES: V
I
= 0V
5.0
A
Input floating voltage
V
IF
KI1 to KI5
0.05 V
DD
V
Pull-down resistance
R
PD
KI1 to KI5: V
DD
= 5.0V
50
100
250
k
Output off leakage current
I
OFFH
DO: VO = 6.0V
6.0
A
V
OH
1
KS1 to KS6: I
O
= 500A
V
LCD
1.0 V
LCD
0.5 V
LCD
0.2
Output high level voltage
V
OH
2
P1 to P4: I
O
= 1mA
V
LCD
1.0
V
V
OH
3
S1 to S55: I
O
= 20A
V
LCD
1.0
V
OH
4
COM1 to COM4: I
O
= 100A
V
LCD
1.0
V
OL
1
KS1 to KS6: I
O
= 25A
0.2
0.5
1.5
V
OL
2
P1 to P4: I
O
= 1mA
1.0
Output low level voltage
V
OL
3
S1 to S55: I
O
= 20A
1.0
V
V
OL
4
COM1 to COM4: I
O
= 100A
1.0
V
OL
5
DO: I
O
= 1mA
0.1
0.5
V
MID
1
COM1 to COM4: 1/2bias, I
O
= 100A
1/2V
LCD
1.0
1/2V
LCD
+ 1.0
V
MID
2
S1 to S55: 1/3bias,I
O
= 20A
2/3V
LCD
1.0
2/3V
LCD
+ 1.0
Output middle level voltage
*
2
V
MID
3
S1 to S55: 1/3bias, I
O
= 20A
1/3V
LCD
1.0
1/3V
LCD
+ 1.0
V
V
MID
4
COM1 to COM4: 1/3bias,I
O
= 100A
2/3V
LCD
1.0
2/3V
LCD
+ 1.0
V
MID
5
COM1 to COM4: 1/3bias,I
O
= 100A
1/3V
LCD
1.0
1/3V
LCD
+ 1.0
Oscillator frequency
fosc
OSC: R
OSC
= 43k
, C
OSC
= 680pF
40
50
60
kHz
I
DD
1
V
DD
:Sleep mode
100
I
DD
2
V
DD
: V
DD
= 6.0V, output open,fosc = 50kHz
270
540
Current drain
I
LCD
1
V
LCD
: Sleep mode
5
A
I
LCD
2
V
LCD
: V
LCD
= 6.0V, output open, 1/2bias,
200
400
fosc = 50kHz
I
LCD
3
V
LCD
: V
LCD
= 6.0V, output open, 1/3bias,
120
240
fosc = 50kHz
Electrical Characteristics for the Allowable Operating Ranges
Nete:
*
2. Excluding the bias voltage generation divider resistor built into V
LCD
1 and V
LCD
2. (See Figure 1.)
Figure 1
1. When CL is stopped at the low level
Figure 2
No. 6086-4/27
LC75884E, LC75884W
2. When CL is stopped at the high level
Pin Assignment
No. 6086-5/27
LC75884E, LC75884W
Block Diagram
No. 6086-6/27
LC75884E, LC75884W
No. 6086-7/27
LC75884E, LC75884W
Pin
Pin No.
Function
Active
I/O
Handling
LC75884E
LC75884W
when unused
S1/P1
1
79
S2/P2
2
80
S3/P3
3
1
--
q
q
OPEN
S4/P4
4
2
S5 to S53
5 to 53
3 to 51
COM1
54
52
COM2
55
53
--
q
q
OPEN
COM3
56
54
COM4
57
55
KS1/S54
58
56
KS2/S55
59
57
--
O
OPEN
KS3 to KS6
60 to 63
58 to 61
KI1 to KI5
64 to 68
62 to 66
H
I
GND
OSC
75
73
--
I/O
V
DD
CE
78
76
H
I
CL
79
77
I
GND
DI
80
78
--
I
DO
77
75
--
O
OPEN
RES
76
74
L
I
V
DD
TEST
74
72
This pin must be connected to ground.
--
I
--
V
LCD
1
71
69
--
I
OPEN
V
LCD
2
72
70
--
I
OPEN
V
DD
69
67
--
--
--
V
LCD
70
68
--
--
--
V
SS
73
71
Power supply connection. Connect to ground.
--
--
--
Pin Functions
Segment outputs for displaying the display data transferred by serial
data input.
The S1/P1 to S4/P4 pins can be used as general-purpose output ports
under serial data control.
Common driver outputs
The frame frequency fo is given by : fo = (f
OSC
/512)Hz.
Key scan outputs
Although normal key scan timing lines require diodes to be inserted in
the timing lines to prevent shorts, since these outputs are unbalanced
CMOS transistor outputs, these outputs will not be damaged by shorting
when these outputs are used to form a key matrix. The KS1/S54 and
KS2/S55 pins can be used as segment outputs when so specified by
the control data.
Key scan inputs
These pins have built-in pull-down resistors.
Oscillator connection
An oscillator circuit is formed by connecting an external resistor and
capacitor at this pin.
Serial data interface connections to the controller. Note that DO, being
an open-drain output, requires a pull-up resistor.
CE :Chip enable
CL :Synchronization clock
DI :Transfer data
DO :Output data
v
Reset signal input
RES=low Display off
Key scan disabled
All key data is reset to low
RES=high Display on
Key scan enabled
However, serial data can be transferred when RES is low.
Used for applying the LCD drive 2/3 bias voltage externally. Must be
connected to VLCD2 when a 1/2 bias drive scheme is used.
Used for applying the LCD drive 1/3 bias voltage externally. Must be
connected to VLCD1 when a 1/2 bias drive scheme is used.
Logic block power supply connection. Provide a voltage of between 4.5
and 6.0V.
LCD driver block power supply connection. Provide a voltage of
between VDD0.5 and 6.0V.
Serial Data Input
1. When CL is stopped at the low level
Note: B0 to B3,A0 to A3 ........ CCB address
DD ................................ Direction data
No. 6086-8/27
LC75884E, LC75884W
No. 6086-9/27
LC75884E, LC75884W
2. When CL is stopped at the high level
Note: B0 to B3,A0 to A3 ........ CCB address
DD ................................ Direction data
CCB address ........ 42H
D1 to D220 ............ Display data
S0,S1 .................... Sleep control data
K0,K1 .................... Key scan output/segment output selection data
P0 to P2 ................ Segment output port/general-purpose output port selection data
SC ........................ Segment on/off control data
DR ........................ 1/2 bias or 1/3 bias drive selection data
Control Data Functions
1. S0, S1 : Sleep control data
These control data bits switch between normal mode and sleep mode and set the states of the KS1 to KS6 key scan
outputs during key scan standby.
Note: This assumes that the KS1/S54 and KS2/S55 output pins are selected for key scan output.
No. 6086-10/27
LC75884E, LC75884W
Control data
Mode
OSC oscillator
Segment outputs
Output pin states during key scan standby
S0
S1
Common outputs
KS1
KS2
KS3
KS4
KS5
KS6
0
0
Normal
Operating
Operating
H
H
H
H
H
H
0
1
Sleep
Stopped
L
L
L
L
L
L
H
1
0
Sleep
Stopped
L
L
L
L
L
H
H
1
1
Sleep
Stopped
L
H
H
H
H
H
H
2. K0, K1 : Key scan output /segment output selection data
These control data bits switch the functions of the KS1/S54 and KS2/S55 output pins between key scan output and
segment output.
X: don't care
Note: KSn(n=1 or 2) : Key scan output
Sn (n=54 or 55): Segment output
Control data
Output pin state
Maximum number of
K0
K1
KS1/S54
KS2/S55
input keys
0
0
KS1
KS2
30
0
1
S54
KS2
25
1
X
S54
S55
20
3. P0 to P2 : Segment output port/general-purpose output port selection data
These control data bits switch the functions of the S1/P1 to S4/P4 output pins between the segment output port and
the general-purpose output port.
Note: Sn(n=1 to 4): Segment output port
Pn(n=1 to 4): General-purpose output port
The table below lists the correspondence between the display data and the output pins when these pins are selected to be general-purpose output ports.
For example, if the S4/P4 output pin is selected to be a general-purpose output port, the S4/P4 output pin will output a high level (V
LCD
) when the display data
D13 is 1, and will output a low level (Vss) when D13 is 0.
Control data
Output pin state
P0
P1
P2
S1/P1
S2/P2
S3/P3
S4/P4
0
0
0
S1
S2
S3
S4
0
0
1
P1
S2
S3
S4
0
1
0
P1
P2
S3
S4
0
1
1
P1
P2
P3
S4
1
0
0
P1
P2
P3
P4
Output pin
Corresponding display data
S1/P1
D1
S2/P2
D5
S3/P3
D9
S4/P4
D13
No. 6086-11/27
LC75884E, LC75884W
However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off waveforms from the segment
output pins.
SC
Display state
0
on
1
off
4. SC : Segment on/off control data
This control data bit controls the on/off state of the segments.
DR
Drive scheme
0
1/3 bias drive
1
1/2 bias drive
5. DR : 1/2 bias or 1/3 bias drive selection data
This control data bit switches between LCD 1/2 bias or 1/3 bias drive.
Display Data and Output Pin Correspondence
Note: This is for the case where the output pins S1/P1 to S4/P4, KS1/S54 and KS2/S55 are selected for use as segment outputs.
Output pin
COM1
COM2
COM3
COM4
S1/P1
D1
D2
D3
D4
S2/P2
D5
D6
D7
D8
S3/P3
D9
D10
D11
D12
S4/P4
D13
D14
D15
D16
S5
D17
D18
D19
D20
S6
D21
D22
D23
D24
S7
D25
D26
D27
D28
S8
D29
D30
D31
D32
S9
D33
D34
D35
D36
S10
D37
D38
D39
D40
S11
D41
D42
D43
D44
S12
D45
D46
D47
D48
S13
D49
D50
D51
D52
S14
D53
D54
D55
D56
S15
D57
D58
D59
D60
S16
D61
D62
D63
D64
S17
D65
D66
D67
D68
S18
D69
D70
D71
D72
S19
D73
D74
D75
D76
S20
D77
D78
D79
D80
S21
D81
D82
D83
D84
S22
D85
D86
D87
D88
S23
D89
D90
D91
D92
S24
D93
D94
D95
D96
S25
D97
D98
D99
D100
S26
D101
D102
D103
D104
S27
D105
D106
D107
D108
S28
D109
D110
D111
D112
Output pin
COM1
COM2
COM3
COM4
S29
D113
D114
D115
D116
S30
D117
D118
D119
D120
S31
D121
D122
D123
D124
S32
D125
D126
D127
D128
S33
D129
D130
D131
D132
S34
D133
D134
D135
D136
S35
D137
D138
D139
D140
S36
D141
D142
D143
D144
S37
D145
D146
D147
D148
S38
D149
D150
D151
D152
S39
D153
D154
D155
D156
S40
D157
D158
D159
D160
S41
D161
D162
D163
D164
S42
D165
D166
D167
D168
S43
D169
D170
D171
D172
S44
D173
D174
D175
D176
S45
D177
D178
D179
D180
S46
D181
D182
D183
D184
S47
D185
D186
D187
D188
S48
D189
D190
D191
D192
S49
D193
D194
D195
D196
S50
D197
D198
D199
D200
S51
D201
D202
D203
D204
S52
D205
D206
D207
D208
S53
D209
D210
D211
D212
KS1/S54
D213
D214
D215
D216
KS2/S55
D217
D218
D219
D220
For example, the table below lists the segment output states for the S11 output pin.
No. 6086-12/27
LC75884E, LC75884W
Display data
Output pin state (S11)
D41
D42
D43
D44
0
0
0
0
The LCD segments for COM1,COM2,COM3 and COM4 are off.
0
0
0
1
The LCD segment for COM4 is on.
0
0
1
0
The LCD segment for COM3 is on.
0
0
1
1
The LCD segments for COM3 and COM4 are on.
0
1
0
0
The LCD segment for COM2 is on.
0
1
0
1
The LCD segments for COM2 and COM4 are on.
0
1
1
0
The LCD segments for COM2 and COM3 are on.
0
1
1
1
The LCD segments for COM2,COM3 and COM4 are on.
1
0
0
0
The LCD segment for COM1 is on.
1
0
0
1
The LCD segments for COM1 and COM4 are on.
1
0
1
0
The LCD segments for COM1 and COM3 are on.
1
0
1
1
The LCD segments for COM1,COM3 and COM4 are on.
1
1
0
0
The LCD segments for COM1 and COM2 are on.
1
1
0
1
The LCD segments for COM1,COM2 and COM4 are on.
1
1
1
0
The LCD segments for COM1,COM2 and COM3 are on.
1
1
1
1
The LCD segments for COM1,COM2,COM3 and COM4 are on.
Serial Data Output
1. When CL is stopped at the low level
Note: B0 to B3, A0 to A3CCB address
2. When CL is stopped at the high level
Note: B0 to B3, A0 to A3CCB address
CCB address ...... 43H
KD1 to KD30........ Key data
SA ........................ Sleep acknowledge data
Note: If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data(SA) will be invalid.
Output Data
1. KD1 to KD30 : Key data
When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and
one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the
relationship between those pins and the key data bits.
When the KS1/S54 and KS2/S55 output pins are selected to be segment outputs by control data bits K0 and K1 and a
key matrix of up to 20 keys is formed using the KS3 to KS6 output pins and the KI1 to KI5 input pins, the KD1 to
KD10 key data bits will be set to 0.
2. SA : Sleep acknowledge data
This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data
is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in sleep
mode and 0 in normal mode.
Sleep Mode Functions
Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment outputs will all go low and the common
outputs will also go low, and the oscillator on the OSC pin will stop (it will be started by a key press). This reduces
power dissipation. This mode is cleared by sending control data with both S0 and S1 set to 0. However, note that the
S1/P1 to S4/P4 outputs can be used as general-purpose output ports according to the state of the P0 to P2 control data
bits, even in sleep mode. (See the control data description for details.)
No. 6086-13/27
LC75884E, LC75884W
KI1
KI2
KI3
KI4
KI5
KS1/S54
KD1
KD2
KD3
KD4
KD5
KS2/S55
KD6
KD7
KD8
KD9
KD10
KS3
KD11
KD12
KD13
KD14
KD15
KS4
KD16
KD17
KD18
KD19
KD20
KS5
KD21
KD22
KD23
KD24
KD25
KS6
KD26
KD27
KD28
KD29
KD30
2. In normal mode
The pins KS1 to KS6 are set high.
When a key is pressed a key scan is started and the keys are scanned until all keys are released. Multiple key
presses are recognized by determining whether multiple key data bits are set.
If a key is pressed for longer than 800T(s) (Where T= ) the LC75884E/W outputs a key data read request (a
low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if
CE is high during a serial data transfer, DO will be set high.
After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75884E/W
performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1
and 10 k
).
No. 6086-14/27
LC75884E, LC75884W
Note:
*
3. In sleep mode the high/low state of these pins is determined by the S0 and S1 bits in the control data. Key scan output signals are not output from
pins that are set low.
1
----
fosc
Key Scan Operation Functions
1. Key scan timing
The key scan period is 384T(s). To reliably determine the on/off state of the keys, the LC75884E/W scans the keys
twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low
level on DO) 800T(s) after starting a key scan. If the key data dose not agree and a key was pressed at that point, it
scans the keys again. Thus the LC75884E/W cannot detect a key press shorter than 800T(s).
No. 6086-15/27
LC75884E, LC75884W
3. In sleep mode
The pins KS1 to KS6 are set to high or low by the S0 and S1 bits in the control data. (See the control data
description for details.)
If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the
OSC pin is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses
are recognized by determining whether multiple key data bits are set.
If a key is pressed for longer than 800T(s)(Where T= ) the LC75884E/W outputs a key data read request (a
low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if
CE is high during a serial data transfer, DO will be set high.
After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75884E/W
performs another key scan. However, this dose not clear sleep mode. Also note that DO, being an open-drain
output, requires a pull-up resistor (between 1 and 10 k
).
Sleep mode key scan example
Example: S0=0, S1=1 (sleep with only KS6 high)
Multiple Key Presses
Although the LC75884E/W is capable of key scanning without inserting diodes for dual key presses, triple key presses on
the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than
these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be
inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should
check the key data for three or more 1 bits and ignore such data.
1
----
fosc
Note:
*
4. These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the above
example. That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5
lines are pressed at the same time.
COM1
1/4 Duty, 1/2 Bias Drive Technique
COM2
COM3
COM4
LCD driver output when all LCD segments corresponding to
COM1, COM2, COM3 and COM4 are turned off.
LCD driver output when only LCD segments
corresponding to COM1 are on
LCD driver output when only LCD segments
corresponding to COM2 are on.
LCD driver output when LCD segments corresponding
to COM1 and COM2 are on.
LCD driver output when only LCD segments
corresponding to COM3 are on.
LCD driver output when LCD segments corresponding
to COM1 and COM3 are on.
LCD driver output when LCD segments corresponding
to COM2 and COM3 are on.
LCD driver output when LCD segments corresponding
to COM1, COM2 and COM3 are on.
LCD driver output when only LCD segments
corresponding to COM4 are on.
LCD driver output when LCD segments corresponding
to COM2 and COM4 are on.
LCD driver output when all LCD segments corresponding to
COM1, COM2, COM3 and COM4 are on.
VLCD
VLCD1, VLCD2
0 V
VLCD
VLCD1, VLCD2
0 V
VLCD
VLCD1, VLCD2
0 V
VLCD
VLCD1, VLCD2
0 V
VLCD
VLCD1, VLCD2
0 V
VLCD
VLCD1, VLCD2
0 V
VLCD
VLCD1, VLCD2
0 V
VLCD
VLCD1, VLCD2
0 V
VLCD
VLCD1, VLCD2
0 V
VLCD
VLCD1, VLCD2
0 V
VLCD
VLCD1, VLCD2
0 V
VLCD
VLCD1, VLCD2
0 V
VLCD
VLCD1, VLCD2
0 V
VLCD
VLCD1, VLCD2
0 V
VLCD
VLCD1, VLCD2
0 V
1/4 Duty, 1/2 Bias Waveforms
No. 6086-16/27
LC75884E, LC75884W
No. 6086-17/27
LC75884E, LC75884W
COM1
1/4 Duty, 1/3 Bias Drive Technique
COM2
COM3
COM4
LCD driver output when all LCD segments corresponding to
COM1, COM2, COM3 and COM4 are turned off.
LCD driver output when only LCD segments
corresponding to COM1 are on
LCD driver output when only LCD segments
corresponding to COM2 are on.
LCD driver output when LCD segments corresponding
to COM1 and COM2 are on.
LCD driver output when only LCD segments
corresponding to COM3 are on.
LCD driver output when LCD segments corresponding
to COM1 and COM3 are on.
LCD driver output when LCD segments corresponding
to COM2 and COM3 are on.
LCD driver output when LCD segments corresponding
to COM1, COM2 and COM3 are on.
LCD driver output when only LCD segments
corresponding to COM4 are on.
LCD driver output when LCD segments corresponding
to COM2 and COM4 are on.
LCD driver output when all LCD segments corresponding to
COM1, COM2, COM3 and COM4 are on.
VLCD
VLCD1
VLCD2
0 V
VLCD
VLCD1
VLCD2
0 V
VLCD
VLCD1
VLCD2
0 V
VLCD
VLCD1
VLCD2
VLCD
VLCD1
VLCD2
0 V
VLCD
VLCD1
VLCD2
0 V
VLCD
VLCD1
VLCD2
0 V
VLCD
VLCD1
VLCD2
0 V
VLCD
VLCD1
VLCD2
0 V
VLCD
VLCD1
VLCD2
0 V
VLCD
VLCD1
VLCD2
0 V
VLCD
VLCD1
VLCD2
0 V
VLCD
VLCD1
VLCD2
0 V
VLCD
VLCD1
VLCD2
0 V
VLCD
VLCD1
VLCD2
0 V
1/4 Duty, 1/3 Bias Waveforms
Voltage Detection Type Reset Circuit (VDET)
This circuit generates an output signal and resets the system when logic block power is first applied and when the voltage
drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage VDET,
which is 3.0V, typical. To assure that this function operates reliably, a capacitor must be added to the logic block power
supply line so that the logic block power supply voltage V
DD
rise time when the logic block power is first applied and the
logic block power supply voltage V
DD
fall time when the voltage drops are both at least 1 ms. (See Figure 3.)
Power Supply Sequence
The following sequences must be observed when power is turned on and off. (See Figure 3.)
Power on :Logic block power supply(V
DD
) on
LCD driver block power supply(V
LCD
) on
Power off:LCD driver block power supply(V
LCD
) off
Logic block power supply(V
DD
) off
However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off
at the same time.
System Reset
The LC75884E/W supports the reset methods described below. When a system reset is applied, display is turned off, key
scanning is stopped, and all the key data is reset to low. When the reset is cleared, display is turned on and key scanning
become possible.
1. Reset methods
(1) Reset at power-on and power-down
If at least 1 ms is assured as the logic block supply voltage V
DD
rise time when logic block power is applied, a system
reset will be applied by the VDET output signal when the logic block supply voltage is brought up. If at least 1 ms is
assured as the logic block supply voltage V
DD
fall time when logic block power drops, a system reset will be applied in
the same manner by the VDET output signal when the supply voltage is lowered. Note that the reset is cleared at the
point when all the serial data (the display data D1 to D220 and the control data) has been transferred, i.e., on the fall of
the CE signal on the transfer of the last direction data, after all the direction data has been transferred. However, the
above operations will be performed regardless of the state (high or low) of the RES pin. If RES is high, the reset will be
cleared at the point the above operations are completed. On the other hand, if RES is low, the system will remain in the
reset period as long as RES is not set high, even if the above operations are completed. (See Figure 3.)
No. 6086-18/27
LC75884E, LC75884W
(2) Reset when the logic block power supply voltage is in the allowable operating range (V
DD
= 4.5 to 6.0V)
The system is reset when the RES pin is set low, and the reset is cleared by setting RES pin high.
2. LC75884E/W internal block states during the reset period
CLOCK GENERATOR
Reset is applied and the base clock is stopped. However, the OSC pin state (normal or sleep mode) is determined
after the S0 and S1 control data bits are transferred.
COMMON DRIVER, SEGMENT DRIVER & LATCH
Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.
KEY SCAN
Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled.
KEY BUFFER
Reset is applied and all the key data is set to low.
CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER
Since serial data transfer is possible, these circuits are not reset.
No. 6086-19/27
LC75884E, LC75884W
Note: t1
1 [ms] (Logic block power supply voltage V
DD
rise time)
t2
0
t3
0
t4
1 [ms] (Logic block power supply voltage V
DD
fall time)
No. 6086-20/27
LC75884E, LC75884W
3. Output pin states during the reset period
X: don't care
Note:
*
5. These output pins are forcibly set to the segment output function and held low.
*
6. When power is first applied, these output pins are undefined until the S0 and S1 control data bits have been transferred.
*
7. Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 k
is required. This pin remains high during the reset period
even if a key data read operation is performed.
Output pin
State during reset
S1/P1 to S4/P4
L
*
5
S5 to S53
L
COM1 to COM4
L
KS1/S54, KS2/S55
L
*
5
KS3 to KS5
X
*
6
KS6
H
DO
H
*
7
Sample Application Circuit 1
1/2 bias (for use with normal panels)
No. 6086-21/27
LC75884E, LC75884W
Note:
*
8.
Add a capacitor to the logic block power supply line so that the logic block power supply voltage V
DD
rise time when power is applied and the
logic block power supply voltage V
DD
fall time when power drops are both at least 1 ms, as the LC75884E/W is reset by the VDET.
*
9.
If the RES pin is not used for system reset, it must be connected to the logic block power supply V
DD
.
*
10. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 k
) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
No. 6086-22/27
LC75884E, LC75884W
Sample Application Circuit 2
1/2 bias (for use with large panels)
Note:
*
8.
Add a capacitor to the logic block power supply line so that the logic block power supply voltage V
DD
rise time when power is applied and the
logic block power supply voltage V
DD
fall time when power drops are both at least 1 ms, as the LC75884E/W is reset by the VDET.
*
9.
If the RES pin is not used for system reset, it must be connected to the logic block power supply V
DD
.
*
10. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 k
) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
No. 6086-23/27
LC75884E, LC75884W
Sample Application Circuit 3
1/3 bias (for use with normal panels)
Note:
*
8.
Add a capacitor to the logic block power supply line so that the logic block power supply voltage V
DD
rise time when power is applied and the
logic block power supply voltage V
DD
fall time when power drops are both at least 1 ms, as the LC75884E/W is reset by the VDET.
*
9.
If the RES pin is not used for system reset, it must be connected to the logic block power supply V
DD
.
*
10. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 k
) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
No. 6086-24/27
LC75884E, LC75884W
Sample Application Circuit 4
1/3 bias (for use with large panels)
Note:
*
8.
Add a capacitor to the logic block power supply line so that the logic block power supply voltage V
DD
rise time when power is applied and the
logic block power supply voltage V
DD
fall time when power drops are both at least 1 ms, as the LC75884E/W is reset by the VDET.
*
9.
If the RES pin is not used for system reset, it must be connected to the logic block power supply V
DD
.
*
10. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 k
) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
Notes on transferring display data from the controller
The display data (D1 to 220) is transferred to the LC75884E/W in four operations. All of the display data should be
transferred within 30 ms to maintain the quality of the displayed image.
Notes on the controller key data read techniques
1. Timer based key data acquisition
(1) Flowchart
(2) Timing chart
t5: Key scan execution time when the key data agreed for two key scans. (800T(s))
t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again.
(1600T(s))
t7: Key address (43H) transfer time
t8: Key data read time
(3) Explanation
In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must
check the DO state when CE is low every t9 period without fail. If DO is low, the controller recognizes that a key has
been pressed and executes the key data read operation.
The period t9 in this technique must satisfy the following condition.
t9>t6+t7+t8
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
1
T = ------
fosc
No. 6086-25/27
LC75884E, LC75884W
No. 6086-26/27
LC75884E, LC75884W
2. Interrupt based key data acquisition
(1) Flowchart
(2) Timing chart
t5: Key scan execution time when the key data agreed for two key scans. (800T(S))
t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again.
(1600T(S))
t7: Key address (43H) transfer time
t8: Key data read time
1
T = ------
fosc
PS No. 6086-27/27
LC75884E, LC75884W
(3) Explanation
In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller
must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and
executes the key data read operation. After that the next key on/off determination is performed after the time t10 has
elapsed by checking the DO state when CE is low and reading the key data. The period t10 in this technique must
satisfy the following condition.
t10 > t6
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
This catalog provides information as of February, 1999. Specifications and information herein are subject
to change without notice.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer's products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
PDF 
ZIP