Ordering number : EN6015
11999RM (OT) No. 6015-1/31
Overview
The LC78622NE is a CMOS IC that implements the
signal processing and servo control required by compact
disc players. At the same time as providing an EFM PLL
circuit, a 1-bit D/A converter, and an analog low-pass
filter the LC78622NE realizes an optimal cost-
performance tradeoff for low-end players by strictly
limiting functionality to basic signal-processing and servo
system functionality. The LC78622NE signal-processing
system provides demodulation of the EFM signal from the
pickup, de-interleaving, error detection and correction, and
digital filters that can prove useful in reducing the cost of
end products. The LC78622NE servo control system
processes servo commands sent from the control
microprocessor.
The LC78622NE is an improved version of the LC78622E
that adds 8
oversampling digital filters, three general-
purpose output ports (that also have specific shared
functions) and the PCCL pin (pin 34). However, some
handling of general-purpose ports differ from that of the
LC78622E, therefore care must be taken.(Refer to pages
16 and 21).
Functions
Input signal processing: The LC78622NE takes an HF
signal as input, digitizes (slices) that signal at a precise
level, converts that signal to an EFM signal, and
generates a PLL clock with an average frequency of
4.3218 MHz by comparing the phases of that signal and
an internal VCO.
Precise reference clock and necessary internal timing
generation using an external 16.9344 MHz crystal
oscillator
Disk motor speed control using a frame phase difference
signal generated from the playback clock and the
reference clock
Frame synchronization signal detection, protection and
interpolation to assure stable data readout
EFM signal demodulation and conversion to 8-bit
symbol data
Subcode data separation from the EFM demodulated
signal and output of that data to an external
microprocessor
Subcode Q signal output to a microprocessor over the
serial I/O interface after performing a CRC error check
(LSB first)
Demodulated EFM signal buffering in internal RAM to
handle up to 4 frames of disk rotational jitter
Demodulated EFM signal reordering in the prescribed
order for data unscrambling and de-interleaving
Error detection, correction, and flag processing (error
correction scheme: dual C1 plus dual C2 correction)
Sets the C2 flags based on the C1 flags and a C2 check,
and then performs signal interpolation or muting
depending on the C2 flags. The interpolation circuit uses
a dual-interpolation scheme. The previous value is held
if the C2 flags indicate errors two or more times
consecutively.
Support for command input from a control
microprocessor: commands include track jump, focus
start, disk motor start/stop, muting on/off and track
count (8 bit serial input)
Built-in digital output circuits.
Arbitrary track counting to support high-speed data
access
D/A converter outputs with data continuity improved by
8
oversampling digital filters.
Built-in third-order
D/A converters (An analog low-
pass filter is built in.)
LC78622NE
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
Compact Disc Player DSP
CMOS IC
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
Built-in digital attenuator (8 bits alpha, 239 steps)
Built-in digital de-emphasis
Zero cross muting
Supports the implementation of a double-speed dubbing
function.
Support for bilingual applications.
General-purpose I/O ports: 5 pins
Features
5 V single-voltage power supply
Package Dimensions
unit: mm
3159-QFP64E
No. 6015-2/31
LC78622NE
14.0
17.2
1.0
1.0
1.6
0.15
0.35
0.1
15.6
0.8
0.8
3.0max
1
16
17
32
33
48
49
64
2.7
14.0
17.2
1.0
1.0
1.6
0.8
SANYO: QFP64E (QIP64E)
[LC78622NE]
Equivalent Circuit Block Diagram
No. 6015-3/31
LC78622NE
Pin Assignment
Specifications
Absolute Maximum Ratings
at Ta = 25C, V
SS
= 0 V
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
DD
max
V
SS
0.3 to V
SS
+ 7.0
V
Input voltage
V
IN
V
SS
0.3 to V
DD
+ 0.3
V
Output voltage
V
OUT
V
SS
0.3 to V
DD
+ 0.3
V
Allowable power dissipation
Pd max
300
mW
Operating temperature
Topr
20 to +75
C
Storage temperature
Tstg
40 to +125
C
No. 6015-4/31
LC78622NE
Allowable Operating Ranges
at Ta = 25C, V
SS
= 0 V
Parameter
Symbol
Conditions
min
typ
max
Unit
V
DD
(1)
V
DD
, XV
DD
, LV
DD
, RV
DD
, VV
DD
:
3.6
5.5
V
During normal-speed playback
Supply voltage
V
DD
(2)
V
DD
, XV
DD
, LV
DD
, RV
DD
, VV
DD
:
3.6
5.5
V
During double-speed playback
V
IH
(1)
DEFI, COIN, RES, HFL, TES, SBCK, RWC, CQCK,
Input high level voltage
TAI, TEST1 to TEST5, CS, CONT1 to CONT5, PCCL
0.7 V
DD
V
DD
V
V
IH
(2)
EFMIN
0.6 V
DD
V
DD
V
V
IL
(1)
DEFI, COIN, RES, HFL, TES, SBCK, RWC, CQCK,
Input low level voltage
TAI, TEST1 to TEST5, CS, CONT1 to CONT5, PCCL
0
0.3 V
DD
V
V
IL
(2)
EFMIN
0
0.4 V
DD
V
Data setup time
t
SU
COIN, RWC: Figure 1
400
ns
Data hold time
t
HD
COIN, RWC: Figure 1
400
ns
High level clock pulse width
t
WH
SBCK, CQCK: Figures 1, 2 and 3
400
ns
Low level clock pulse width
t
WL
SBCK, CQCK: Figures 1, 2 and 3
400
ns
Data read access time
t
RAC
SQOUT, PW: Figures 2 and 3
0
400
ns
Command transfer time
t
RWC
RWC: Figure 1
1000
ns
Subcode Q read enable time
t
SQE
WRQ: Figure 2, with no RWC signal
11.2
ms
Subcode read cycle time
t
SC
SFSY: Figure 3
136
s
Subcode read enable time
t
SE
SFSY: Figure 3
400
ns
Port input data setup time
t
CSU
CONT1 to CONT5, RWC: Figure 4
400
ns
Port input data hold time
t
CHD
CONT1 to CONT5, RWC: Figure 4
400
ns
Port input clock setup time
t
RCQ
RWC, CQCK: Figure 4
100
ns
Port output data delay time
t
CDD
CONT1 to CONT8, RWC: Figure 5
1200
ns
Input level
V
IN
(1)
EFMIN: Slice level control
1.0
Vp-p
V
IN
(2)
X
IN
: Capacitor-coupled input
1.0
Vp-p
Operating frequency range
fop
EFMIN
10
MHz
Crystal oscillator frequency
f
X
X
IN
, X
OUT
16.9344
MHz
Electrical Characteristics
at Ta = 25C, V
DD
= 5 V, V
SS
= 0 V
Parameter
Symbol
Conditions
min
typ
max
Unit
Current drain
I
DD
V
DD
, XV
DD
, LV
DD
, RV
DD
, VV
DD
25
35
mA
DEFI, EFMIN, COIN, RES, HFL, TES, SBCK,
Input high level current
I
IH
(1)
RWC, CQCK: TEST1: V
IN
= V
DD
5
A
I
IH
(2)
TAI, TEST2 to TEST5, CS, PCCL: V
IN
= V
DD
= 5.5 V
25
75
A
DEFI, EFMIN, COIN, RES, HFL, TES, SBCK, RWC,
Input low level current
I
IL
CQCK: TAI, TEST1 to TEST5, CS, PCCL: V
IN
= 0 V
5
A
EFMO, CLV
+
, CLV
, V/P, PCK, FSEQ, TOFF,
V
OH
(1)
TGL, JP
+
, JP
, EMPH/CONT6, EFLG, FSX: I
OH
= 1 mA
4
V
MUTEL/CONT7, MUTER/CONT8, C2F, SBSY, PW,
Output high level voltage
V
OH
(2)
SFSY, WRQ, SQOUT, TST11, 16M, 4.2M, CONT1 to
4
V
CONT5: I
OH
= 0.5 mA
V
OH
(3)
DOUT: I
OH
= 12 mA
4.5
V
EFMO, CLV
+
, CLV
, V/P, PCK, FSEQ,
V
OL
(1)
TOFF, TGL, JP
+
, JP
, EMPH/CONT6, EFLG, FSX:
1
V
I
OH
= 1 mA
Output low level voltage
MUTEL/CONT7, MUTER/CONT8,
V
OL
(2)
C2F, SBSY, PW, SFSY, WRQ, SQOUT,
0.4
V
TST11, 16M, 4.2M, CONT1 to CONT5:
I
OH
= 2 mA
V
OL
(3)
DOUT: I
OH
= 12 mA
0.5
V
I
OFF
(1)
PDO, CLV
+
, CLV
, JP
+
, JP
, CONT1 to CONT5:
5
A
V
OUT
= V
DD
Output off leakage current
I
OFF
(2)
PDO, CLV
+
, CLV
, JP
+
, JP
, CONT1 to CONT5:
5
A
V
OUT
= 0 V
Charge pump output current
I
PDOH
PDO: R
ISET
= 68 k
64
80
96
A
I
PDOL
PDO: R
ISET
= 68 k
96
80
64
A
No. 6015-5/31
LC78622NE
One-Bit D/A Converter Analog Characteristics
at Ta = 25C, V
DD
= LV
DD
= RV
DD
= 5 V, V
SS
= LV
SS
= RV
SS
= 0 V
Note: Measured with the normal-speed playback mode in the Sanyo one-bit D/A converter block reference digital attenuator circuit set to EE (hexadecimal).
Parameter
Symbol
Conditions
min
typ
max
Unit
Total harmonic distortion
THD + N
LCHO, RCHO; 1 kHz: 0 dB data input,
0.009
0.012
%
using the 20 kHz low-pass filter (AD725D built in)
LCHO, RCHO; 1 kHz: 60 dB data input,
Dynamic range
DR
using the 20 kHz low-pass filter and the A filter
87
90
dB
(AD725D built in)
LCHO, RCHO; 1 kHz: 0 dB data input,
Signal-to-noise ratio
S/N
using the 20 kHz low-pass filter and the A filter
93
95
dB
(AD725D built in)
Crosstalk
CT
LCHO, RCHO; 1 kHz: 0 dB data input,
82
84
dB
using the 20 kHz low-pass filter (AD725D built in)
Figure 1 Command Input
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