LC7940YD,7941YD
SANYO Electric Co., Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
63099RM (ID) No. 6158--1/11
Ordering number: EN 6158
s
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
s
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
CMOS IC
Dot-matrix LCD Drivers
Overview
The LC7940YD and LC7941YD are segment driver ICs
for driving large, dot
matrix LCD displays. They read 4
bit parallel or serial input, display data from a controller
into an 80
bit latch, and then generate LCD drive signals
corresponding to that data.
The LC7940YD and LC7941YD feature mirror
image pin
assignments, allowing them to be used together to increase
component density. They are designed to be used with the
LC7942YD common driver to drive large LCD panels.
Features
80 built
in LCD display drive circuits
1/8 to l/128display duty cycle
Serial or 4
bit parallel data input
Chip disable for low power dissipation for large
sized
panels
Bias supply voltags can be supplied externally
Operating supply voltage and ambient temperature
- 2.7 to 5.5 V logic supply ( V
DD
) at Ta =
20 to +85C
- 8 to 20V LCD supply (V
DD
V
EE
) at Ta =
20 to
+85 C
CMOS process
100
pin flat plastic package
Package Dimensions
unit: mm
3180
QIP100D
Specifications
Absolute Maximum Ratings
at Ta = 25 2C, V
SS
= 0 V
[LC7940YD, LC7941YD]
21.6
0.8
2.45max
1.6
17.2
0.15
2.15
15.6
0.3
14.0
0.65
0.825
100
0.8
1
30
31
50
51
80
81
1.6
0.575
20.0
23.2
0.65
SANYO : QFP100D (QIP100D)
Parameter
Symbol
Ratings
Unit
Logic supply voltge
V
DD
max
0.3 to +7.0
V
LCD supply voltage, See Note below.
V
DD
V
EE
max
0 to 22
V
Input voltage
V
I
max
0.3 to V
DD
+ 03
V
LC7940YD, LC7941YD
No. 6158--2/11
Note
V
DD
V
1
> V
3
> V
4
> V
EE
Recommended Operating Condltions
at Ta =
20 to + 85C, V
SS
= 0V
Notes
1. V
DD
V
l
> V
3
> V
4
> V
EE
2. At turn ON, the LCD supply should be energized after or simultaneously with the logic supply. At turn OFF, the logic supply
should be cut after or simultaneously with the LCD supply.
Electrlcai Characterfstlcs
at Ta = 25 2C,V
SS
= 0V, V
DD
= 2.7 to 5.5 V
Operating temperature range
T
opr
20 to +85
C
Storage temperature range
T
stg
40 to +125
C
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Logic supply voltage
V
DD
2.7
5.5
V
LCD supply voltage
V
DD
V
EE
See Notes 1 and 2.
8
20
V
HIGHlevel input voltage
V
IH
CP, CDl, DI1 to DI3, M,
SDl, P/S, DISPOFF and
LOAD
0.8V
DD
V
LOWlevel inpvt voltage
V
IL
CP, CDI, Dl1 to DI3, M,
SDl, P/S,DISPOFF and
LOAD
0.2V
DD
V
CP shift clock frequency
f
CP
3.3
MHz
CP pulsewidth
t
WC
100
ns
LOAD pulsewidth
t
WL
100
ns
DIn and SDI to CP setup time
t
SETUP
80
ns
DIn and SDI to CP hold time
t
HOLD
80
ns
CP to LOAD time
t
CL1
0
ns
t
CL2
100
ns
LOAD to CP time
t
LC
100
ns
CP rise time
t
R
50
ns
CP fall time
t
F
50
ns
LOAD rise time
t
RL
50
ns
LOAD fall time
t
FL
50
ns
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
HIGHlevel input current
I
IH
V
IN
=V
DD
; LOAD, CP, CDI,
P/S, DI1 to DI3, SDl, M,
and DISPOFF
1
A
LOWlevel input current
I
IL
V
IN
= V
SS
; LOAD, CP, CDl,
P/S, DI1 to DI3, SDI, M,
and DISPOFF
1
A
CDO HIGHlevel output voltage
V
OH
I
OH
= 400 A
V
DD
0.4
V
CDO LOWlevef output voltage
V
OL
I
OL
= 400 A
0.4
V
O1 to O80 driver ON resistance
R
ON
V
DD
V
EE
= 18 V,
|V
DE
V
O
|= 0.25 V.
See note
2
4
k
Parameter
Symbol
Ratings
Unit
LC7940YD, LC7941YD
No. 6158--4/11
Pad Layout (Top view)
050
049
048
047
046
045
044
043
042
041
040
039
038
037
036
035
034
033
032
031
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
080
079
078
077
076
075
074
073
072
071
070
069
068
067
066
065
064
063
062
061
060
059
058
057
056
055
054
053
052
051
080
079
078
077
076
075
074
073
072
071
070
069
068
067
066
065
064
063
062
061
060
059
058
057
056
055
054
053
052
051
LC7940YD
LC7941YD
031
032
033
034
035
036
037
038
039
040
041
042
043
044
045
046
047
048
049
050
NC
CDO
NC
DISP OFF
P/S
V
SS
V
EE
V4
V3
NC
V
DD
V1
M
DI1
DI2
DI3
SDI
LOAD
CDI
CP
CP
CDI
LOAD
SDI
DI3
DI2
DI1
M
V1
V
DD
NC
V3
V4
V
EE
V
SS
P/S
DISP OFF
NC
CDO
NC
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
LC7940YD, LC7941YD
No. 6158--5/11
Block Diagram
Pin Functions
4 Level LCD Drive Circuit
(80 bits)
Level Shifter (80 bits)
2nd Latch (80 bits)
1st Latch (80 bits)
Address Decoder
4 bits
Data Bus
Interface
Address Counter
(7 bits)
Chip Disable &
Latch Control
SER/PAR
Control
CLK
80
80
80
20
4
V1
01
02
03
079 080
V3
V4
M
SDI
DI3
DI2
DI1
P/S
CDO
DISP OFF
V
SS
V
DD
CDI
CP
LOAD
V
EE
Pin No.
Synbol
I/O
Functions
LC7940YD
LC7941YD
91
90
V
DD
Supply
V
DD
V
SS
is the logic supply.
V
DD
V
EE
is the LCD supply.
86
95
V
SS
87
94
V
EE
92
89
V
1
Supply
LCD panel drive voltage supplies
V
1
and V
EE
are selected levels.
V
3
and V
4
are notselected levels.
89
92
V
3
88
93
V
4
l00
81
CP
I
Display data Input clock (fallingedge trigger).
99
82
CDI
I
Chip disable.
Data is read in when LOW, and not road in when HIGH.
98
83
LOAD
I
Display data latch clock (fallingedge trigger).
On the falling edge, the LCD drive signals set by the display data are output.
97
84
SDI
I
Serial data input.
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