43097 (OT) No. 5601-1/8
Overview
The LC82151 is a facsimile controller that integrates the
main functions required by facsimile systems on a single
chip. The LC82151 includes a FAX modem with ADPCM
and HDLC functions, image processing functions that can
create high-quality binary image data without external
memory, a CODEC accelerator, a CPU and CPU
peripheral circuits, general-purpose I/O ports, and other
functions. A facsimile system with excellent cost-
performance characteristics can be created easily by
providing ROM and RAM.
Functions
CPU and peripheral circuits
High-speed 16-bit CPU (65C816) operating at
7.4 MHz
16-MB program address space
CODEC accelerator
Two-channel DMA controller
Four 16-bit timers
16-bit watchdog timer
TPH interface
Serial I/O interface
Parallel I/O: 10 to 43 pins
Image processing
Processes 2048 pixels per line
Processing speed: 540 ns per pixel (maximum)
Built-in 8-bit A/D converter (Includes a sensor signal
delay function.)
Sensor drive circuit (Supports CCDs and all major
CIS devices.)
Distortion correction (White distortion: 8-pixel
averaging correction, black correction: Allows the
black correction subtraction data to be set.)
-correction (Supports user-defined correction curves.)
Simple binary conversion processing (fixed threshold
and density-adaptive threshold)
Halftone processing error diffusion method (64 levels)
Image reduction (decimation, fine black line retention,
and fine white line retention)
Modem
Group 3 FAX modem
ITU-T V.29 (9600, 7200, and 4800 bps)
ITU-T V.27ter (4800 and 2400 bps)
ITU-T V.21ch2 (300 bps)
Simultaneous high/low-speed wait function
Short training function (ITU-T V.27ter only)
HDLC function (for all transmission speeds)
Synthesizer function
Caller ID function
Bell 202 (1200 bps)
ITU-T V.23 (1200 bps)
ADPCM function
Encoding: 2, 3, or 4 bits
Sampling frequencies: 9.6, 7.2, 4.8, and 3.6 kHz
RTC low-voltage backup
5-V single-voltage power supply
Package Dimension
unit: mm
3214-SQFP144
Preliminary
SANYO: SQFP144
[LC82151]
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
CMOS LSI
LC82151
Single-Chip Facsimile Controller
No.
*
5601
No. 5601-2/8
LC82151
Block Diagram
PA7 to PA0
PB2 to PB0
D7 to D0
A19 to A0
PXD7 to PXD0
PDREQ, PDACK
CPU
65C816
Image
processing
Modem
CODEC
accelerator
RTC
DMAC
SIO
WDT
Interrupt
controller
INT2
INT8
ROSC1
ROSC2
TXA, RXA,
PGCO, PGCI, V
REF
,
RIN, VCOI, PHASEO,
EYED, EYECLK,
EYESYNC
2, RES, R/W,
IRQ, VP, RDY,
BE, NMI, VPA,
VDA, ABCNT
AIN, ATAP, TEMP, SH, RS, ACLK1,
ACLK2, ASAMP, DAREFH, DAREFL
RAS
CAS
DRAM
controller
TPH interface
PIO
Timer
CPU
interface
RD, WR
ROMCS, RAMCS,
IOCS, MCS
BREQ, BACK, EXRDY
TO0
TO1
RTC, CTS,
DSR, DTR,
RI, DCD
TD, RD
PCK/SCLK,
PDATA/TXD,
EXCLK,
LATCH/RXD,
STB0 to STB3,
HVON
PROTECT
XTAL1, XTAL2,
XOUT,CLKIN,
RESET,
BACKUP
TEST2 to TEST0
TESTOUT
Pin No.
Pin
I/O
Pin function
1
V
SS
P
Ground
2
VP
I
ICE vector address signal
3
RDY
O
ICE ready signal
4
VPA
I
ICE valid program address signal
5
VDA
I
ICE valid data address signal
6
A19
O
7
A18
O
Address bus
8
A17
O
9
A16
O
10
D7
B
11
D6
B
12
D5
B
13
D4
B
Data bus
14
D3
B
15
D2
B
16
D1
B
17
D0
B
18
V
DD
P
Power supply
19
V
SS
P
Ground
20
RD
O
Read signal from the CPU
21
WR
O
Write signal from the CPU
22
ROMCS
O
Program ROM chip select signal
23
RAMCS
O
Working RAM chip select signal
24
IOCS
O
External I/O chip select signal
25
MCS
O
External I/O chip select signal
26
RAS/PG1
B
DRAM row address strobe/general-purpose port G
27
CAS/PG2
B
DRAM column address strobe/general-purpose port G
28
PA7
B
29
PA6
B
30
PA5
B
31
PA4
B
General-purpose port A
32
PA3
B
33
PA2
B
34
PA1
B
35
PA0
B
36
V
SS
P
Ground
37
V
DD
P
Power supply
38
RIN
I
PLL bias input
39
PHASEO
O
PLL phase detector output
40
VCOI
I
PLL voltage-controlled oscillator input
41
INT8/PB7
B
External interrupt request signal/general-purpose port B
42
INT2/PB6
B
43
BACK/PB5
B
CPU bus acknowledge signal/general-purpose port B
44
BREQ/PB4
B
CPU bus request signal/general-purpose port B
45
EXRDY/PB3
B
External ready input/general-purpose port B
46
PB2
B
47
PB1
B
General-purpose port B
48
PB0
B
49
NMI
I
Non-maskable interrupt request signal
50
TEST2
I
Test pin
No. 5601-3/8
LC82151
Type
I
Input pins
B
Bidirectional pins
NC
No connection
O
Output pins
P
Power pins
Continued on next page.
Pin Assignment
No. 5601-4/8
LC82151
Continued from preceding page.
Pin No.
Pin
I/O
Pin function
51
TEST1
I
52
TEST0
I
Test pins
53
TESTOUT
I
54
V
DD
P
Power supply
55
V
SS
P
Ground
56
ROSC1
I
RTC crystal oscillator connections
57
ROSC2
O
58
BACKUP
I
Low power mode input
59
RESET
I
System reset signal
60
AV
DD
P
Analog system power supply
61
AV
SS
P
Analog system ground
62
AIN
I
Sensor signal input
63
TEMP
I
Thermistor input
64
ATAP
O
A/D converter reference voltage output
65
DAREFH
I
D/A converter high-level reference voltage input
66
DAREFL
I
D/A converter low-level reference voltage input
67
TXA
O
Modem analog transmit output
68
RXA
I
Modem analog receive input
69
PGCO
O
Modem gain adjustment output
70
PGCI
I
Modem gain adjustment input
71
V
REF
I
Modem analog block reference input
72
V
SS
P
Ground
73
V
DD
P
Power supply
74
SH
O
Image sensor start pulse
75
RS
O
Image sensor reset pulse
76
ACLK1
O
Image sensor data transfer clocks
77
ACLK2
O
78
ASAMP
O
Built-in A/D converter sampling point monitor signal
79
PXD7/PC7
B
80
PXD6/PC6
B
81
PXD5/PC5
B
82
PXD4/PC4
B
Image data output/general-purpose port C
83
PXD3/PC3
B
84
PXD2/PC2
B
85
PXD1/PC1
B
86
PXD0/PC0
B
87
PDREQ/PF7
B
Image data DMA request signal/general-purpose port F
88
PDACK/PF6
B
Image data DMA acknowledge signal/general-purpose port F
89
EYED/PF5
B
Eye pattern data output/general-purpose port F
90
V
DD
P
Power supply
91
V
SS
P
Ground
92
EYECLK/PF4
B
Eye pattern data clock/general-purpose port F
93
EYESYNC/PF3
B
Eye pattern data synchronizing signal/general-purpose port F
94
TO1/PF2
B
Timer outputs/general-purpose port F
95
TO0/PF1
B
96
PCK/SCLK/PE7
B
Thermal head data transfer clock/serial I/O clock/general-purpose port E
97
PDATA/TXD/PE6
B
Thermal head serial output data/serial I/O send data/general-purpose port E
98
EXCLK/PE5
B
Thermal head control external clock/general-purpose port E
99
LATCH/RXD/PE4
B
Thermal head data latch signal/serial I/O receive data/general-purpose port E
100
STB3/PE3
B
101
STB2/PE2
B
Thermal head strobe signal/general-purpose port E
102
STB1/PE1
B
103
STB0/PE0
B
104
HVON/PF0
B
Head power on/off control signal/general-purpose port F
105
PROTECT/PG0
B
Head protection abnormality indication signal input/general-purpose port G
Continued on next page.
No. 5601-5/8
LC82151
Pin No.
Pin
I/O
Pin function
106
XTAL1
I
System clock crystal oscillator element connection (29.4912 MHz)
107
XTAL2
O
108
V
SS
P
Ground
109
V
DD
P
Power supply
110
XOUT
O
Crystal oscillator clock output
111
CLKIN
I
System clock input
112
A15
B
113
A14
B
114
A13
B
115
A12
B
Address bus
116
A11
B
117
A10
B
118
A9
B
119
A8
B
120
TD/PD7
B
Serial port transmit data output/general-purpose port D
121
RD/PD6
B
Serial port receive data input/general-purpose port D
122
RTS/PD5
B
Request to send signal/general-purpose port D
123
CTS/PD4
B
Clear to send signal/general-purpose port D
124
DSR/PD3
B
Data set ready/general-purpose port D
125
DTR/PD2
B
Data terminal ready/general-purpose port D
126
V
DD
P
Power supply
127
V
SS
P
Ground
128
RI/PD1
B
Ring indicator/general-purpose port D
129
DCD/PD0
B
Data carrier detect/general-purpose port D
130
A7
B
131
A6
B
132
A5
B
133
A4
B
Address bus
134
A3
B
135
A2
B
136
A1
B
137
A0
B
138
ABCNT
O
ICE bus control signal
139
BE
O
ICE bus enable signal
140
2
O
ICE system clock
141
RES
O
ICE reset signal
142
RWB
I
ICE read/write signal
143
IRQ
O
ICE interrupt request signal
144
V
DD
P
Power supply
Continued from preceding page.
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