91400 RM (IM) HS No.6695-1/20
Ver.1.01
N1798
Preliminary
Overview
The LC863332/28/24/20/16A are 8-bit single chip microcontrollers with the following on-chip functional blocks:
- CPU : Operable at a minimum bus cycle time of 0.424
s
- On-chip ROM capacity
Program ROM : 32K/28K/24K/20K/16K bytes
CGROM : 16K bytes
- On-chip RAM capacity : 512 bytes
- OSD RAM : 352
9 bits
- Five channels
8-bit AD Converter
- Three channels
7-bit PWM
- Two 16-bit timer/counters, 14-bit base timer
- 8-bit synchronous serial interface circuit
- IIC-bus compliant serial interface circuit (Multi-master type)
- ROM correction function
- 15-source 9-vectored interrupt system
- Integrated system clock generator and display clock generator
X'tal oscillator (32.768kHz) for PLL reference is used for TV control.
All of the above functions are fabricated on a single chip.
8-Bit Single Chip Microcontroller
LC863332/28/24/20/16A
Ordering number : ENN*6695
CMOS IC
LC863332/28/24/20/16A
No.6695-2/20
Features
(1) Read-Only Memory (ROM) :
32768
8 bits / 28672
8 bits / 24576
8 bits
20480
8 bits / 16384
8 bits for program
16128
8 bits for CGROM
(2) Random Access Memory (RAM) :
512
8 bits (including 128 bytes for ROM correction function)
352
9 bits (for CRT display)
(3) OSD functions
- Screen display
: 36 characters
16 lines (by software)
- RAM
: 352 words (9 bits per word)
Display area
: 36 words
8 lines
Control area
: 8 words
8 lines
- Characters
Up to 252 kinds of 16
32 dot character fonts
(4 characters including 1 test character are not programmable)
Each font can be divided into two parts and used as two fonts :
a
16
17 dot and 8
9 dot character font
- Various character attributes
Character colors
: 16 colors
Character background colors
: 16 colors
Fringe / shadow colors
: 16 colors
Full screen colors
: 16colors
Rounding
Underline
Italic
character
(slanting)
- Attribute can be changed without spacing
- Vertical display start line number can be set for each row independently (Rows can be overlapped)
- Horizontal display start position can be set for each row independently
- Horizontal pitch (bit 9 - 16)
*1
and vertical pitch (bit-32) can be set for each row independently
- Different display modes can be set for each row independently
Caption
Text mode / OSD mode 1 / OSD mode 2 (Quarter size) / Simplifed graphic mode
- Ten character sizes
*1
Horez.
Vert. = (1
1), (1
2), (2
2), (2
4), (0.5
0.5)
(1.5
1), (1.5
2), (3
2), (3
4), (0.75
0.5)
- Shuttering and scrolling on each row
- Simplified Graphic Display
*1 Note : range depends on display mode : refer to the manual for details.
(4) Bus Cycle Time / Instruction-Cycle Time
Bus cycle time
Instruction cycle time
System clock oscillation
Oscillation Frequency
Voltage
0.424
s 0.848
s
Internal VCO
(Ref : X'tal 32.768kHz)
14.156MHz 4.5V
to
5.5V
7.5
s 15.0
s
Internal RC
800kHz
4.5V to
5.5V
183.1
s 366.2
s
Crystal 32.768kHz
4.5V
to
5.5V
(5) Ports
- Input / Output Ports
: 5 ports (28 terminals)
Data direction programmable in nibble units
: 1 port (8 terminals)
(If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.)
Data direction programmable for each bit individually
: 4 ports (20 terminals)
- Input port
: 1 port (1 terminal)
LC863332/28/24/20/16A
No.6695-3/20
(6) AD converter
- 5 channels
8-bit AD converters
(7) Serial interfaces
- IIC-bus compliant serial interface (Multi-master type)
Consists of a single built-in circuit with two I/O channels. The two data lines and two clock lines can be connected
internally.
- Synchronous 8-bit serial interface
(8) PWM output
- 3 channels
7-bit PWM
(9) Timer
- Timer 0 : 16-bit timer/counter
With 2-bit prescaler + 8-bit programmable prescaler
Mode 0 : Two 8-bit timers with a programmable prescaler
Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with a programmable prescaler
Mode 3 : 16-bit counter
The resolution of timer is 1 tCYC.
- Timer 1 : 16-bit timer/PWM
Mode 0 : Two 8-bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : Variable bit PWM (9 to 16 bits)
In mode0/1,the resolution of Timer1/PWM is 1 tCYC
In mode2/3,the resolution is selectable by program; tCYC or 1/2 tCYC
- Base timer
Generate every 500ms overflow for a clock application (using 32.768kHz crystal oscillation for the base timer clock)
Generate every 976
s, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768kHz crystal oscillation for the base timer
clock)
Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler
output of Timer 0
(10) Remote control receiver circuit (connected to the P73/INT3/T0IN terminal)
- Noise rejection function
- Polarity switching
(11) Watchdog timer
External RC circuit is required
Interrupt or system reset is activated when the timer overflows
(12) ROM correction function
Max 128 bytes / 2 addresses
(13) Interrupts
- 15 sources 9 vectored interrupts
1. External Interrupt INT0
2. External Interrupt INT1
3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits)
4. External Interrupt INT3, base timer
5. Timer/counter T0H (Upper 8 bits)
6.
Timer
T1H,T1L
7.
SIO0
8. Vertical synchronous signal interrupt ( VS ), horizontal line (
HS
), AD
9. IIC, Port 0
LC863332/28/24/20/16A
No.6695-4/20
- Interrupt priority control
Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high
priority can be assigned to the interrupts from 3 to 9 listed above. For the external interrupt INT0 and INT1, high
or highest priority can be set.
(14) Sub-routine stack level
- A maximum of 128 levels (stack is built in the internal RAM)
(15) Multiplication/division instruction
-
16
bits
8 bits (7 instruction cycle times)
- 16 bits / 8 bits (7 instruction cycle times)
(16) 3 oscillation circuits
- Built-in RC oscillation circuit used for the system clock
- Built-in VCO circuit used for the system clock and OSD
- X'tal oscillation circuit used for base timer, system clock and PLL reference
(17) Standby function
- HALT mode
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is
stopped. This mode can be released by the interrupt request or the system reset.
- HOLD mode
The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X'tal oscillations. This mode can be
released by the following conditions.
Pull the reset terminal ( RES ) to low level.
Feed the selected level to either P70/INT0 or P71/INT1.
Input the interrupt condition to Port 0.
(18) Package
- DIP42S
- QIP48E
(19) Development tools
- Flash EEPROM:
LC86F3348A
- Evaluation chip:
LC863096
- Emulator:
EVA86000 (main) + ECB863200 (evaluation chip board)
+ POD863300 (pod: DIP42S) or POD863301 (QIP48E)
LC863332/28/24/20/16A
No.6695-5/20
System Block Diagram
Interrupt Control
Standby Control
Cl
o
c
k
Ge
n
e
r
a
t
o
r
X'tal
VCO
RC
PLL
IR
PLA
ROM
PC
ACC
B Register
C Register
ALU
PSW
RAR
RAM
Stack Pointer
Port 0
Watch Dog Timer
ROM Correct Control
XRAM
Bus Interface
Port 1
Port 6
Port 7
Port 8
OSD
Control
Circuit
VRAM
CGROM
IIC
SIO0
Timer 0
Timer 1
Base Timer
ADC
INT0-3
Noise Rejection Filter
PWM
LC863332/28/24/20/16A
No.6695-6/20
Pin Assignment
DIP42S
QIP48E
P07
P06
P05
P04
P03
P02
P01
P00
P73/INT3/T0IN
P72/INT2/T0IN
P71/INT1
P70/INT0
P63/SCLK1
P62/SDA1
P61/SCLK0
P60/SDA0
I
BL
B
G
R
P10/SO0
P11/SI0
P12/SCK0
P13/PWM1
P14/PWM2
P15/PWM3
P16
P17/PWM
VSS
XT1
XT2
VDD
P84/AN4
P85/AN5
P86/AN6
P87/AN7
RES
FILT
P83/AN3
VS
HS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P02
P01
P00
NC
P73/INT3/T0IN
P72/INT2/T0IN
P71/INT1
P70/INT0
P63/SCLK1
P62/SDA1
P61/SCLK0
P60/SDA0
NC
P
14/P
W
M
2
P
13/P
W
M
1
P
12/S
C
K
0
P
11/S
I
0
P
10/S
O
0
NC
P
07
P
06
P
05
P
04
P
03
RE
S
FI
L
T
P
83/A
N
3
NC
VS
HS
R
G
B
B
L
I
NC
P15/PWM3
P16
P17/PWM
VSS
XT1
XT2
VDD
NC
P84/AN4
P85/AN5
P86/AN6
P87/AN7
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
Package Dimension
(unit : mm)
3025B
SANYO : DIP-42S(600mil)
Package Dimension
(unit : mm)
3156
SANYO : QIP-48E
LC863332/28/24/20/16A
No.6695-7/20
Pin Description
Pin Description Table
Terminal I/O
Function
Description
Option
VSS
-
Negative power supply
XT1
I
Input terminal for crystal oscillator
XT2
O
Output terminal for crystal oscillator
VDD
-
Positive power supply
RES
I Reset
terminal
FILT
O
Filter terminal for PLL
VS
I
Vertical synchronization signal input terminal
HS
I
Horizontal synchronization signal input terminal
R
O
Red (R) output terminal of RGB image output
G
O
Green (G) output terminal of RGB image output
B
O
Blue (B) output terminal of RGB image output
I
O
Intensity ( I ) output terminal of RGB image output
BL
O
Fast blanking control signal
Switch TV image signal and OSD image signal
Port 0
P00 - P07
I/O
8-bit input/output port,
Input/output can be specified in nibble unit
Other functions
HOLD release input
Interrupt input
Pull-up resistor
provided/not provided
Output Format
CMOS/Nch-OD
Port 1
8-bit input/output port
Input/output can be specified in a bit
Other functions
P10
P11
P12
P13
P14
P15
P17
SIO0 data output
SIO0 data input/bus input/output
SIO0 clock input/output
PWM1 output
PWM2 output
PWM3 output
Timer1 (PWM) output
P10 - P17
I/O
Output Format
CMOS/Nch-OD
Port 6
4-bit input/output port
Input/output can be specified for each bit
Other functions
P60
P61
P62
P63
IIC0 data I/O
IIC0 clock output
IIC1 data I/O
IIC1 clock output
P60 - P63
I/O
LC863332/28/24/20/16A
No.6695-8/20
Terminal I/O
Function
Description
Option
Port 7
4-bit input/output port
Input or output can be specified for each bit
Other function
P70
P71
P72
P73
INT0 input/HOLD release input/
Nch-Tr. output for wachdog timer
INT1 input/HOLD release input
INT2 input/Timer 0 event input
INT3 input (noise rejection filter
connected)/
Timer 0 event input
Interrupt receiver format, vector addresses
rising
falling
rising/
falling
H level L level vector
INT0 enable enable disable enable enable 03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
P70
P71 - P73
I/O
INT3 enable enable enable disable disable 1BH
Port 8
P83
I
P84-P87 I/O
1-bit input port
4-bit input/output port
Input or output can be specified for each bit
Other function
AD converter input port (5 lines)
NC -
unused
terminal
Leave open
Output form and existance of pull-up resistor for all ports can be specified for each bit.
Programmable pull-up resistor is always connected regardless of port option, CMOS or N-ch open drain output in port 1.
Port status in reset
Terminal
I/O
Pull-up resistor status at selecting pull-up option
Port 0
I
Pull-up resistor OFF, ON after reset release
Port 1
I
Programmable pull-up resistor OFF
LC863332/28/24/20/16A
No.6695-9/20
1. Absolute Maximum Ratings at VSS=0V and Ta=25
C
Ratings
Parameter Symbol Pins
Conditions
VDD[V] min. typ. max.
unit
Supply voltage
VDDMAX VDD
-0.3
+7.0
Input voltage
VI(1)
RES
,
HS
,
VS
,
P83
-0.3
VDD+0.3
Output voltage
VO(1)
R, G, B, I, BL,
FILT
-0.3
VDD+0.3
Input/output voltage VIO
Ports 0, 1, 6, 7,
84 to 87
-0.3
VDD+0.3
V
IOPH(1)
Ports 0, 1, 7, 84 to
87
CMOS output
For each pin.
-4
Peak
output
current
IOPH(2)
R, G, B, I, BL
CMOS output
For each pin.
-5
IOAH(1)
Ports 0, 1
The total of all
pins.
-20
IOAH(2)
Ports 7,
84 to 87
The total of all
pins.
-10
High
level
output
current
Total
output
current
IOAH(3)
R, G, B, I, BL
The total of all
pins.
-15
IOPL(1)
Ports 0, 1, 6,
84 to 87
For each pin.
20
IOPL(2)
Port 7
For each pin.
15
Peak
output
current
IOPL(3)
R, G, B, I, BL
For each pin.
5
IOAL(1)
Ports 0, 1
The total of all
pins.
40
IOAL(2)
Ports 6, 7,
84 to 87
The total of all
pins.
40
Low
level
output
current
Total
output
current
IOAL(3)
R, G, B, I, BL
The total of all
pins.
15
mA
DIP42S 800
Maximum power
dissipation
Pdmax
QIP48E
Ta=-10 to +70
C
400
mW
Operating
temperature
range
Topr
-10
+70
Storage
temperature
range
Tstg
-55
+125
C
LC863332/28/24/20/16A
No.6695-10/20
2. Recommended Operating Range at Ta= -10
C to +70
C, VSS=0V
Ratings
Parameter Symbol
Pins
Conditions
VDD[V] min. typ. max.
unit
VDD(1)
0.844
s
tCYC
0.852
s
4.5
5.5
Operating
supply voltage
range
VDD(2)
VDD
4
s
tCYC
400
s
4.5
5.5
Hold voltage
VHD
VDD
RAMs and the
registers data are
kept in HOLD
mode.
2.0
5.5
VIH(1)
Port 0 (Schumitt)
Output disable
4.5 - 5.5 0.6VDD
VDD
VIH(2)
Ports 1,6 (Schumitt)
Port 7 (Schumitt)
port input/interrupt
HS
,
VS
,
RES
(Schumitt)
Output disable
4.5 - 5.5 0.75VDD
VDD
VIH(3) Port
70
Watchdog timer input
Output disable
4.5 - 5.5 VDD-0.5
VDD
High level
input voltage
VIH(4) Port
8
port input
Output disable
4.5 - 5.5 0.7VDD
VDD
VIL(1)
Port 0 (Schumitt)
Output disable
4.5 - 5.5
VSS
0.2VDD
VIL(2)
Ports 1,6 (Schumitt)
Port 7 (Schumitt)
port input/interrupt
HS
,
VS
,
RES
(Schumitt)
Output disable
4.5 - 5.5
VSS
0.25VDD
VIL(3) Port
70
Watchdog timer input
Output disable
4.5 - 5.5
VSS
0.6VDD
Low level input
voltage
VIL(4) Port
8
port input
Output disable
4.5 - 5.5
VSS
0.3VDD
V
tCYC(1)
All
functions
operating
4.5 - 5.5
0.844
0.848
0.852
tCYC(2)
AD
converter
operating
OSD is not
operating
4.5 - 5.5
0.844
30
Operation
cycle time
tCYC(3)
OSD and AD
converter are not
operating
4.5 - 5.5
0.844
400
s
Oscillation
frequency
range
FmRC
Internal
RC
oscillation
4.5 - 5.5
0.4
0.8
3.0
MHz
LC863332/28/24/20/16A
No.6695-11/20
3. Electrical Characteristics at Ta=-10
C to +70
C, VSS=0V
Ratings
Parameter Symbol
Pins
Conditions
VDD[V] min. typ. max.
unit
IIH(1)
Ports 0, 1, 6, 7, 8
Output disable
Pull-up MOS Tr.
OFF
VIN=VDD
(including the off-
leak current of the
output Tr.)
4.5 - 5.5
1
High level
input current
IIH(2)
RES
HS
,
VS
VIN=VDD
4.5 - 5.5
1
IIL(1)
Ports 0, 1, 6, 7, 8
Output disable
Pull-up MOS
Tr. OFF
VIN=VSS
(including the off-
leak current of the
output Tr.)
4.5 - 5.5
-1
Low level input
current
IIL(2)
RES
HS
,
VS
VIN=VSS
4.5 - 5.5
-1
A
VOH(1)
CMOS output of
ports 0, 1,
71 - 73,
84 - 87
IOH=-1.0mA
4.5 - 5.5
VDD-1
High level
output voltage
VOH(2)
R, G, B, I, BL
IOH=-0.1mA
4.5 - 5.5 VDD-0.5
VOL(1)
Ports 0, 1,
71 - 73,
84 - 87
IOL=10mA
4.5 - 5.5
1.5
VOL(2)
Ports 0, 1,
71 - 73,
84 - 87
IOL=1.6mA
4.5 - 5.5
0.4
VOL(3)
R, G, B, I, BL
Port 6
IOL=3.0mA
4.5 - 5.5
0.4
VOL(4)
Port 6
IOL=6.0mA
4.5 - 5.5
0.6
Low level
output voltage
VOL(5)
Port 70
IOL=1mA
4.5 - 5.5
0.4
V
Pull-up MOS
Tr. resistance
Rpu
Ports 0, 1, 7, 8
VOH=0.9VDD
4.5 - 5.5
13
38
80
k
Bus terminal
short circuit
resistance
(SCL0-SCL1,
SDA0-SDA1)
RBS P60-P62
P61-P63
4.5 - 5.5
130
Hysteresis
voltage
VHIS
Ports 0, 1, 6, 7
RES
HS
,
VS
Output disable
4.5 - 5.5
0.1VDD
V
Pin capacitance CP
All pins
f=1MHz
Every other
terminals are
connected to VSS.
Ta=25
C
4.5 - 5.5
10
pF
LC863332/28/24/20/16A
No.6695-12/20
4. Serial Input/Output Characteristics at Ta= -10
C to +70
C, VSS=0V
Ratings
Parameter Symbol
Pins
Conditions
VDD[V] min. typ.
max.
unit
Cycle
tCKCY(1) 2
Low Level
pulse width
tCKL(1) 1
I
n
pu
t clock
High Level
pulse width
tCKH(1)
SCK0
SCLK0
Refer to figure 4.
4.5 - 5.5
1
Cycle
tCKCY(2) 2
Low Level
pulse width
tCKL(2)
1/2tCKCY
S
e
ri
al clock
Ou
tp
ut
c
l
oc
k
High Level
pulse width
tCKH(2)
SCK0
SCLK0
Use pull-up
resistor (1k
)
when Nch open-
drain output.
Refer to figure 4.
4.5 - 5.5
1/2tCKCY
tCYC
Data set up time
tICK 0.1
Se
r
i
a
l
i
n
p
u
t
Data hold time
tCKI
SI0
Data set-up to
SCK0.
Data hold from
SCK0.
Refer to figure 4.
4.5 - 5.5
0.1
Output delay time
(Using external
clock)
tCKO(1) SO0
4.5
-
5.5
7/12tCYC
+0.2
Seri
al out
pu
t
Output delay time
(Using internal
clock)
tCKO(2) SO0
Data hold from
SCK0.
Use pull-up
resistor (1k
)
when Nch open-
drain output.
Refer to figure 4.
4.5 - 5.5
1/3tCYC
+0.2
s
5. IIC Input/Output Conditions at Ta=-10
C to +70
C, VSS=0V
Standard High
speed
Parameter Symbol
min. max. min. max.
unit
SCL
Frequency
fSCL 0 100 0 400
kHz
BUS free time between stop - start
tBUF
4.7
-
1.3
-
s
HOLD time of start, restart condition
tHD;STA
4.0
-
0.6
-
s
L time of SCL
tLOW
4.7
-
1.3
-
s
H time of SCL
tHIGH
4.0
-
0.6
-
s
Set-up time of restart condition
tSU;STA
4.7
-
0.6
-
s
HOLD time of SDA
tHD;DAT
0
-
0
0.9
s
Set-up time of SDA
tSU;DAT
250
-
100
-
ns
Rising time of SDA, SCL
tR
-
1000
20+0.1Cb
300
ns
Falling time of SDA, SCL
tF
-
300
20+0.1Cb
300
ns
Set-up time of stop condition
tSU;STO
4.0
-
0.6
-
s
Refer to figure 9
(Note)
Cb : Total capacitance of all BUS (unit : pF)
LC863332/28/24/20/16A
No.6695-13/20
6. Pulse Input Conditions at Ta=-10
C to +70
C, VSS=0V
Ratings
Parameter Symbol
Pins
Conditions
VDD[V] min. typ. max.
unit
tPIH(1)
tPIL(1)
INT0, INT1
INT2/T0IN
Interrupt acceptable
Timer0-countable
4.5 - 5.5
1
tPIH(2)
tPIL(2)
INT3/T0IN
(1/1 is selected for
noise rejection
clock.)
Interrupt acceptable
Timer0-countable
4.5 - 5.5
2
tPIH(3)
tPIL(3)
INT3/T0IN
(1/16 is selected for
noise rejection
clock.)
Interrupt acceptable
Timer0-countable
4.5 - 5.5
32
tPIH(4)
tPIL(4)
INT3/T0IN
(1/64 is selected for
noise rejection
clock.)
Interrupt acceptable
Timer0-countable
4.5 - 5.5
128
tCYC
tPIL(5)
RES
Reset acceptable
4.5 - 5.5
200
High/low level
pulse width
tPIH(6)
tPIL(6)
HS
,
VS
Display position
controllable (Note)
The active edge of
HS
and
VS
must
be apart at least
1 tCYC.
Refer to figure 6.
4.5 - 5.5
8
s
Rising/falling
time
tTHL
tTLH
HS
Refer to figure 6.
4.5 - 5.5
500
ns
7. AD Converter Characteristics at Ta=-10
C to + 70
C, VSS=0V
Ratings
Parameter Symbol
Pins
Conditions
VDD[V] min. typ. max.
unit
Resolution N
8 bit
Absolute
precision
ET
(Note
3)
1.5
LSB
ADCR2=0 (Note 4)
16
Conversion
time
tCAD
ADCR2=1 (Note 4)
32
tCYC
Analog input
voltage range
VAIN
VSS
VDD
V
IAINH VAIN=VDD
1
Analog port
input current
IAINL
AN3 - AN7
VAIN=VSS
4.5 5.5
-1
A
(Note 3) Absolute precision does not include quantizing error (1/2LSB).
(Note 4) Conversion time is the time till the complete digital conversion value for analog input value is set to a register after
the instruction to start conversion is sent.
LC863332/28/24/20/16A
No.6695-14/20
8. Sample Current Dissipation Characteristics at Ta=-10
C to +70
C, VSS=0V
The sample current dissipation characteristics is the measurement result of Sanyo provided evaluation board when the
recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. The currents
through the output transistors and the pull-up MOS transistors are ignored.
Ratings
Parameter Symbol
Pins Conditions
VDD[V] min. typ. max.
unit
Current dissipation
during basic
operation
(Note 3)
IDDOP(1) VDD FmX'tal=32.768kHz
X'tal oscillation
System clock :
VCO
VCO for OSD
operating
Internal RC
oscillation stops
4.5 - 5.5
17
30
mA
IDDHALT(1) VDD HALT
mode
FmX'tal=32.768kHz
X'tal oscillation
System clock :
VCO
VCO for OSD stops
Internal RC
oscillation stops
4.5 - 5.5
7
12
mA
IDDHALT(2) VDD HALT
mode
FmX'tal=32.768kHz
X'tal oscillation
VCO for system
stops
VCO for OSD stops
System clock :
Internal RC
4.5 - 5.5
300
1200
Current dissipation
in HALT mode
(Note 3)
IDDHALT(3) VDD HALT
mode
FmX'tal=32.768kHz
X'tal oscillation
VCO for system
stops
VCO for OSD stops
System clock : X'tal
4.5 - 5.5
50
200
A
Current dissipation
in HOLD mode
(Note 3)
IDDHOLD VDD HOLD
mode
All oscillation stops.
4.5 - 5.5
0.05
20
A
(Note 3) The currents through the output transistors and the pull-up MOS transistors are ignored.
LC863332/28/24/20/16A
No.6695-15/20
Recommended Oscillation Circuit and Sample Characteristics
The sample oscillation circuit characteristics in the table below is based on the following conditions:
Recommended circuit parameters are verified by an oscillator manufacturer using a Sanyo provided oscillation evaluation
board.
Sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally.
Recommended oscillation circuit and sample characteristics (Ta = -10 to +70
C)
Recommended circuit parameters
Oscillation
stabilizing time
Notes
Frequency
Manufacturer
Oscillator
C1 C2 Rf Rd
Operating
supply voltage
range
typ. max
32.768kHz Seiko
Epson C-002RX 18pF 18pF Open
390k
4.5 5.5V
1.00s
1.50s
Notes
The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes stable
after the following conditions. (Refer to Figure 2.)
1. The VDD becomes higher than the minimum operating voltage after the power is supplied.
2. The HOLD mode is released.
The sample oscillation circuit characteristics may differ applications. For further assistance, please contact with oscillator
manufacturer with the following notes in your mind.
Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the
oscillation frequency on the production board.
The above oscillation frequency and the operating supply voltage range are based on the operating temperature of -10
C
to +70
C. For the use with the temperature outside of the range herein, or in the applications requiring high reliability
such as car products, please consult with oscillator manufacturer.
When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with Sanyo
sales personnel.
Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low
gain in order to reduce the power dissipation, refer to the following notices.
The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as
possible.
The capacitors' VSS should be allocated close to the microcontroller's GND terminal and be away from other GND.
The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit.
Figure 1 Recommended oscillation circuit.
C1
Rd
C2
X'tal
XT2
XT1
Rf
LC863332/28/24/20/16A
No.6695-16/20
<Reset time and oscillation stabilizing time>
<HOLD release signal and oscillation stabilizing time>
Figure 2 Oscillation stabilizing time
Power supply
RES
Internal RC
resonato
oscillation
XT1,XT2
VCO for system
Operation mode
Reset time
VDD
VDD limit
0V
Unfixed
Instruction execution mode
Reset
tmsVCO
stable
tmsVCO
stable
Valid
Instruction execution mode
HOLD
HOLD release signal
XT1,XT2
VCO for system
Operation mode
Internal RC
resonato
oscillation
LC863332/28/24/20/16A
No.6695-17/20
Figure 3 Reset circuit
< AC timing measurement point >
< Timing >
< Test load >
Figure 4 Serial input / output test condition
(Note) Determine the CRES, RRES value to
generate more than 200
s reset time.
C
RES
VDD
R
RES
RES
0.5VDD
SO0
SB0
SI0
SCK0
50pF
1K
VDD
tCKO
tCKI
tICK
tCKH
tCKL
tCKCY
LC863332/28/24/20/16A
No.6695-18/20
Figure 5 Pulse input timing condition 1
Figure 6 Pulse input timing condition - 2
Figure 7 Recommended Interface circuit
tPIH (1)-(4)
tPIL (1)-(5)
tPIL(6)
tPIL(6)
tTLH
0.75VDD
0.25VDD
more than 1tCYC
HS
VS
LC863332A
HS
10k
C536
HS
LC863332/28/24/20/16A
No.6695-19/20
Figure 8 FILT recommended circuit
(Note) Place FILT parts on board as close to the microcontroller as possible.
S : start condition
tsp : Spike suppression
Standard mode : not exist
P : stop condition
High speed mode : less than 50ns
Sr : restart condition
Figure 9 IIC timing
FILT
100
1M
2.2
F
33000pF
+
-
SDA
SCL
P
S
Sr
P
tBUF
tHD;STA tR
tLOW
tHD;DAT
tHIGH
tF
tSU;DAT tSU;STA
tHD;STA tsp
tSU;STO
LC863332/28/24/20/16A
No.6695-20/20
memo:
PS
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