73004 JO IM No.7935-1/17

Ver.0.92
62102

LC863448B, LC863440B

LC863432B, LC863428B

LC863424B, LC863420B

LC863416B

Overview

The LC863448/40/32/28/24/20/16B are 8-bit single chip microcontrollers with the following on-chip functional blocks :

CPU : Operable at a minimum bus cycle time of 0.424

On-chip ROM capacity

Program ROM : 48K/40K/32K/28K/24K/20K/16K-bytes
CGROM : 16K- bytes

On-chip RAM capacity : 640/512-bytes

OSD RAM : 352 × 9-bits

Closed-Caption TV controller and the on-screen display controller

Closed-Caption data slicer

Four channels × 6-bit AD Converter

Three channels × 7-bit PWM

16-bit timer/counter, 14-bit base timer

IIC-bus compliant serial interface circuit (Multi-master type)

ROM correction function

12-source 8-vectored interrupt system

Integrated system clock generator and display clock generator

Only one X'tal oscillator (32.768kHz) for PLL reference is used for both generators
TV control and the Closed Caption function

All of the above functions are fabricated on a single chip.

Ordering number : ENN7935

CMOS IC
FROM 48K/40K/32K/28K/24K/20K/16K-byte,
RAM 640/512-byte on-chip and 352

9-bit OSD RAM

8-bit 1-chip Microcontroller

LC863448B/40B/32B/28B/24B/20B/16B

No.7935-2/17

Features

Read-Only Memory (ROM)

: 49152 × 8-bits/40960 × 8-bits/32768 × 8-bits/

28672 × 8-bits/24576 × 8-bits/20480 × 8-bits/

16384 × 8-bits for program

16128 × 8-bits for CGROM

Random Access Memory (RAM) : 512 × 8-bits (working area) : LC863448B/40B

384 × 8-bits (working area) : LC863432B/28B/24B/20B/16B

128 × 8-bits (working or ROM correction function)

352 × 9-bits (for CRT display)

OSD functions

Screen display : 36 characters × 16 lines (by software)

RAM

: 352 words (9-bits per word)

Display area : 36 words × 8 lines
Control area : 8 words × 8 lines

Characters

Up to 252 kinds of 16 × 32 dot character fonts (4 characters including 1 test character are not programmable)
Each font can be divided into two parts and used as two fonts (Ex. 16 × 16 dot character font × 2)
At least 111 characters need to be divide between a 16 × 17 dot and 8 × 9 dot character font to display the caption
fonts.

Various character attributes

Character colors

: 16 colors (analog mode : l Vp-p output) /8 colors (digital mode)

Character background colors : 16 colors (analog mode : l Vp-p output) /8 colors (digital mode)
Fringe/shadow colors

: 16 colors (analog mode : l Vp-p output) /8 colors (digital mode)

Full screen colors

: 16 colors (analog mode : l Vp-p output) /8 colors (digital mode)

Rounding
Underline
Italic character (slanting)

Attribute can be changed without spacing

Vertical display start line number can be set for each row independently (Rows can be overlapped)

Horizontal display start position can be set for each row independently

Horizontal pitch (bit 9 to 16)

and vertical pitch (bit 1 to 32) can be set for each row independently

Different display modes can be set for each row independently

Caption

Text mode/OSD mode 1/OSD mode 2 (Quarter size) /Simplified graphic mode

Ten character sizes

Horez. × Vert. = (1 × 1), (1 × 2), (2 × 2), (2 × 4), (0.5 × 0.5)

(1.5 × 1), (1.5 × 2), (3 × 2), (3 × 4), (0.75 × 0.5)

Shuttering and scrolling on each row

Simplified Graphic Display

*1 Note : range depends on display mode : refer to the manual for details.

Data Slicer (closed caption format)

Closed caption data and XDS data extraction

NTSC/PAL, and extracted line can be specified

Bus Cycle Time/Instruction-Cycle Time

Bus cycle time

Instruction cycle time

Clock divider

System clock oscillation

Oscillation frequency

Voltage

0.424

s 0.848

s 1/2

Internal VCO

(Ref : X'tal 32.768kHz)

14.156MHz

4.5V to 5.5V

7.5

s 15.0

1/2

Internal RC

800kHz

4.5V to 5.5V

91.55

s 183.1

1/1

Crystal

32.768kHz

4.5V to 5.5V

183.1

s 366.2

1/2

Crystal

32.768kHz

4.5V to 5.5V

Ports

Input/Output Ports

: 4 ports (23 terminals)

Data direction programmable in nibble units

: 1 port (8 terminals)

(If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.)
Data direction programmable for each bit individually : 3 ports (15 terminals)

LC863448B/40B/32B/28B/24B/20B/16B

No.7935-3/17

AD converter

4 channels × 6-bit AD converters

Serial interfaces

IIC-bus compliant serial interface (Multi-master type)
Consists of a single built-in circuit with two I/O channels. The two data lines and two clock lines can be connected
internally.

PWM output

3 channels × 7-bit PWM

Timer

Timer 0 : 16-bit timer/counter

With 2-bit prescaler + 8-bit programmable prescaler

Mode 0 : Two 8-bit timers with a programmable prescaler
Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with a programmable prescaler
Mode 3 : 16-bit counter

The resolution of timer is 1 tCYC.

Base timer
Generate every 500ms overflow for a clock application
(using 32.768kHz crystal oscillation for the base timer clock)
Generate every 976

s, 3.9ms, 15.6ms, 62.5ms overflow

(using 32.768kHz crystal oscillation for the base timer clock)
Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler
output of Timer 0

Remote control receiver circuit (connected to the P73/INT3/T0IN terminal)

Noise rejection function

Polarity switching

Watchdog timer
External RC circuit is required
Interrupt or system reset is activated when the timer overflows

ROM correction function
Max 128-bytes/2 addresses

Interrupts

12 sources 8 vectored interrupts
1. External Interrupt INT0
2. External Interrupt INT1
3. External Interrupt INT2, Timer/counter T0L (Lower 8-bits)
4. External Interrupt INT3, base timer
5. Timer/counter T0H (Upper 8-bits)
6. Data slicer
7. Vertical synchronous signal interrupt (VS), horizontal line (HS)
8. IIC, Software

Interrupt priority control
Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible.
Low or high priority can be assigned to the interrupts from 3 to 8 listed above.
For the external interrupt INT0 and INT1, low or highest priority can be set.

LC863448B/40B/32B/28B/24B/20B/16B

No.7935-4/17

Sub-routine stack level

A maximum of 128 levels (stack is built in the internal RAM)

Multiplication/division instruction

16-bits × 8-bits (7 instruction cycle times)

16-bits

8-bits (7 instruction cycle times)

3 oscillation circuits

Built-in RC oscillation circuit used for the system clock

Built-in VCO circuit used for the system clock and OSD

X'tal oscillation circuit used for base timer, system clock and PLL reference

Standby function

HALT mode
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped.
This mode can be released by the interrupt request or the system reset.

HOLD mode
The HOLD mode is used to stop the oscillations ; RC (internal), VCO, and X'tal oscillations.
This mode can be released by the following conditions.
- Pull the reset terminal (RES) to low level.
- Feed the selected level to either P70/INT0 or P71/INT1.

Package

MFP36S

DIP36S

Development tools

Flash EEPROM

: LC86F3448A

Evaluation chip

: LC863096

Emulator

: EVA86000 (main) + ECB863200A (evaluation chip board)

+ SUB863400A (sub board)

+ POD36-CABLE (cable)

+ POD36-DIP (for DIP36S)

or POD36-MFP (for MFP36S)

LC863448B/40B/32B/28B/24B/20B/16B

No.7935-8/17

Pin Description

Pin name

I/O

Function

Option

VSS

Negative power supply

XT1

Input terminal for crystal oscillator

XT2

Output terminal for crystal oscillator

VDD

Positive power supply

RES I

Reset

terminal

FILT

Filter terminal for PLL

CVIN

Video signal input terminal

Vertical synchronization signal input terminal

Horizontal synchronization signal input terminal

Red (R) output terminal of RGB image output

Green (G) output terminal of RGB image output

Blue (B) output terminal of RGB image output

Fast blanking control signal
Switch TV image signal and caption/OSD image signal

Port 0

P00 to P07

I/O

· 8-bit input/output port

Input/output can be specified in nibble unit
(If the N-ch open drain output is selected by option, the corresponding port data can be

read in output mode.)

·Other functions

AD converter input port (P04 to P07 : 4 channels)

Pull-up resistor
provided/not provided
Output Format
CMOS/Nch-OD

Port 1

·8-bit input/output port

Input/output can be specified for each bit
(Programmable pull-up resister provided)

·Other functions
P10

P11
P12
P13
P14
P15
P16

IIC0 data I/O
IIC0 clock output
IIC1 data I/O
IIC1 clock output
PWM1 output
PWM2 output
PWM3 output

P10 to P17

I/O

Output Format
CMOS/Nch-OD

Port 3

P30 to P32

I/O

·3-bit input/output port

Input/output can be specified for each bit
(CMOS output/input with programmable pull-up resister)

Port 7

·4-bit input/output port

Input or output can be specified for each bit

P70 : I/O with programmable pull-up resister
P71 to P73 : CMOS output/input with programmable pull-up resister

·Other function
P70

P71
P72
P73

INT0 input/HOLD release input/
Nch-Tr. Output for watchdog timer
INT1 input/HOLD release input
INT2 input/Timer 0 event input
INT3 input (noise rejection filter connected)
/Timer 0 event input

Interrupt receiver format, vector addresses

rising falling

rising/
falling

H level

L level

vector

INT0 enable enable disable enable enable 03H

INT1 enable enable disable enable enable 0BH

INT2 enable enable enable disable

disable 13H

P70
P71 to P73

I/O

INT3 enable enable enable disable

disable 1BH

Note : A capacitor of at least 10

F must be inserted between VDD and VSS when using this IC.

Continued on next page.

LC863448B/40B/32B/28B/24B/20B/16B

No.7935-9/17

Continued from preceding page.

Output form and existence of pull-up resistor for all ports can be specified for each bit.

Programmable pull-up resistor is always connected regardless of port option, CMOS or N-ch open drain output in port 1.

Port status in reset

Terminal

I/O

Pull-up resistor status at selecting CMOS output option

Port 0

Pull-up resistor OFF, ON after reset release

Port 1

Programmable pull-up resistor OFF

Absolute Maximum Ratings / Ta = 25°C, VSS = 0V

Limits

Parameter Symbol

Pins

Conditions

VDD[V]

min typ max unit

Supply voltage

VDD max

VDD

-0.3

+7.0

Input voltage

VI(1)

RES, HS, VS, CVIN

-0.3

VDD+0.3

Output voltage

VO(1)

R, G, B, BL, FILT

-0.3

VDD+0.3

Input/output voltage

VIO

Ports 0, 1, 3, 7

-0.3

VDD+0.3

IOPH(1)

Ports 0, 1, 3, 7

· CMOS output
· For each pin.

-4

Peak
output
current

IOPH(2)

R, G, B, BL

· CMOS output
· For each pin.

-5

IOAH(1)

Ports 0, 1

The total of all pins.

-20

IOAH(2)

Ports 3, 7

The total of all pins.

-10

High
level
output
current

Total
output
current

IOAH(3)

R, G, B, BL

The total of all pins.

-12

IOPL(1)

Ports 0, 1, 3

For each pin.

IOPL(2)

Port 7

For each pin.

Peak
output
current

IOPL(3)

R, G, B, BL

For each pin.

IOAL(1)

Ports 0, 1

The total of all pins.

IOAL(2)

Ports 3, 7

The total of all pins.

Low
level
output
current

Total
output
current

IOAL(3)

R, G, B, BL

The total of all pins.

MFP36S

340

Maximum power
dissipation

Pd max

DIP36S

Ta = -10 to +70°C

500

Operating
temperature range

Topr

-10

+70

Storage
temperature range

Tstg

-55

+125

°C

Recommended Operating Range / Ta = -10°C to +70°C, VSS = 0V

Limits

Parameter Symbol

Pins

Conditions

VDD [V]

min

typ

max

unit

VDD(1) 0.844

tCYC

0.852

4.5

5.5

Operating supply
voltage range

VDD(2)

VDD

tCYC

400

4.5

5.5

Hold voltage

VHD

VDD

RAMs and the registers
data are kept in HOLD
mode.

2.0

5.5

VIH(1)

Port 0

Output disable

4.5 to 5.5

0.6VDD

VDD

VIH(2)

· Ports 1, 3 (Schumitt)
· Port 7 (Schumitt)
port input/interrupt
· HS, VS, RES
(Schumitt)

Output disable

4.5 to 5.5

0.75VDD

VDD

High level input
voltage

VIH(3) Port

Watchdog timer input

Output disable

4.5 to 5.5

VDD-0.5

VDD

Continued on next page.

LC863448B/40B/32B/28B/24B/20B/16B

No.7935-10/17

Continued from preceding page.

Limits

Parameter Symbol

Pins

Conditions

VDD [V]

min

typ

max

unit

VIL(1)

Port 0

Output disable

4.5 to 5.5

VSS

0.2VDD

VIL(2)

· Ports 1, 3 (Schumitt)
· Port 7 (Schumitt)
port input/interrupt
· HS, VS, RES
(Schumitt)

Output disable

4.5 to 5.5

VSS

0.25VDD

Low level input
voltage

VIL(3) Port

Watchdog timer input

Output disable

4.5 to 5.5

VSS

0.6VDD

CVIN VCVIN

CVIN

5.0 0.7Vp-p

1Vp-p

1.4Vp-p

Vp-p*

tCYC(1)

· All functions operating

4.5 to 5.5

0.844

0.848

0.852

Operation cycle time

tCYC(2)

· OSD and Data slicer are

not operating

4.5 to 5.5

0.844

400

Oscillation
frequency range

FmRC

Internal RC oscillation

4.5 to 5.5

0.4

0.8

3.0

MHz

* Vp-p : Peak-to-peak voltage

Electrical Characteristics / Ta = -10°C to +70°C, VSS = 0V

Limits

Parameter Symbol

Pins

Conditions

VDD[V] min typ max unit

IIH(1)

Ports 0, 1, 3, 7

· Output disable
· Pull-up MOS Tr. OFF
· VIN = VDD

(Including the off-leak current of

the output Tr.)

4.5 to 5.5

High level input
current

IIH(2) ·

RES

· HS, VS

· VIN = VDD

4.5 to 5.5

IIL(1)

Ports 0, 1, 3, 7

· Output disable
· Pull-up MOS Tr. OFF
· VIN = VSS

(Including the off- leak current of

the output Tr.)

4.5 to 5.5

-1

Low level input
current

IIL(2) ·

RES

· HS, VS

VIN = VSS

4.5 to 5.5

-1

VOH(1)

· CMOS output of

ports 0, 1, 3,
71 to 73

IOH = -1.0mA

4.5 to 5.5

VDD-1

High level
output voltage

VOH(2)

R, G, B, BL

IOH = -0.1mA
R. G. B : digital mode

4.5 to 5.5

VDD-0.5

VOL(1)

Ports 0, 1, 3, 71 to 73

IOL = 10mA

4.5 to 5.5

1.5

VOL(2)

Ports 0, 3, 71 to 73

IOL = 1.6mA

4.5 to 5.5

0.4

VOL(3)

· R, G, B, BL
· Port 1

IOL = 3.0mA
R. G. B : digital mode

4.5 to 5.5

0.4

Low level
output voltage

VOL(4) Port

IOL = 1mA

4.5 to 5.5

0.4

Pull-up MOS
Tr. resistance

Rpu

· Ports 0, 1, 3, 7

VOH = 0.9VDD

4.5 to 5.5

Bus terminal
short circuit
resistance

(SCL0 to SCL1,

SDA0 to SDA1)

RBS

· P10 to P12
· P11 to P13

4.5 to 5.5

130

300

Hysteresis
voltage

VHIS

· Ports 1, 3, 7
· RES
· HS, VS

Output disable

4.5 to 5.5

0.1VDD

Input clump
voltage

VCLMP CVIN

5.0 2.3

2.5

2.7

Pin
capacitance

All pins

· f = 1MHz
· Every other terminals are

connected to VSS.

· Ta = 25°C

4.5 to 5.5

LC863448B/40B/32B/28B/24B/20B/16B

No.7935-11/17

IIC Input/Output Conditions / Ta = -10°C to +70°C, VSS = 0V

Standard High

speed

Parameter Symbol

min max min max

unit

SCL Frequency

fSCL 0 100 0 400

kHz

BUS free time between stop to start

tBUF 4.7 - 1.3 -

HOLD time of start, restart condition

tHD

;

STA

4.0 - 0.6 -

L time of SCL

tLOW 4.7 - 1.3 -

H time of SCL

tHIGH 4.0 - 0.6 -

Set-up time of restart condition

tSU

;

STA

4.7 - 0.6 -

HOLD time of SDA

tHD ; DAT

0.9

Set-up time of SDA

tSU

;

DAT

250 - 100 -

Rising time of SDA, SCL

1000

20 + 0.1Cb

300

Falling time of SDA, SCL

300

20 + 0.1Cb

300

Set-up time of stop condition

tSU

;

STO

4.0 - 0.6 -

Refer to figure 8
Note : Cb : Total capacitance of all BUS (unit : pF)

Pulse Input Conditions / Ta = -10°C to +70°C, VSS = 0V

Limits

Parameter Symbol

Pins

Conditions

VDD[V] min typ max unit

tPIH(1)
tPIL(1)

· INT0, INT1
· INT2/T0IN

· Interrupt acceptable
· Timer 0-countable

4.5 to 5.5

tPIH(2)
tPIL(2)

INT3/T0IN

(1 tCYC is selected for

noise rejection clock.)

· Interrupt acceptable
· Timer 0-countable

4.5 to 5.5

tPIH(3)
tPIL(3)

INT3/T0IN

(16 tCYC is selected for

noise rejection clock.)

· Interrupt acceptable
· Timer 0-countable

4.5 to 5.5

tPIH(4)
tPIL(4)

INT3/T0IN

(64 tCYC is selected for

noise rejection clock.)

· Interrupt acceptable
· Timer 0-countable

4.5 to 5.5

128

tCYC

tPIL(5)

RES Reset

acceptable

4.5 to 5.5

200

High/low level pulse
width

tPIH(6)
tPIL(6)

HS, VS

· Display position

controllable (Note)

· The active edge of HS

and VS must be apart
at least 1 tCYC.

· Refer to figure 4.

4.5 to 5.5

Rising/falling time

tTHL
tTLH

Refer to figure 4.

4.5 to 5.5

500

AD Converter Characteristics / Ta = -10°C to +70°C, VSS = 0V

Limits

Parameter Symbol Pins

Conditions

VDD [V]

min

typ

max

unit

Resolution N

bit

Absolute precision

(Note)

±1

LSB

Conversion time

tCAD

Vref selection
to conversion
finish

1-bit conversion time = 2 × tCYC

1.69

Analog input
voltage range

VAIN

VSS

VDD

IAINH

VAIN = VDD

Analog port
input current

IAINL

AN4 to AN7

VAIN = VSS

4.5 to 5.5

-1

Note : Absolute precision does not include quantizing error (1/2LSB).

LC863448B/40B/32B/28B/24B/20B/16B

No.7935-12/17

Analog Mode RGB Characteristics / Ta = -10°C to +70°C, VSS = 0V

Limits

Parameter Symbol

Pins

Conditions

VDD [V]

min

typ

max

unit

Low level output

0.45

0.5 0.55

Intensity output

0.90

1.0 1.10

Analog output
voltage

Analog output mode

Hi level output

1.35

1.5 1.65

Time setting

R. G. B

70% 10pf load

5.0

Sample Current Dissipation Characteristics / Ta = -10°C to +70°C, VSS = 0V

The sample current dissipation characteristics are the measurement result of SANYO provided evaluation board
when the recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally.
The currents through the output transistors and the pull-up MOS transistors are ignored.

Limits

Parameter Symbol

Pins

Conditions

VDD [V]

min

typ

max

unit

IDDOP(1) VDD

· FmX'tal = 32.768kHz

X'tal oscillation

· System clock : VCO
· VCO for OSD operating
· OSD is Digital mode
· Internal RC oscillation stops

4.5 to 5.5

IDDOP(2) VDD

· FmX'tal = 32.768kHz

X'tal oscillation

· System clock : VCO
· VCO for OSD operating
· OSD is Analog mode
· Internal RC oscillation stops

4.5 to 5.5

Current dissipation
during basic
operation

(Note 3)

IDDOP(3) VDD

· FmX'tal = 32.768kHz

X'tal oscillation

· System clock : X'tal

(Instruction cycle time : 366.2

· VCO for system VCO for OSD,

internal RC oscillation stop

· Data slicer, AD converters stop

4.5 to 5.5

300

IDDHALT(1) VDD

· HALT mode
· FmX'tal = 32.768kHz

X'tal oscillation

· System clock : VCO
· VCO for OSD stops
· Internal RC oscillation stops

4.5 to 5.5

IDDHALT(2) VDD

· HALT mode
· FmX'tal = 32.768kHz

X'tal oscillation

· VCO for system stops
· VCO for OSD stops
· System clock : Internal RC

4.5 to 5.5

300

1000

Current dissipation
in HALT mode

(Note 3)

IDDHALT(3) VDD

· HALT mode
· FmX'tal = 32.768kHz

X'tal oscillation

· VCO for system stops
· VCO for OSD stops
· System clock : X'tal

(Instruction cycle time : 366.2

4.5 to 5.5

200

Current dissipation
in HOLD mode

(Note 3)

IDDHOLD VDD

· HOLD mode
· All oscillation stops. 4.5

5.5

0.05

Note 3 : The currents through the output transistors and the pull-up MOS transistors are ignored.

LC863448B/40B/32B/28B/24B/20B/16B

No.7935-13/17

Recommended Oscillation Circuit and Sample Characteristics

The sample oscillation circuit characteristics in the table below is based on the following conditions :

Recommended circuit parameters are verified by an oscillator manufacturer using a SANYO provided oscillation

evaluation board.

Sample characteristics are the result of the evaluation with the recommended circuit parameters connected

externally.

Recommended oscillation circuit and sample characteristics (Ta = -10 to +70°C)

Recommended circuit parameters

Oscillation

stabilizing time

Frequency Manufacturer Oscillator

C1 C2 Rf Rd

Operating supply

voltage range

typ max

Notes

32.768kHz Seiko

Epson C-002RX 18pF 18pF OPEN 390k

4.5 to 5.5V

1.00S

1.50S

Notes : The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes

stable after the following conditions. (Refer to Figure 2.)

1. The VDD becomes higher than the minimum operating voltage after the power is supplied.

2. The HOLD mode is released.

The sample oscillation circuit characteristics may differ applications. For further assistance, please contact with
oscillator manufacturer with the following notes in your mind.

Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the

oscillation frequency on the production board.

The above oscillation frequency and the operating supply voltage range are based on the operating temperature of

-10°C to +70°C. For the use with the temperature outside of the range herein, or in the applications requiring high
reliability such as car products, please consult with oscillator manufacturer.

When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with

SANYO sales personnel.

Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed
with low gain in order to reduce the power dissipation, refer to the following notices.

The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as

possible.

The capacitors' VSS should be allocated close to the microcontroller's GND terminal and be away from other GND.

The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit.

Figure 1 Recommended oscillation circuit

X'tal

XT2

XT1

LC863448B/40B/32B/28B/24B/20B/16B

No.7935-16/17

Output impedance of C-Video before Noise filter should be less then 100

Figure 6 CVIN recommended circuit

Figure 7 FILT recommended circuit

Note : Place FILT parts on board as close to the microcontroller as possible.

S : start condition

tsp : Spike suppression

Standard mode : not exist

P : stop condition

High speed mode : less than 50ns

Sr : restart condition

Figure 8 IIC timing

200

C-Video

1000pF

CVIN

Noise filter

Coupling capacitor

FILT

100

2.2

33000pF

SDA

SCL

tBUF

tHD ; STA tR

tLOW

tHD ; DAT

tHIGH

tSU ; DAT

tSU ; STA

tHD ; STA

tsp

tSU ; STO

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LC863428B

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LC863428B