91400 RM (IM) SK No.6700-1/21
Ver.1.05
71896
Preliminary
Overview
- CPU : Operable at a minimum bus cycle time of 0.5
s (microsecond)
- On-chip ROM maximum capacity : 48K bytes
- On-chip RAM capacity : 1152 bytes
(LC866548A/40A/32A)
: 896 bytes (LC866528A/24A)
- VFD automatic display controller/driver
- 16-bit timer/counter (or two 8-bit timers)
- 16-bit timer/ PWM (or two 8-bit timers)
- 8-channels
8 bit AD Converter
- Two 8-bit synchronous serial-interface circuits (1-channel
16 bit, 1-channel
8 bit)
- 14-source 10-vectored interrupt system
All of the above functions are fabricated on a single chip.
Features
(1) Read Only Memory (ROM)
: LC866548A
49152
8 bits
:
LC866540A
40960
8 bits
:
LC866532A
32768
8 bits
:
LC866528A
28672
8 bits
:
LC866524A
24576
8 bits
8-Bit Single Chip Microcontroller
LC866548/40/32/28/24A
Ordering number : ENN*6700
CMOS IC
LC866548/40/32/28/24A
No.6700-2/21
(2) Random Access Memory (RAM)
: LC866548A/40A/32A
1152
8 bits
LC866528A/24A
896
8 bits
(3) Bus Cycle Time / Instruction Cycle Time
The bus cycle time indicates the speed to read ROM.
Bus cycle time
Cycle time
Clock divider
System clock oscillation
Oscillation Frequency
Voltage
0.5
s 1
s
1/1
Ceramic resonator oscillation
6MHz
4.5 - 6.0V
2
s 4
s
1/2
Ceramic resonator oscillation
3MHz
4.5 - 6.0V
7.5
s 15
s
1/2
RC resonator oscillation
800MHz
4.5 - 6.0V
183
s 366
s
1/2
Crystal oscillation
32.768kHZ
4.5 - 6.0V
Note : External resisters (Rf, Rd) are required when X'tal oscillation is used.
(4) Ports
- Input/output ports
: 3 ports (16 terminals : port 1, 7, 8)
Input/output port programmable in a bit
- 15V withstand Input/output ports
: 2 ports (16 terminals)
Input/output port programmable nibble unit
: 1 port (8 terminals : port 0)
(When the N-channel open drain output is selected, the data in a bit can be inputted.)
Input/output port programmable in a bit
: 1 port (8 terminals : port 3)
- Input port
: 2 ports (6 terminals : port 7, 8)
- VFD output port
: 52 terminals
Large current output for digit
: 16 terminals
Pull-down resistor option available
- Other function
Input/output port
: 2 ports
(12 terminals : port F, G)
Input port
: 3 ports
(24 terminals : port C, D, E)
(5) VFD automatic display controller
- Segment/digit output pattern programmable
Any segment/digit combination available
VFD parallel-drive available
- 16-step dimmer function available
(6) AD converter
- 8-channels
8-bit AD converter
(7) Serial interface
- 1-channel
16-bit serial interface circuits
- 1-channel
8-bit serial interface circuits
- LSB first/MSB first function available
- Internal 8-bit baud-rate generator in common with two serial interface circuits
- SIO automatic transmission available (2-32 byte data can be transmitted with program automatically and
continuously.)
LC866548/40/32/28/24A
No.6700-3/21
(8) Timers
- Timer 0 : 16-bit timer/counter with 2-bit prescaler + 8-bit programmable prescaler
Mode 0 : Two 8-bit timers with programmable prescaler
Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with a programmable prescaler
Mode 3 : 16-bit counter
The resolution of Timer is t
CYC
. (t
CYC : cycle time)
- Timer 1 : 16-bit timer/PWM with
Mode 0 : Two 8-bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : Variable-bit PWM (9-16 bits)
In Mode 0 and Mode 1, the resolution of Timer and PWM is t
CYC
.
In Mode 2 and Mode 3, the resolution of Timer and PWM selectable : t
CYC
or 1/2t
CY
C by program
- Base timer
Every 500ms overflow system for a clock application (using 32.768kHz crystal oscillation for Base timer
clock)
Every 976
s, 3.9ms, 15.6ms, 62.5ms overflow system (using 32.768kHz crystal oscillation for Base timer
clock)
The Base timer clock selectable ; 32.768kHz crystal oscillation, System clock, and programmable prescaler
output of Timer 0
(9) Buzzer output
- The Buzzer sound frequency selectable ; 4kHz, 2kHz (using 32.768kHz crystal oscillation for Base timer clock)
(10) Remote control receiver circuit (connected to the P73/INT3/T0IN terminal)
- Noise rejection function (the time constant of noise rejection filter : 1tCYC/16tCYC/64tCYC)
(tCYC : instruction cycle time)
- Polarity switching
(11) Watchdog timer
- The watchdog timer is taken on RC outside
- Watchdog timer operation selectable : interrupt system, system reset
(12) Interrupt system
- 14-source 10-vectored interrupts :
1. External Interrupt INT0 (include watchdog timer)
2. External Interrupt INT1
3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits)
4. External Interrupt INT3, base timer
5. Timer/counter T0H (Upper 8 bits)
6. Timer T1H / T1L
7. Serial interface SIO0
8. Serial interface SIO1
9. AD converter
10. VFD automatic display controller, Port 0
- Built-in Interrupt priority control register
Microcontroller allows 3 levels of interrupt ; low level, high level, and highest level of multiplex interrupt. It can
specify a low level or a high level interrupt priority from INT2/T0L through port 0 (i. e. the above interrupt
number from three through ten). It can also specify a low level or the highest level interrupt priority to INT0 and
INT1.
(13) Subroutine stack levels
- 128 levels (Max.) : Stack area included in RAM area
LC866548/40/32/28/24A
No.6700-4/21
(14) Multiplication and division
- 16 bit
8 bit (7 instruction cycle times)
- 16 bit 8 bit (7 instruction cycle times)
(15) Three oscillation circuits
- On-chip RC oscillation circuit used for the system clock
- On-chip CF oscillation circuit used for the system clock
- On-chip Crystal oscillation circuit used for the system clock and for time-base clock
Note : External resisters (Rf, Rd) are required
(16) Standby function
- HALT mode function
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped.
This operation mode can be released by the interrupt request signals or the initial system reset request signal.
- HOLD mode function
The HOLD mode is used to stop all the oscillations ;
RC (internal), CF and Crystal oscillations. This mode can be released by the following operations.
Reset terminal (
RES ) set to low level.
Input a assigned level to P70/INT0/T0IN or P71/INT1/T0IN terminal.
Input a Port0 interrupt condition.
(17) Factory shipment
QFP100E delivery form
(18) Development Tools
- Evaluation chip
: LC866094
- EPROM version
: LC86E6548
- One time version
: LC86P6548
- Emulator
: EVA86000 + ECB866500 (Evaluation chip board) + POD866500 (Pod)
Notes for use
Follow the under table.
Frequency range of the system clock
Voltage range
Clock Divider
Note
15kHz to 3MHz
1/1
Can not use 1/2 divider
30kHz to 6MHz
1/1, 1/2
Internal RC oscillation
4.5V to 6.0V
1/1, 1/2
LC866548/40/32/28/24A
No.6700-5/21
Pin Assignment QIP100E
Package Dimension
(unit : mm)
3151
SANYO : QIP-100E
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
80
79
78 77
76 75
74 73
72
71 70
69 68
67 66
65 64
63
62 61
60 59
58 57
56 55
54
53 52
51
1
2
3 4
5 6
7 8
9
10 11
12 13
14 15
16 17
18
19 20
21 22
23 24
25 26
27
28 29
30
S48/PG0
S49/PG1
S50/PG2
S51/PG3
P00
P01
P02
P03
VSS2
VDD2
P04
P05
P06
P07
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
S19/PC3
S18/PC2
S17/PC1
S16/PC0
VDD3
S15/T15
S14/T14
S13/T13
S12/T12
S11/T11
S10/T10
S9/T9
S8/T8
S7/T7
S6/T6
S5/T5
S4/T4
S3/T3
S2/T2
S1/T1
S
47/P
F
7
S
46/P
F
6
S
45/P
F
5
S
44/P
F
4
S
43/P
F
3
S
42/P
F
2
S
41/P
F
1
S
40/P
F
0
VDD4
S
39/P
E7
S
38/P
E6
S
37/P
E5
S
36/P
E4
S
35/P
E3
S
34/P
E2
S
33/P
E1
S
32/P
E0
S
31/P
D
7
S
30/P
D
6
S
29/P
D
5
S
28/P
D
4
S
27/P
D
3
S
26/P
D
2
S
25/P
D
1
S
24/P
D
0
S
23/P
C
7
S
22/P
C
6
S
21/P
C
5
S
20/P
C
4
VP
P
16/B
U
Z
Z
P
17/P
W
M
0
P3
0
P3
1
P3
2
P3
3
P3
4
P3
5
P3
6
P3
7
P
70/I
N
T
0
RE
S
X
T
1/P
74
X
T
2/P
75
V
SS1
CF
1
CF
2
VDD1
P
80/A
N
0
P
81/A
N
1
P
82/A
N
2
P
83/A
N
3
P
84/A
N
4
P
85/A
N
5
P
86/A
N
6
P
87/A
N
7
P
71/I
N
T
1
P
72/I
N
T
2/T
0
I
N
P
72/I
N
T
3/T
0I
N
S
0/T
0
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