D2700 RM (IM) SK No.6838-1/20
Ver.1.02
72396
Preliminary
Overview
The LC86P7248 is a CMOS 8-bit single chip microcontroller with one-time PROM for the LC867200 series. This
microcontroller has the function and the pin description of the LC867200 series mask ROM version, and 48K-byte
EPROM.
QIP package are available for shipping as well as LC867200 series. It is suitable to set up first release, prototyping,
developing and testing of set.
Features
(1) Option switching by PROM data
The option function of the LC867200 series can be specified by the PROM data.
LC86P7248 can be checked the functions of the trial pieces using the mass production board.
(2) Internal one-time PROM capacity : 49408 bytes
(3) Internal RAM capacity
: 1152 bytes
Used PROM or RAM capacity are equal ROM or RAM capacity of mask ROM version which applies LC86P7248.
Mask ROM version
EPROM capacity
RAM capacity
LC867248 49152
bytes 1152
bytes
LC867240 40960
bytes 1152
bytes
LC867232 32768
bytes 1152
bytes
LC867224 24576
bytes 1152
bytes
Programming service
We offers various services at nominal charges. These include ROM writing, ROM reading and package stamping and
screening. Contact local our representative for further information.
8-Bit Single-Chip Microcontroller
with the One-Time Programmable PROM Built in
LC86P7248
Ordering number : ENN*6838
CMOS IC
LC86P7248
No.6838-2/20
(4) Operating supply voltage
: 4.5V to 6.0V
(5) Instruction cycle time
: 1
s to 366
s
(6) Operating temperature
: -30
C to +70
C
(7) The pin compatible with the LC867200 series mask ROM devices
(8) Applicable mask ROM version
: LC867248/LC867240/LC867232/LC867224
(9) Factory shipment
: QIP100E
Notice for use
LC86P7248 is provided for the first release and small shipping of the LC867200 series.
At using, take notice of the followings.
(1) A point of difference LC86P7248 and LC867200 series
Item LC86P7248 LC867248/40/32/24
Operation after reset
releasing
The option is specified until 3ms after
going to a `H' level to the reset
terminal by degrees. The program is
executed from 00H of the program
counter.
The program is executed from 00H of
the program counter immediately after
going to a `H' level to the reset
terminal.
Operating supply
voltage range (VDD)
4.5V to 6.0V
2.5V to 6.0V
Power dissipation
Refer to `electrical characteristics' on the semiconductor news.
LC86P7248 uses 256 bytes that is addressed on 0FF00H to FFFFH in the program memory as the option configuration data
area. This option configuration can execute all options which LC867200 series have.
A kind of the option of the LC86P7248
A kind of option
Pins, Circuits
Contents of the option
1. N-channel open drain output
2. CMOS output
*1
Port 0
1. Pull-up MOS Tr.
2. No Pull-up MOS Tr.
*2
Port 1
*1
1. Input : Programmable pull-up MOS Tr.
Output : N-channel open drain
2. Input : Programmable pull-up MOS Tr.
Output : CMOS
Input/output form of
input/output ports
Port 3
*1
1. Input : No Programmable pull-up MOS Tr.
Output : N-channel open drain
2. Input : Programmable pull-up MOS Tr.
Output : CMOS
Pull-up MOS Tr. of
input port
Ports 70, 71, 72, 73
*1
1. No Pull-up MOS Tr.
2. Pull-up MOS Tr.
*1) Specified in a bit.
*2) Specified in nibble unit. Pull-up MOS Tr. is not provided in N-channel open drain output port.
LC86P7248
No.6838-3/20
(1) Option
The option data is created by the option specified program "SU86K.EXE". The created option data is linked to the
program area by linkage loader "L86K.EXE".
(2) ROM space
LC86P7248 and LC867200 series use 256 bytes that is addressed on 0FF00H to 0FFFFH in the program memory as the
option specified data area. These program memory capacity are 49152 bytes that is addressed on 0000H to 0BFFFH.
(3) Ordering information
1. When ordering the identical mask ROM and PROM devices simultaneously.
Provide an EPROM containing the target memory contents together with the separate order forms for each of the mask
ROM and PROM versions.
2. When ordering a PROM device.
Provide an EPROM containing the target memory contents together with an order form.
0FFFFH
0FF00H
0EFFFH
0DFFFH
0CFFFH
0BFFFH
0AFFFH
9FFFH
8FFFH
7FFFH
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
0FFFH
0000H
Option data
area 256 bytes
Program area
48K bytes
Option
data area
Program area
40K bytes
LC867248 LC867240
Option
data area
Program area
32K bytes
LC867232
Option
data area
LC867224
Program area
24K bytes
LC86P7248
No.6838-4/20
How to use
(1) Specification of option
Programming data for PROM of the LC86P7248 is required.
Debugged evaluation file (EVA file) must be converted to an INTEL-HEX formatted file (HEX file) with file converter
program, EVA2HEX.EXE. The HEX file is used as the programming data for the LC86P7248.
(2) How to program for the PROM
The LC86P7248 can be programmed by PROM programmer with attachment ; W86EP7248Q
Recommended EPROM programmer
Productor EPROM
programmer
Advantest
R4945, R4944, R4943
Andou AF-9704
AVAL PKW-1100,
PKW-3000
Minato electronics
MODEL1890A
"27512 (Vpp=12.5V) Intel high speed programming" mode available. The address must be set to "0 to 0FFFFH" and a
jumper (DASEC) must be set to `OFF' at programming.
(3) How to use the data security function
"Data security" is the disabled function to read the data of the PROM.
The following is the process in order to execute the data security.
1. Set `ON' the jumper of attachment.
2. Program again. Then PROM programmer displays the error. The error means normally activity of the data security.
It is not a trouble of the PROM programmer or the LSI.
Notes
Data security is not executed when the data of all address have `FFH' at the sequence 2 above.
The programming by a sequential operation "BLANK=>PROGRAM=>VERIFY" cannot be executed data security at the
sequence 2 above.
Set to `OFF' the jumper after executing the data security.
W86EP7248Q
Data security
Not data security
LC86P7248
No.6838-5/20
Pin Assignment
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V3/PL6
S47/PF7
S46/PF6
S45/PF5
S44/PF4
S43/PF3
S42/PF2
S41/PF1
S40/PF0
S39/PE7
S38/PE6
S37/PE5
S36/PE4
S35/PE3
S34/PE2
S33/PE1
S32/PE0
S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
VSS2
VDD2
S25/PD1
S24/PD0
S23/PC7
S22/PC6
S21/PC5
P06
P07
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/BUZ
P17/PWM0
P70/INT0
RES
XT1/P74
XT2/P75
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
P71/INT1
P72/INT2/T0IN
P73/INT3/T0IN
S0/PA0
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S15/PB7
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1/PA1
V2/PL5
V1/PL4
COM0/PL0
COM1/PL1
COM2/PL2
COM3/PL3
P30
P31
VSS3
VDD3
P32
P33
P34
P35
P00
P01
P02
P03
P04
P05
Notes
The QIP packages should be heat-soaked for 12 hours at 125
C immediately prior to mounting (This baking is called
pre-baking).
After pre-baking, a controlled environment must be maintained until soldering. The environment must be held at a
temperature of 30
C or less and a humidity level of 70% or less. Please solder within 24 hours.
Package Dimension
(unit : mm)
3151
SANYO : QIP-100E
LC86P7248
No.6838-6/20
System Block Diagram
IR
PLA
EPROM
Control
A15-A0
D7-D0
TA
CE
OE
DASEC
EPROM (48KB)
PC
ACC
B Register
C Register
ALU
PSW
RAR
RAM
Stack Pointer
Port 0
Watchdog Timer
Stand-by Control
Cl
ock
G
e
n
e
rat
o
r
CF
RC
X'tal
Base Timer
Bus Interface
Port 1
Port 7
Port 8
Port 3
ADC
INT0 to 3 Noise
Rejection Filter
SIO0
SIO1
Timer 0
Timer 1
Real Time Service
RAM 128 bytes
LCD Display
Controller
SO0 to S7 (PA)
S8 to S13 (PB)
COM0 to -COM3(PL)
S16 to S23 (PC)
S24 to S31 (PD)
S32 to S39 (PE)
S40 to S47 (PF)
Interrupt Control
LC86P7248
No.6838-7/20
Pin Description
Pin name
I/O
Function description
Option
PROM mode
VSS1, 2, 3
*1
- Power
pin
()
-
-
VDD1, 2, 3
*1
- Power
pin
(+)
-
-
PORT0
P00 to P07
I/O 8-bit input/output port
Input/output in nibble units
Input for port 0 interrupt
Input for HOLD release
Pull-up resistor :
Provided/Not
provided
(specified in nibble units)
Output form (P00 P07) :
CMOS/N-channel open drain
(specified in a bit)
-
PORT1
P10 to P17
I/O 8-bit input/output port
Input/output can be specified in bit unit
Other pin functions
P10 : SIO0 data output
P11 : SIO0 data input/bus input/output
P12 : SIO0 clock input/output
P13 : SIO1 data output
P14 : SIO1 data input/bus input/output
P15 : SIO1 clock input/output
P16 : Buzzer output
P17 : Timer1 output (PWM output)
Output form :
CMOS/N-channel open drain
(specified in a bit)
Data line
D0 to D7
PORT3
P30 to P35
I/O 6-bit input/output port
Input/output can be specified in bit unit
Output form :
CMOS/N-channel open drain
(specified in a bit)
-
6-bit input port
Other pin functions
P70 : INT0 input/HOLD release input/
N-ch Tr. output for watchdog timer
P71 : INT1 input/HOLD release input
P72 : INT2 input/timer 0 event input
P73 : INT3 input with noise filter/timer 0
event
input
Interrupt received form, vector address
Pull-up resistor :
Provided/Not
provided
(specified in a bit)
(P70, P71, P72, P73)
* P74 , P75 don't have the pull-up
resistor option.
rising
falling
rising
&
falling
high
level
low
level
vector
INT0 enable enable disable enable enable 03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
INT3 enable enable enable disable disable 1BH
PORT7
P70
P71 to P73
P74 , P75
I/O
I
I
P74 : XT1 terminal for crystal oscillation
P75 : XT2 terminal for crystal oscillation
Power for
programming
PROM control
signals
DASEC (*2)
OE
(*3)
CE
(*4)
Port8
P80 to P87
I
8-bit input port
Other function
AD input port (8 port pins)
- -
LC86P7248
No.6838-8/20
Pin name
I/O
Function description
Option
PROM mode
Port A
(S0/PA0 to
S7/PA7)
I/O
Segment output terminal for LCD display
Can be used as a general input/output
port
- Address
input
A0 to A7
Port B
(S8/PB0 to
S15/PB7)
I/O
Segment output terminal for LCD display
Can be used as a general input/output
port
- Address
input
A8 to A13
Port C
(S16/PC0 to
S23/PC7)
I/O
Segment output terminal for LCD display
Can be used as a general input/output
port
- PROM
control
signal input
TA (*5)
Address input
A14, A15
Port D
(S24/PD0 to
S31/PD7)
I/O
Segment output terminal for LCD display
Can be used as a general input/output
port
- -
Port E
(S32/PE0 to
S39/PE7)
I/O
Segment output terminal for LCD display
Can be used as a general input/output
port
- -
Port F
(S40/PF0 to
S47/PF7)
I/O
Segment output terminal for LCD display
Can be used as a general input/output
port
- -
Port L
(COM0/PL0
to
COM3/PL3)
I/O
Common output terminal for LCD display
Can be used as a general input port
- -
V1/PL4
V3/PL6
I
Bias power terminal for LCD drive
Can be used as a general input port
- -
RES
I Reset
pin
-
-
XT1/ P74
I
Input pin for 32.768kHz crystal
oscillation
In case of non use, connect to VDD.
Other function
A general input port P74
- -
XT2/P75 O
(I)
Output pin for 32.768kHz crystal
oscillation
In case of non use, should be left
unconnected
Other function
A general input port P75
- -
CF1
I
Input pin for ceramic resonator
oscillation
- -
CF2
O
Output pin for ceramic resonator
oscillation
- -
* All of port options can be specified in bit unit except the pull-up resistor of port 0.
[Notes] The VDD1, VDD2 and VDD3 terminals must be shorted electrically each other.
The VSS1, VSS2 and VSS3 terminals must be shorted electrically each other.
*1 Connect like the following figure to reduce noise into a VDD terminals.
*2 Memory select input for data security
*3 Output enable input
*4 Chip enable input
*5 TA ! PROM control signal input
LSI
VSS1 VSS2 VSS3
VDD1
VDD2
VDD3
Power
Supply
LC86P7248
No.6838-9/20
1. Absolute Maximum Ratings at Ta=25
C, VSS=VSS1=VSS2=VSS3=0V
Ratings
Parameter Symbol
Pins
Conditions
VDD
[V]
min. typ. max.
unit
Supply voltage
VDDMAX VDD1, VDD2
VDD3
VDD1=VDD2=
VDD3
-0.3 +7.0
LCD display
voltage
VLCD V1/PL6,
V2/PL5
V3/PL4
VDD1=VDD2=
VDD3
-0.3 VDD
Input voltage
VI
Ports 71, 72, 73
Ports 74 , 75
Port 8, Port L
RES
-0.3
VDD+0.3
Input/output
voltage
VIO
Port 0, 1, 3
Port 70
Ports A,B,C,D,E,F
-0.3
VDD+0.3
V
IOPH(1)
Ports 0, 1, 3
-4
Peak
output
current
IOPH(2) Ports
A,B,C,D,E,F
CMOS output
At each pins
-4
IOAH(1) Ports 0, 1, 32, 33,
34, 35
Total all pins
-38
IOAH(2) Ports 30, 31
Total all pins
-4
IOAH(3) Ports S0 to S25
Total all pins
-25
High
level
output
current
Total
output
current
vIOAH(4) Ports S26 to S47
Total all pins
-25
IOPL(1)
Ports 0, 1, 3
At each pins
20
IOPL(2)
Ports A,B,C,D,E,F
At each pins
20
Peak
output
current IOPL(3)
Port 70
At each pins
15
IOAL(1) Ports 0, 1, 32, 33,
34, 35
Total
all
pins
50
IOAL(2) Ports 30, 31
Total all pins
20
IOAL(3) Ports S0 to S25
Total all pins
39
IOAL(4) Ports S26 to S47
Total all pins
33
Low
level
output
current Total
output
current
IOAL(5) Port 70
Total all pins
10
mA
Maximum
power
dissipation
Pdmax QIP100E
Ta=-30 to +70
C
515
mW
Operating
temperature
range
Topr
-30 +70
Storage
temperature
range
Tstg
-55
+125
C
Notes
The QIP packages should be heat-soaked for 12 hours at 125
C immediately prior to mounting (This baking is called
pre-baking).
After pre-baking, a controlled environment must be maintained until soldering. The environment must be held at a
temperature of 30
C or less and a humidity level of 70% or less. Please solder within 24 hours.
LC86P7248
No.6838-10/20
2. Recommended Operating Range at Ta=-30
C to +70
C, VSS=VSS1=VSS2=VSS3=0V
Ratings
Parameter Symbol
Pins
Conditions
VDD[V] min. typ. max.
unit
VDD(1)
0.98
s
t
CYC
400
s
4.5 6.0
Operating
supply voltage
range
VDD(2)
VDD1=VDD2=
VDD3
3.9
s
t
CYC
400
s
2.5 6.0
Hold voltage
VHD
VDD1=VDD2=
VDD3
RAMs and the
registers hold voltage
at HOLD mode.
2.0 6.0
VIH(1)
Port 0
Output disable
4.5 to 6.0 0.4VDD
+0.9
VDD
VIH(2) Ports
1,
3
Ports A,B,C,D,E,F,L
Ports 72, 73
Output disable
4.5 to 6.0 0.75VDD
VDD
VIH(3) Port
70
Port input/interrupt
Port 71
RES
Output N-channel
Tr. OFF
4.5 to 6.0 0.75VDD
VDD
VIH(4) Port
70
Watchdog timer
Output N-channel
Tr. OFF
4.5 to 6.0 0.9VDD
VDD
Input high
voltage
VIH(5) Port
8
Port 74 ,75
Using as port
4.5-6.0 0.75VDD
VDD
VIL(1)
Port 0
Output disable
4.5 to 6.0 VSS
0.2VDD
VIL(2) Ports
1,
3
Ports A,B,C,D,E,F,L
Ports 72, 73
Output disable
4.5 to 6.0 VSS
0.25VDD
VIL(3) Port
70
Port input/interrupt
Port 71
RES
Output N-channel
Tr. OFF
4.5 to 6.0 VSS
0.25VDD
VIL(4) Port
70
Watchdog timer
Output N-channel
Tr. OFF
4.5 to 6.0 VSS
0.8VDD
-1.0
Input low
voltage
VIL(5) Port
8
Port 74 ,75
Using as port
4.5 to 6.0 VSS
0.25VDD
V
Operation
cycle time
t
CYC
4.5 to 6.0 0.98
400
s
FmCF(1)
CF1, CF2
6MHz (ceramic
resonator oscillation)
Refer to figure 1
4.5 to 6.0
6
FmCF(2)
CF1, CF2
3MHz (ceramic
resonator oscillation)
Refer to figure 1
4.5 to 6.0
3
FmRC
RC oscillation
4.5 to 6.0
0.4
0.8
3.0
MHz
Oscillation
frequency
range
(Note 1)
FsXtal
XT1, XT2
32.768kHz (crystal
oscillation)
Refer to figure 2
4.5 to 6.0
32.768
kHz
tmsCF(1)
CF1, CF2
6MHz (ceramic
resonator oscillation)
Refer to figure 3
4.5 to 6.0
tmsCF(2)
CF1, CF2
3MHz (ceramic
resonator oscillation)
Refer to figure 3
4.5 to 6.0
ms
Oscillation
stabilizing
time period
(Note 1)
tssXtal
XT1, XT2
32.768kHz (crystal
oscillation)
Refer to figure 3
4.5 to 6.0
s
(Note 1) The oscillation constant is shown on table 1 and table 2.
LC86P7248
No.6838-11/20
3. Electrical Characteristics at Ta=-30
C to +70
C, VSS=VSS1=VSS2=VSS3=0V
Ratings
Parameter Symbol
Pins
Conditions
VDD[V] min. typ. max.
unit
IIH(1) Port
1
Port 0 without
pull-up MOS Tr.
Output disable
Pull-up MOS Tr.
OFF. VIN=VDD
(including the off-
leak current of the
output Tr.)
4.5 to 6.0
1
IIH(2)
Port 7 without
pull-up MOS Tr.
Port 8
VIN=VDD
4.5 to 6.0
1
IIH(3)
Port 3
VIN=VDD
4.5 to 6.0
1
IIH(4) Ports
A,B,C,D,E,F,L
VIN=VDD
4.5 to 6.0
1
IIH(5)
RES
VIN=VDD
4.5 to 6.0
1
Input high
current
IIH(6)
Ports 74 ,75
Using as port
VIN=VDD
4.5 to 6.0
1
IIL(1) Port
1
Port 0 without
pull-up MOS Tr.
Output disable
Pull-up MOS Tr.
OFF. VIN=VSS
(including the off-
leak current of the
output Tr.)
4.5 to 6.0
-1
IIL(2)
Port 7 without
pull-up MOS Tr.
Port 8
VIN=VSS
4.5 to 6.0
-1
IIL(3)
Port 3
VIN=VSS
4.5 to 6.0
-1
IIL(4) Ports
A,B,C,D,E,F,L
VIN=VSS
4.5 to 6.0
-1
IIL(5)
RES
VIN=VSS
4.5 to 6.0
-1
Input low
current
IIL(6)
Ports 74 ,75
Using as port
VIN=VSS
4.5 to 6.0
-1
A
VOH(1)
Ports 0,1 of
CMOS output
IOH=-1.0mA
4.5 to 6.0 VDD-1
Output high
voltage
VOH(2)
Port 3 of CMOS
output
Ports A,B,C,D,E,F
of CMOS output
IOH=-1.0mA
4.5 to 6.0 VDD-1
VOL(1)
IOL=10mA
4.5 to 6.0
1.5
VOL(2)
Ports 0, 1
IOL=1.6mA
4.5 to 6.0
0.4
VOL(3)
Port 70
IOL=1mA
4.5 to 6.0
0.4
VOL(4)
IOL=10mA
4.5 to 6.0
1.5
VOL(5)
Port 3
IOL=1.6mA
4.5 to 6.0
0.4
VOL(6)
IOL=8mA
4.5 to 6.0
1.5
Output low
voltage
VOL(7)
Ports A,B,C,D,E,F
Of CMOS output
IOL=1.6mA
4.5 to 6.0
0.4
V
Continue.
LC86P7248
No.6838-12/20
Ratings
Parameter Symbol
Pins
Conditions
VDD[V] min.
typ. max.
unit
VODLS
S0 to S47
Deference voltage
to ideal value
VLCD, 2/3VLCD,
1/3VLCD
4.5 to 6.0
0
0.2
LCD output
regulation
VODLC COM0 to COM3
Deference voltage
to ideal value
VLCD, 2/3VLCD,
1/2VLCD, 1/3VLCD
4.5 to 6.0
0
0.2
V
RLCD(1)
Resistance at a
ladder resistor
4.5 to 6.0
60
LCD ladder
resistor
RLCD(2)
Resistance at a
ladder resistor
1/2R mode
4.5 to 6.0
30
Pull-up MOS
Tr. resistor
Rpu
Ports 0, 1, 3
Ports A,B,C,D,E,F
Ports 70, 71, 72, 73
VOH=0.9VDD
4.5 to 6.0
15
40
70
k
Hysteresis
voltage
VHIS Port
1
Ports 70, 71, 72, 73
RES
Output disable
4.5 to 6.0
0.1VDD
V
Pin
capacitance
CP All
pins
f=1MHz
Unmeasurement
terminals for the
input are set to
VSS level.
Ta=25
C
4.5 to 6.0
10
pF
4. Serial Input/Output Characteristics at Ta=-30
C to +70
C, VSS=VSS1=VSS2=VSS3=0V
Ratings
Parameter Symbol
Pins Conditions
VDD[V] min. typ. max.
unit
Cycle t
CKCY
(1) 2
Low Level
pulse width
t
CKL
(1) 1
In
put
c
l
oc
k
High Level
pulse width
t
CKH
(1)
SCK0,
SCK1
Refer to figure 5.
4.5 to 6.0
1
Cycle t
CKCY
(2) 2
Low Level
pulse width
t
CKL
(2)
1/2
t
CKCY
Se
ri
al
cl
o
c
k
O
u
t
put c
l
o
c
k
High Level
pulse width
t
CKH
(2)
SCK0,
SCK1
Use pull-up
resistor (1k
)
when open drain
output.
Refer to figure 5.
4.5 to 6.0
1/2
t
CKCY
t
CYC
Data set up time
t
ICK
4.5 to 6.0
0.1
S
e
r
i
a
l
inpu
t
Data hold time
t
CKI
SI0,SI1
SB0,SB1
Data set-up to
SCK0, 1
Data hold from
SCK0, 1
Refer to figure 5.
4.5 to 6.0
0.1
Output delay time
(Serial clock is
external clock)
t
CKO(1)
4.5 to 6.0
7/12tCYC
+0.2
S
e
r
i
a
l
outp
u
t
Output delay time
(Serial clock is
internal clock)
t
CKO(2)
SO0, SO1
SB0, SB1
Use pull-up
resistor (1k
)
when open drain
output.
Data hold from
SCK0, 1
Refer to figure 5.
4.5 to 6.0
1/3tCYC
+0.2
s
LC86P7248
No.6838-13/20
5. Pulse Input Conditions at Ta=-30
C to +70
C, VSS=VSS1=VSS2=VSS3=0V
Ratings
Parameter Symbol
Pins
Conditions
VDD[V] min. typ. max.
unit
tPIH(1)
tPIL(1)
INT0, INT1
INT2/T0IN
Interrupt acceptable
Timer0-countable
4.5 to 6.0
1
tPIH(2)
tPIL(2)
INT3/T0IN
(The noise rejection
clock is selected to
1/1.)
Interrupt acceptable
Timer0-countable
4.5 to 6.0
2
tPIH(3)
tPIL(3)
INT3/T0IN
(The noise rejection
clock is selected to
1/16.)
Interrupt acceptable
Timer0-countable
4.5 to 6.0
32
tPIH(4)
tPIL(4)
INT3/T0IN
(The noise rejection
clock is selected to
1/64.)
Interrupt acceptable
Timer0-countable
4.5 to 6.0 128
t
CYC
High/low level
pulse width
tPIL(5)
RES
Reset acceptable
4.5 to 6.0 200
s
6. AD Converter Characteristics at Ta=-30
C to + 70
C, VSS=VSS1=VSS2=VSS3=0V
Ratings
Parameter Symbol
Pins
Conditions
VDD[V] min. typ. max. unit
Resolution
NAD
4.5 to 6.0
8
bit
Absolute precision
(Note 2)
ETAD
4.5 to 6.0
1.5
LSB
AD conversion time =
16
tCYC
(ADCR2=0)
(Note 3)
15.68
(tCYC=
0.98
s)
65.28
(tCYC=
4.08
s)
Conversion time
tCAD
AD conversion time =
32
tCYC
(ADCR2=1)
(Note 3)
4.5 to 6.0
31.36
(tCYC=
0.98
s)
130.56
(tCYC=
4.08
s)
s
Analog input
voltage range
VAIN
4.5 to 6.0 VSS
VDD
V
IAINH
VAIN=VDD
4.5 to 6.0
1
Analog port
input current
IAINL
AN0 - AN7
VAIN=VSS
4.5 to 6.0
-1
A
(Note 2) Absolute precision excepts quantizing error (
1/2 LSB).
(Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital
conversion value to the register.
LC86P7248
No.6838-14/20
7. Current Dissipation Characteristics at Ta=-30
C to +70
C, VSS=VSS1=VSS2=VSS3=0V
Ratings
Parameter Symbol
Pins Conditions
VDD[V] min. typ. max.
unit
IDDOP(1) FmCF=6MHz
Ceramic resonator
oscillation
FsXtal=32.768kHz
crystal oscillation
System clock :
CF oscillation
Internal RC
oscillation stops
1/1 divided
4.5 to 6.0
15
30
IDDOP(2) FmCF=3MHz
Ceramic resonator
oscillation
FsXtal=32.768kHz
crystal oscillation
System clock :
CF oscillation
Internal RC
oscillation stops
1/2 divided
4.5 to 6.0
6
15
IDDOP(3) FmCF=0Hz
(when oscillation
stops)
FsXtal=32.768kHz
crystal oscillation
System clock :
RC oscillation
1/2 divided
4.5 to 6.0
4
13
Current dissipation
during basic
operation
(Note 4)
IDDOP(4)
VDD1=
VDD2=
VDD3
FmCF=0Hz
(when oscillation
stops)
FsXtal=32.768kHz
crystal oscillation
System clock :
crystal oscillation
Internal RC
oscillation stops
1/2 divided
4.5 to 6.0
4
9
mA
Continue.
LC86P7248
No.6838-15/20
Ratings
Parameter Symbol
Pins Conditions
VDD[V] min. typ. max.
unit
IDDHALT(1) HALT
mode
FmCF=6MHz
Ceramic resonator
oscillation
FsXtal=32.768kHz
crystal oscillation
System clock :
CF oscillation
Internal RC
oscillation stops
1/1 divided
4.5 to 6.0
6
11
IDDHALT(2) HALT
mode
FmCF=3MHz
Ceramic resonator
oscillation
FsXtal=32.768kHz
crystal oscillation
System clock :
CF oscillation
Internal RC
oscillation stops
1/2 divided
4.5 to 6.0
2.2
9
mA
IDDHALT(3) HALT
mode
FmCF=0Hz
(when oscillation
stops)
FsXtal=32.768kHz
crystal oscillation
System clock :
RC oscillation
1/2 divided
4.5 to 6.0
500
1700
IDDHALT(4)
Current dissipation
in HALT mode
(Note 4)
IDDHALT(5)
VDD1=
VDD2=
VDD3
HALT mode
FmCF=0Hz
(when oscillation
stops)
FsXtal=32.768kHz
crystal oscillation
System clock :
crystal oscillation
Internal RC
oscillation stops
1/2 divided
4.5 to 6.0
25
100
Current dissipation
in HOLD mode
(Note 4)
IDDHOLD(1) VDD1=
VDD2=
VDD3
HOLD mode
4.5 to 6.0
0.05
30
A
(Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored.
LC86P7248
No.6838-16/20
Table 1. Ceramic resonator oscillation guaranteed constant (main clock)
Oscillation type
Maker
Oscillator
C1
C2
6MHz ceramic resonator
oscillation
3MHz ceramic resonator
oscillation
* Both C1 and C2 must use K rank (
10%) and SL characteristics.
Table 2. Crystal oscillation recommended constant (sub clock)
Oscillation type
Maker
Oscillator
C3
C4
Rd
32.768kHz crystal oscillation
(Notes) Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close
to the oscillation pins as possible with the shortest possible pattern length.
If you use other oscillators herein, we provide no guarantee for the characteristics.
CF1
CF2
CF
C2
C1
C4
C3
X'tal
XT1
XT2
Rd
Figure 1 Ceramic oscillation circuit
Figure 2 Crystal oscillation circuit
LC86P7248
No.6838-17/20
< Reset time and oscillation stable time >
< HOLD release signal and oscillation stable time >
Figure 3 Oscillation stable time
VDD
VDD limit
0V
Reset time
tmsCF
tssXtal
Power supply
RES
Internal RC
resonator oscillation
CF1, CF2
Operation mode
XT1, XT2
Unfixed
Reset
Instruction execution mode
Instruction
execution mode
OCR6=1
tmsCF
tssXtal
Internal RC
resonator oscillation
CF1, CF2
Operation mode
XT1, XT2
HOLD
Instruction execution mode
Valid
HOLD release signal
LC86P7248
No.6838-18/20
RES
VDD
R
RES
C
RES
Figure 4 Reset circuit
0.5VDD
< AC timing point >
< Timing >
< Test load >
Figure 5 Serial input / output test condition
tPIL
tPIH
Figure 6 Pulse input timing condition
(Note) Fix the value of C
RES
, R
RES
that is
sure to reset until 200
s, after Power
supply has been over inferior limit of
supply voltage.
S00, S01
SB0, SB1
SI0
SI1
SCK0
SCK1
50pF
1k
VDD
tCKO
tCKI
tICK
tCKH
tCKL
tCKCY
LC86P7248
No.6838-19/20
Notice for use
The construction of the one-time programmable microcomputer with a blank built-in PROM makes it impossible for Sanyo to
completely factory-test it before shipping. To probe reliability of the programmed devices, the screening procedure shown
in the following figure should always be followed.
It is not possible to perform a writing test on the blank PROM. 100% yield, therefore, cannot be guaranteed.
Keeping the dry packing
The environment must be held at a temperature of 30
C or less and a humidity level of 70% or less.
After opening the packing
The preparation procedures shown in the following figure should always be followed prior to mounting the packages on the
substrate. Note that the QIP package should be heat-soaked for 12 hours at 125
C immediately prior to mounting (This
baking is called pre-baking). After pre-baking, a controlled environment must be maintained until soldering. The
environment must be held at a temperature of 30
C or less and a humidity level of 70% or less. Please solder within 24
hours.
a. Shipping with a blank PROM
b. Shipping with a programmed PROM
(Programming the data by yourself)
(Programming the data by Sanyo)
Recommended process of screening
QIP
Writing data for program/Verifying
Heat-soak
1505
C, 24 Hr
+1
-0
Reading ascertain of program
VDD=50.5V
Mounting
QIP
Mounting
Baking before mounting
125
C, 12 hours
Baking
Baking before mounting
125
C, 12 hours
Baking
LC86P7248
No.6838-20/20
memo :
PS
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