CMOS LSI
Ordering number :
*
EN5572
22897HA (OT) No. 5572-1/11
Preliminary
LC897194
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
CD-ROM Decoder with Built-In ATAPI (IDE) and DVD
ECC Interfaces
Overview
The LC897194 provides CD-ROM functionality and
includes built-in DVD ECC and ATAPI (IDE) interfaces.
Function
CD-ROM ECC functionality, an ATAPI (IDE) interface
(the register and other blocks), and a DVD ECC
interface
Features
ATAPI (IDE) interface
DVD ECC interface
Supports up to 12
-speed playback (when using 70-ns
16-bit data path DRAM)
Transfer rate: 16.6 MB/s (when using 60-ns 16-bit data
path DRAM)
Transfer rate: 8.33 MB/s (when using 70-ns 8-bit data
path DRAM)
Between 1 and 32 Mbits of DRAM can be used as buffer
RAM.
The user can freely set up the CD main channel and the
C2 flags in buffer RAM.
Built-in batch transfer function (function for transferring
the CD main channel and the C2 flags in one operation)
Built-in multiple transfer function (function for
automatically transferring multiple blocks in a single
operation)
Package Dimensions
unit: mm
3214-SQFP144
SANYO: SQFP144
[LC897194]
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
DD
max
Ta = 25C
0.3 to +7.0
V
I/O voltages
V
I
, V
O
Ta = 25C
0.3 to V
DD
+0.3
V
Allowable power dissipation
Pd max
Ta
70C
550
mW
Operating temperature
Topr
30 to +70
C
Storage temperature
Tstg
55 to +125
C
Soldering heat resistance (pins only)
10 seconds
235
C
Maximum I/O power
I
I
, I
O
max
20
*
mA
Specifications
Absolute Maximum Ratings
at V
SS
= 0 V
Note: Per basic I/O cell.
No. 5572-2/11
LC897194
Parameter
Symbol
Applicable pins (see below)
Ratings
Unit
min
typ
max
Input high-level voltage
V
IH1
TTL compatible: (1)
2.2
V
Input low-level voltage
V
IL1
TTL compatible: (1)
0.8
V
Input high-level voltage
V
IH2
TTL compatible, with pull-up resistor: (12)
2.2
V
Input low-level voltage
V
IL2
TTL compatible, with pull-up resistor: (12)
0.8
V
Input high-level voltage
V
IH3
TTL compatible, with pull-down resistor: (2)
2.2
V
Input low-level voltage
V
IL3
TTL compatible, with pull-down resistor: (2)
0.8
V
Input high-level voltage
V
IH4
TTL compatible, Schmitt characteristics: (3),
2.5
V
(5), (13), (14)
Input low-level voltage
V
IL4
TTL compatible, Schmitt characteristics: (3),
0.6
V
(5), (13), (14)
Input high-level voltage
V
IH5
CMOS compatible, Schmitt characteristics: (4)
0.8 V
DD
V
Input low-level voltage
V
IL5
CMOS compatible, Schmitt characteristics: (4)
0.2 V
DD
V
Output high-level voltage
V
OH1
I
OH
= 2 mA : (7), (10), (12)
V
DD
2.1
V
Output low-level voltage
V
OL1
I
OL
= 2 mA : (7), (10), (12)
0.4
V
Output high-level voltage
V
OH2
I
OH
= 8 mA : (6)
V
DD
2.1
V
Output low-level voltage
V
OL2
I
OL
= 8 mA : (6)
0.4
V
Output high-level voltage
V
OH3
I
OH
= 4 mA : (8), (13)
V
DD
2.1
V
Output low-level voltage
V
OL3
I
OL
= 24 mA : (8), (13)
0.4
V
Output high-level voltage
V
OH4
I
OL
= 24 mA : (9), (14)
0.4
V
Output low-level voltage
V
OL5
I
OL
= 2 mA : (11)
0.4
V
Input leakage current
I
IL
V
I
= V
SS
, V
DD
: (1), (2), (3), (4), (5), (12), (13),
10
+10
A
(14)
Output leakage current
I
OZ
When the output is high impedance: (9), (11),
10
+10
A
(13), (14)
Pull-up resistance
R
UP
(12)
40
80
160
k
Pull-down resistance
R
DN
(2)
40
80
160
k
DC Characteristics
at Ta = 30 to +70C, V
SS
= 0 V, V
DD
= 4.5 to 5.5 V
Note: The applicable pins are as follows:
INPUT
(1)
CSCTRL, RSSEL, HDB0 to 7, SUA0 to 6
(2)
TEST0 to 4
(3)
ZDMACK, ZHRST, ZRESET, BCK, C2PO, LRCK, SDATA, DA0 to 2, ZCS1FX, ZCS3FX
(4)
ZCS, ZRD, ZWR
(5)
ZDIOR, ZDIOW, DRESP, WFCK, SCOR
OUTPUT
(6)
MCK, MCK2
(7)
ZINT0, ZINT1
(8)
DMARQ, HINTRQ
(9)
IORDY, ZIOCS16
(10) RA0 to 9, ZCAS0 to 1, ZRAS0 to 1, ZLWE, ZUWE, ZOE, DREQ
(11) ZRSTCPU, ZRSTIC, ZSWAIT
INOUT
(12) D0 to 7, IO0 to 15
(13) DD0 to 15
(14) ZDASP, ZPDIAG
*
: The DC characteristics do not apply to the XTAL and XTALCK pins.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
DD
4.5
5.0
5.5
V
Input voltage range
V
IN
0
V
DD
V
Allowable Operating Ranges
at Ta = 30 to +70C, V
SS
= 0 V
Recommended Oscillator Circuit Example
R1 = 120 k
R2 = 47
C1 = 30 pF
With a crystal with a resonant frequency of 16.9344 MHz, or:
R1 = 3.3 k
R2 = None
C1 = 5 pF
With a crystal with a resonant frequency of 33.8688 MHz.
If third harmonics are a problem in the 33.8688-MHz recommended circuit, consult with the manufacturer of the crystal
for exact component values, since those values will be influenced by the printed circuit board used.
No. 5572-3/11
LC897194
Block Diagram
*1
BCK, SDATA, LRCK, C2PO
*2
DD0 to DD15, ZDASP, ZPDIAG
*3
ZCS1FX, ZCS3FX, DA0 to DA2, ZDIOR, ZDIOW, ZDMACK
*4
DMARQ, HINTRQ, ZIOCS16, IORDY, ZHRST
*5
ZRD, ZWR, SUA0 to SUA6, ZCS, CSCTRL
*6
D0 to D7
*7
IO0 to IO15
*8
RA0 to RA9, ZRAS0, ZRAS1, ZCAS0, ZCAS1, ZOE, ZUWE, ZLWE
*9
DREQ
*10 HDB0 to HDB7, DRESP
*11 WFCK, SCOR
**1 HISIDE (WD25C32) is made by WESTERN DIGITAL.
No. 5572-4/11
LC897194
No. 5572-5/11
LC897194
Pin Functions
typ
I
Input
B
Bidirection
NC
Not connected
O
Output
P
Power
Pin No.
Symbol
Type
Function
1
V
SS0
P
2
ZRAS0
O
RAS signal output 0 to the buffer DRAM (Output 0 is normally used.)
3
ZRAS1
O
RAS signal output 1 to the buffer DRAM
4
V
SS0
P
5
ZCAS0
O
CAS signal output 0 to the buffer DRAM (Output 0 is normally used.)
6
ZCAS1
O
CAS signal output 1 to the buffer DRAM
7
V
SS0
P
8
ZOE
O
Buffer RAM output enable
9
ZUWE
O
Buffer RAM upper write enable
10
ZLWE
O
Buffer RAM lower write enable
11
RA0
O
RA0 to RA9 are used for the data buffer DRAM address.
12
RA1
O
13
RA2
O
14
RA3
O
15
RA4
O
16
RA5
O
17
RA6
O
18
V
DD
P
19
V
SS0
P
20
RA7
O
RA0 to RA9 are used for the data buffer DRAM address.
21
RA8
O
22
RA9
O
23
TEST0
NC
Used for testing. There should be no connections to these pins.
24
TEST1
NC
These pins must be left open.
25
TEST2
NC
26
TEST3
NC
27
TEST4
NC
28
IO0
B
Data I/O to/from data buffer DRAM
29
IO1
B
Pull-up resistors are built in.
30
IO2
B
31
IO3
B
32
IO4
B
33
IO5
B
34
IO6
B
35
IO7
B
36
V
SS0
P
37
V
DD
P
Continued on next page.
PDF 
ZIP