SB1011
PRODUCT BRIEF
Revision: 1.1
Silicon Bridge Inc.,
1
April 10, 2003
41688 Christy Street, Fremont, CA 94538 (510)-360-8888
SILICON BRIDGE
FEATURES
Quad SerDes transceivers with Clock multiplier and
bias/reference that supports FC at 1.0625Gbps,
2.125Gbps, 4.25Gbps, XAUI-FC at 3.1875 Gbps,
XAUI at 3.125Gbps, PCI Express at 2.5Gbps.
10b/20b wide PMA functional blocks operating at
1Gbps - 4.25Gbps baud rate
Independent TX rate and RX rate selections for FC at
1.0625Gbps, 2.125Gbps, 4.25Gbps operation
Supports backplane traces, inter-rack interconnec-
tions, or copper cable FC Interfaces
Programmable 10-bit/7-bit detection word alignment
with programmable pattern for external control
Serial and parallel loopback modes
Programmable on chip termination resistors
Per-channel power down mode
Synchronizer (receive) PLL recovers clock and data
from input serial data stream
Single 1.5V supply
Less than 100 mW typical power consumption per
channel at 4.25 Gbps (preliminary target)
Available in TSMC 0.13mm generic CMOS FSG pro-
cess technology
Bumping technology supported
BENEFITS/ADVANTAGES
Low power
Integrated programmable pre-emphasis circuit which
opens up the transmitter eye at the end of a long PCB
traces or cable
Integrated equalization circuit which allows the re-
ceiver to recover clock and data over long PCB trace
or cable
Very low jitter generation < 3ps rms
Rich sets of control and monitor features
Rich sets of BIST features for device manufacturabil-
ity and reliability
Wide frequency range of operation
APPLICATIONS
1/2/4Gbps Fibre Channel
Gigabit Ethernet 1000-Base-X
10Gbps Ethernet XAUI to XGMII(optional)
10Gbps Fiber Channel and PCI Express
10Gbps CWDM fiber optic module
10Gbps Backplane & interconnect
Test equipment
XAUI or FC retimer
Figure 1.0: Typical Application Diagram
1-4.25G
XCVR
SB1011
1-4.25G
XCVR
1-4.25G
XCVR
1-4.25G
XCVR
CWDM
Optical
Module
1-4.25G
XCVR
SB1011
1-4.25G
XCVR
1-4.25G
XCVR
1-4.25G
XCVR
Custom
Blocks
CHASIS
1.0625/2.125/4.25Gbps Backplane
4X20b
4X20b
4x3.125Gbps
LINE CARD
ASIC
1-4.25G
XCVR
SB1011
1-4.25G
XCVR
1-4.25G
XCVR
1-4.25G
XCVR
Custom
4X20b
Blocks
ASIC
SB1011 Macro Cell
for backplane ASIC
SB1011 Macro Cell
for line card ASIC
or 4X3.1875Gbps
SB1011 - Quad 0.625 - 4.25Gbps Low Power CMOS
Transceiver Macro Cell in 0.13um TSMC Process
SB1011
PRODUCT BRIEF
Revision: 1.1
Silicon Bridge Inc.,
2
April 10, 2003
41688 Christy Street, Fremont, CA 94538 (510)-360-8888
SILICON BRIDGE
1.0 General Description
SB1011 is a feature-rich, programmable, high-performance transceiver macro cell which inte-
grates four channels of 3.125Gbps to reach an aggregate rates of up to 12.5Gbps. Each transceiv-
er port is capable of transmitting and receiving data rate from 0.625 to 4.25 Gbps. It is ideal for
10Gbps Ethernet, fibre channel, PCI Express, backplane, chip to chip interconnect and test equip-
ment applications.
The macro is ideal for embedded SOC applications and consists of an on chip serializer, deserialz-
er, clock and data recovery (CDR), a transmit Phase Lock Loop (TXPLL), receive equalizer, clock
synthesizer, transmit FIFO, optional serial MDIO port, programmable pre-emphasis, termination
resistors, equalizer, and BIST functions.
In the tranmsitter path, the SB1011 takes in an 10/20 bit interface and latches them into the TX
FIFO.The built-in FIFO compensates for phase matching between clocks. Each deserializer which
operates up to 3.125Gbps, includes a programmable pre-emphasis circuit and programmable 50/
75 termination resistors. The pre-emphasis circuit enables the device to open up the transmit eye
as the signal travels across a lossy PCB traces.
In the receiver path, the device receives serial NRZ data, performs signal equalization, clock and
data recovery, deserialzation, symobl alignment and outputs it to the 10b/20b interface. The re-
ceive equalization circuit allows the receiver to recover the data across long lossy PCB traces or
cable. Furthermore, the receiver provides a feature which retimes the recovered data and directly
loop it to the transmitter for the repeater or XAUI retimer application.
Each tansceiver can be independently programmed and configured to "half rate" or "quarter rate"
transmit or receive speeds through local independent dividers. This uniques feature enables the
SB1011 suitable for 1/2/4G Fibre Channel applications. Moreoever, a rich sets of programmable
features are accessed through optional MDIO interface. PRBS, incremental patterns, serial for-
ward/reverse, and parallel loopbacks are part of the built-in self test (BIST) of the device.
CDR
TX
Serializer
PRBS
10
b/
2
0
b I
n
terfa
c
e
XAU
I/
FC
/
P
C
I
Expr
ess Int
e
rfac
e
Channel 1
Channel 2
Channel 3
SB1011 Block Diagram
JTAG
SCAN
Power Down
MDIO I/F
MDIO Registers
TXPLL + Clock Synthesizer
Vrefgen
REFCLK+/-
RX
Equalizer
FIFO
Checker
PRBS
Generator
Pre-emp.
Circuit
retimed mode
parallel loopback mode
serial loopback mode
TXDATA
TXCLK
RXDATA
RXCLK
RXI+/-
TXO+/-
Deserialzer
Bit
Alignment
Channel 0
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