LH28F008SC
1
8M (1M 8) Flash Memory
Figure 2. TSOP 40-Pin Configuration
FEATURES
High-Density Symmetrically-Blocked
Architecture
Sixteen 64K Erasable Blocks
High-Performance
85 ns Read Access Time
Enhanced Automated Suspend Options
Byte Write Suspend to Read
Block Erase Suspend to Byte Write
Block Erase Suspend to Read
Enhanced Data Protection Features
Absolute Protection with V
PP
= GND
Flexible Block Locking
Block Erase/Byte Write Lockout during
Power Transitions
Extended Cycling Capability
100,000 Block Erase Cycles
1.6 Million Block Erase Cycles/Chip
Low Power Management
Deep Power-Down Mode
Automatic Power Saving Mode Decreases
I
CC
in Static Mode
Automated Byte Write and Block Erase
Command User Interface
Status Register
SmartVoltage Technology
3.3 V or 5 V V
CC
3.3 V, 5 V, or 12 V V
PP
SRAM - Compatible Write Interface
ETOXTM V Nonvolatile Flash Technology
Industry - Standard Packaging
42-Pin, .67 mm 8 mm
2
CSP Package
40-Pin, 1.2 mm 10 mm 20 mm
TSOP (Type I) Package
44-Pin, 600-mil, SOP Package
28F008SC-1
TOP VIEW
40-PIN TSOP
2
3
4
5
8
9
A
12
A
15
37
36
35
34
33
32
29
26
6
7
A
13
A
14
A
16
A
19
A
17
A
18
31
30
OE
RY/BY
DQ
6
10
11
12
39
38
WE
13
28
DQ
3
DQ
2
DQ
1
27
DQ
7
14
15
16
17
18
19
20
23
25
24
22
21
A
0
A
1
A
2
A
3
A
6
A
5
A
7
A
4
A
10
A
9
A
11
A
8
NC
DQ
5
DQ
4
V
CC
DQ
0
40
1
NC
V
PP
V
CC
RP
CE
GND
GND
28F008SC-20
TOP VIEW
42-PIN CSP
A
5
A
A
8
A
11
V
PP
A
12
A
15
A
17
1
2
3
4
5
6
7
A
4
A
7
A
10
V
CC
A
18
A
13
NC
A
6
A
9
RP
CE
A
14
A
16
A
19
A
3
DQ
1
NC
V
CC
DQ
4
DQ
7
NC
A
2
A
0
DQ
3
GND
DQ
6
OE
NC
A
1
B
C
D
E
F
DQ
0
DQ
2
GND
DQ
5
RY/BY
WE
Figure 1. CSP 42-Pin Configuration
LH28F008SC
8M (1M 8) Flash Memory
2
Figure 3. SOP 44-Pin Configuration
V
CC
VOLTAGE
V
PP
VOLTAGE
3.3 V
3.3 V, 5 V, 12 V
5 V
5 V, 12 V
INTRODUCTION
SHARP'S LH28F008SC FlashFileTM memory with
SmartVoltage technology is a high-density, low-cost, non-
volatile, read/write storage solution for a wide range of
applications. Its symmetrically-blocked architecture, flex-
ible voltage and extended cycling provide for highly flex-
ible component suitable for resident flash arrays, SIMMs
and memory cards. Its enhanced suspend capabilities pro-
vide for an ideal solution for code and data storage appli-
cations. For secure code storage applications, such as
networking, where code is either directly executed out of
flash or downloaded to DRAM, the LH28F008SC offers
three levels of protection: absolute protection with V
PP
at
GND, selective hardware block locking, or flexible software
block locking. These alternatives give designers ultimate
control of their code security needs.
The LH28F008SC is manufactured on SHARP's
0.4 m ETOXTM V process technology. It comes in in-
dustry-standard packages: the 40-pin TSOP, ideal for
board constrained applications, and the rugged 44-pin
SOP. Based on the 28F008SA architecture, the
LH28F008SC enables quick and easy upgrades for
designs demanding the state-of-the art.
New Features
The LH28F008SC SmartVoltage FlashFile memory
maintains backwards-compatiblity with SHARP'S
28F008SA. Key enhancements over the 28F008SA
include:
SmartVoltage Technology
Enhanced Suspend Capabilities
In-System Block Locking
Both devices share a compatible pinout, status reg-
ister, and software command set. These similarities
enable a clean upgrade from the 28F008SA to
LH28F008SC. When upgrading, it is important to note
the following differences:
Because of new feature support, the two devices
have different device codes. This allows for soft-
ware optimization.
V
PPLK
has been lowered from 6.5 V to 1.5 V to
support 3.3 V and 5 V block erase, byte write, and
lock-bit configuration operations. Designs that
switch V
PP
off during read operations should make
sure that the V
PP
voltage transitions to GND.
To take advantage of SmartVoltage technology,
allow V
PP
connection to 3.3 V or 5 V.
DESCRIPTION
The LH28F008SC is a high-performance 8M Smart-
Voltage FlashFile memory organized as 1M of 8 bits. The
1M of data is arranged in sixteen 64K blocks which are
individually erasable, lockable, and unlockable in-system.
The memory map is shown in Figure 5.
SmartVoltage technology provides a choice of V
CC
and V
PP
combinations, as shown in the Voltage Combi-
nations Table, to meet system performance and power
expectations. 3.3 V V
CC
consumes approximately one-
fourth the power of 5 V V
CC
. But, 5 V V
CC
provides the
highest read performance. V
PP
at 3.3 V and 5 V elimi-
nates the need for a separate 12 V converter, while
V
PP
= 12 V maximizes block erase and byte write per-
formance. In addition to flexible erase and program volt-
ages, the dedicated V
PP
pin gives complete data
protection when V
PP
V
PPLK
.
V
CC
and V
PP
Voltage Combinations
Offered by SmartVoltage Technology
28F008SC-2
TOP VIEW
44-PIN SOP
2
3
4
5
8
9
A
6
A
9
41
40
39
38
37
36
33
30
6
7
A
7
A
8
A
10
V
PP
A
11
RP
35
34
10
11
12
43
42
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
13
32
NC
NC
WE
31
14
15
16
17
18
19
20
27
29
28
26
25
RY/BY
DQ
7
DQ
6
DQ
5
DQ
3
DQ
2
DQ
1
DQ
0
21
22
24
23
DQ
4
V
CC
GND
GND
A
2
A
1
A
3
A
0
CE
OE
44
1
V
CC
NC
A
4
NC
A
5
NC
NC
8M (1M 8) Flash Memory
LH28F008SC
3
Figure 4. LH28F008SC Block Diagram
OUTPUT
BUFFER
IDENTIFIER
REGISTER
DATA
REGISTER
STATUS
REGISTER
INPUT
BUFFER
A
0
- A
19
DQ
0
- DQ
7
ADDRESS
LATCH
I/O LOGIC
DATA
COMPARATOR
WRITE STATE
MACHINE
RY/BY
RP
OE
WE
CE
PROGRAM/
ERASE
VOLTAGE
SWITCH
Y-GATING
OUTPUT
MULTIPLEXER
Y-DECODER
X-DECODER
COMMAND
REGISTER
INPUT
BUFFER
. . .
ADDRESS
COUNTER
RP
V
CC
V
PP
GND
16 64KB BLOCKS
28F008SC-3
Internal V
CC
and V
PP
detection Circuitry automati-
cally configures the device for optimized read and write
operations.
A Command User Interface (CUI) serves as the in-
terface between the system processor and internal op-
eration of the device. A valid command sequence written
to the CUI initiates device automation. An Internal Write
State Machine (WSM) automatically executes the algo-
rithms and timings necessary for block erase, byte write,
and lock-bit configuration operations.
A block erase operation erases one of the device's
64K blocks typically within 1 second (5 V V
CC
, 12 V V
PP
)
independent of other blocks. Each block can be inde-
pendently erased 100,000 times (1.6 million block erases
per device). Block erase suspend mode allows system
software to suspend block erase to read or write data
from any other block.
Writing memory data is performed in byte increments
typically within 6 s (5 V V
CC
, 12 V V
PP
). Byte write sus-
pend mode enables the system to read data or execute
code from any other flash memory array location.
Individual block locking uses a combination of bits,
sixteen block lock-bits and a master lock-bit, to lock and
unlock blocks. Block lock-bits gate block erase and byte
write operations, while the master lock-bit gates block
lock-bit modification. Lock-bit configuration operations
(Set Block, Lock-Bit, Set Master Lock-Bit, and Clear
Block Lock-Bits commands) set and cleared lock-bits.
The status register indicates when the WSM's block
erase, byte write, or lock-bit configuration operation is
finished.
LH28F008SC
8M (1M 8) Flash Memory
4
PIN DESCRIPTION
SYMBOL
TYPE
NAME AND FUNCTION
A
0
- A
19
INPUT
ADDRESS INPUTS:
Inputs for addresses during read and write operations.
Addresses are internally latched during a write cycle.
DQ
0
- DQ
7
INPUT/OUTPUT
DATA INPUT/OUTPUTS:
Inputs data and commands during CUI write cycles; outputs
data during memory array, status register and identifier code read cycles. Data pins
float to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.
CE
INPUT
CHIP ENABLE:
Activates the device's control logic input buffers, decoders, and
sense amplifiers. CE
high deselects the device and reduces power consumption to
standby levels.
RP
INPUT
RESET/DEEP POWER-DOWN:
Puts the device in deep power-down mode and resets
internal automation. RP
high enables normal operation. When driven low, RP
inhibits
write operations which provides data protection during power transitions. Exit from deep
power-down sets the device to read array mode. RP
at V
HH
enables setting of the
master lock-bit and enables configuration of block lock-bits when the master lock-bit is
set. RP
= V
HH
overrides block lock-bits thereby enabling block erase and byte write
operation to locked memeory blocks. Block erase, byte write, or lock-bit configuration
with V
IH
< RP
< V
HH
produce spurious results and should not be attempted.
OE
INPUT
OUTPUT ENABLE:
Gates the device's outputs during a read cycle.
WE
INPUT
WRITE ENABLE:
Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE Pulse.
RY
/BY
OUTPUT
READY/BUSY:
Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, byte write, or lock-bit configuration).
RY
/BY
high indicates that the WSM is ready for new commands, block erase is
suspended, and byte write is inactive, byte write is suspended, or the device is in
deep power-down mode. RY
/BY
is always active and does not float when the chip
is deselected or data outputs are disabled.
V
PP
SUPPLY
BLOCK ERASE/BYTE WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY:
For erasing array blocks, writing bytes, or configuring lock-bits. With V
PP
V
LKO
,
memory contents cannot be altered. Block erase, byte write, and lock-bit configura-
tion with an invalid V
PP
(see DC Characteristics) produce spurious results and
should not be attempted.
V
CC
SUPPLY
DEVICE POWER SUPPLY:
Internal detection configures the device for 3.3 V or 5 V
operation. To switch from one voltage to another, ramp V
CC
down to GND and then
ramp V
CC
to the new voltage. Do not float any power pins. With V
CC
V
LKO
, all write
attempts to the flash memory are inhibited. Device operations at invalid V
CC
voltage
(see DC Characteristics) produce spurious results and should not be attempted.
GND
SUPPLY
GROUND:
Do not float any pins
NC
NO CONNECT:
Lead is not internal connected; it may be driven or floated.
8M (1M 8) Flash Memory
LH28F008SC
5
The RY
/BY
output gives an additional indicator of
WSM activity by providing both a hardware signal of
status (versus software polling) and status masking
(interrupt masking for background block erase, for
example). Status polling using RY
/BY
minimizes both
CPU overhead and system power consumption. When
low, RY
/BY
indicates that the WSM is performing a block
erase, byte write, or lock-bit configuration. RY
/BY
high
indicates that the WSM is ready for a new command,
block erase is suspended (and byte write is inactive),
byte write is suspended, or the device is in deep power-
down mode.
The access time is 85 ns (t
AVAV
) over the commer-
cial temperature range (0C to +70C) and V
CC
supply
voltage range of 4.75 V - 5.25 V. At lower V
CC
voltages,
the access times are 90 ns (4.5 V - 5.5 V) and 120 ns
(3.0 V - 3.6 V).
The Automatic Power Savings (APS) feature substan-
tially reduces active current when the device is in static
mode (addresses not switching). In APS mode, the typi-
cal I
CCR
current is 1 mA at 5 V V
CC
.
When CE
and RP
pins are at V
CC
, the I
CC
CMOS
standby mode is enabled. When the RP
pin is at GND,
deep power-down mode is enabled which minimizes
power consumption and provides write protection dur-
ing reset. A reset time (t
PHQV
) is required from RP
switching high until outputs are valid. Likewise, the de-
vice has a wake time (t
PHEL
) from RP
-high until writes
to the CUI are recognized. With RP
at GND, the WSM
is reset and the status register is cleared.
The device is available in 40-pin TSOP (Thin Small
Outline Package, 1.2 mm thick) and 44-pin SOP (Small
Outline Package). Pinouts are shown in Figures 1 and 2.
PRINCIPLES OF OPERATION
The LH28F008SC SmartVoltage FlashFile memory
includes an on-chip WSM to manage block erase, byte
write, and lock-bit configuration functions. It allows for:
100% TTL-level control inputs, fixed power supplies dur-
ing block erasure, byte write, and lock-bit configuration,
and minimal processor overhead with RAM-like inter-
face timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and out-
put disable operations.
Status register and identifier codes can be accessed
through the CUI independent of the V
PP
voltage. High
voltage on V
PP
enables successful block erasure, byte
writing, and lock-bit configuration. All functions associ-
ated with altering memory contentsblock erase, byte
write, Lock-bit configuration, status, and identifier codes-
are accessed via the CUI and verified through the sta-
tus register.
Commands are written using standard microproces-
sor write timings. The CUI contents serve as input to
the WSM, which controls the block erase, byte write,
and lock-bit configuration. The internal algorithms are
regulated by the WSM, including pulse repetition, inter-
nal verification, and margining of data. Addresses and
data are internally latch during write cycles. Writing the
appropriate command outputs array data, accesses the
identifier codes, or outputs status register data.
Interface software that initiates and polls progress of
block erase, byte write, and lock-bit configuration can
be stored in any block. This code is copied to and ex-
ecuted from system RAM during flash memory updates.
After successful completion, reads are again possible
via the Read Array command. Block erase suspend al-
lows sytem software to suspend a block. Byte write sus-
pend allows system software to suspend a byte write to
read data from any other flash memory array location.
FFFFF
F0000
EFFFF
E0000
DFFFF
D0000
CFFFF
C0000
BFFFF
B0000
AFFFF
A0000
9FFFF
90000
8FFFF
80000
7FFFF
70000
6FFFF
60000
5FFFF
50000
4FFFF
40000
3FFFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
00000
64KB BLOCK
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
28F008SC-4
Figure 4. Memory Map
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