LH28F040SUTD-Z4

4M (512K × 8) Flash Memory

Figure 1. TSOP Configuration

FEATURES

512K × 8 Bit Configuration

5 V Write/Erase Operation (5 V V

, 3.3 V

)

for Write/Erase at as low as 2.9 V

Min. 2.7 V Read Capability
190 ns Maximum Access Time

= 2.7 V)

2 Banks Enable the Simultaneous
Read/Write/Erase Operation

32 Independently Lockable Blocks (16K)

100,000 Erase Cycles per Block

Automated Byte Write/Block Erase
Command User Interface
Status Register

System Performance Enhancement
Erase Suspend for Read
Two-Byte Write
Bank Erase

Data Protection
Hardware Erase/Write Lockout during

Power Transitions

Software Erase/Write Lockout

Independently Lockable for Write/Erase
on Each Block (Lock Block and Protect
Set/Reset)

20 µA (Maximum) I

in CMOS Standby

State-of-the-Art 0.55 µm ETOXTM
Flash Technology

40-Pin, 1.2 mm × 10 mm × 20 mm TSOP
(Type I) Package

28F040SUZ4-1

TOP VIEW

40-PIN TSOP

NC1

NC2

GND

4M (512K × 8) Flash Memory

LH28F040SUTD-Z4

PIN DESCRIPTION

SYMBOL

TYPE

NAME AND FUNCTION

- A

INPUT

BYTE-SELECT ADDRESSES:

Select a byte within one 16K block. These addresses

are latched during Data Writes.

- A

INPUT

BLOCK-SELECT ADDRESSES:

Select 1 of 16K Erase blocks. These addresses

are latched during Data Writes, Erase and Lock-Block operations.

- DQ

INPUT/OUTPUT

DATA INPUT/OUTPUT:

Inputs data and commands during CUI write cycles.

Outputs array, buffer, identifier or status data in the appropriate Read mode.
Floated when the chip is de-selected or the outputs are disabled.

, BE

INPUT

BANK ENABLE INPUTS

: Activate the device's control logic, input buffers, decoders

and sense amplifiers. CE

must be low to select the device. When BE

is low,

bank0 is active. When BE

is low, bank1 is active. Both BE

and BE

must not be

low at the same time.

INPUT

OUTPUT ENABLE:

Gates device data through the output buffers when low. The

outputs float to tri-state off when OE

is high.

INPUT

WRITE ENABLE:

Controls access to the CUI, Page Buffers, Data Queue Registers

and Address Queue Latches. WE is active low, and latches both address and data
(command or array) on its rising edge.

SUPPLY

ERASE/WRITE POWER SUPPLY (5.0 V ±0.5 V):

For erasing memory array blocks

or writing bytes into the flash array.

SUPPLY

DEVICE POWER SUPPLY (3.3 V ±0.3 V):

Do not leave any power pins floating.

GND

SUPPLY

GROUND FOR ALL INTERNAL CIRCUITRY:

Do not leave any ground pins floating.

NO CONNECTION

NC1, NC2

OPEN PIN:

But NC1 (between pin1 and pin2) and also NC2 (pin19 and pin20) are

connected inside package.

INTRODUCTION

Sharp's LH28F040SUTD-Z4 4M Flash Memory is a

revolutionary architecture which enables the design of
truly mobile, high performance, personal computing and
communication products. With innovative capabilities,
3.3 V low power operation and very high read/write per-
formance, the LH28040SU-Z4 is also the ideal choice
for designing embedded mass storage flash memory
systems.

The LH28F040SUTD-Z4 is a very high density, high-

est performance non-volatile read/write solution for solid-
state storage applications. Its independently lockable
32 symmetrical blocked architecture (16K each)
extended cycling, low power operation, very fast write
and read performance and selective block locking pro-
vide a highly flexible memory component suitable for
high density memory cards, Resident Flash Arrays and

PCMCIA-ATA Flash Drives. The LH28F040SUTD-Z4's
5.0 V/3.3 V power supply operation enables the design
of memory cards which can be read in 3.3 V system
and written in 5.0 V/3.3 V systems. Its x8 architecture
allows the optimization of memory to processor inter-
face. The flexible block locking option enables bundling
of executable application software in a Resident Flash
Array or memory card. Manufactured on Sharp's 0.55
µm ETOXTM process technology, the LH28F040SUTD-
Z4 is the most cost-effective, high-density 3.3 V flash
memory.

LH28F040SUTD-Z4 divides 4M into two areas. Each

area can read/write/erase independently. For example,
while you write and erase on one area, you can simul-
taneously read the data from the other area. This
enables users to reduce the number of components in
their system.

LH28F040SUTD-Z4

4M (512K × 8) Flash Memory

DESCRIPTION

The LH28F040SUTD-Z4 is a high performance 4M

(4,194,304 bit) block erasable non-volatile random
access memory organized as 256K × 8 × 2 banks. The
LH28F040SUTD-Z4 includes thirty-two 16K (16,384)
blocks. A chip memory map is shown in Figure 3.

The two banks, the one selected by BE

(bank0) and

the other selected by BE

(bank1) can be controlled

independently. For example, while erase the data in
bank0, the data in bank1 can be read out.

The implementation of a new architecture, with many

enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.

Among the significant enhancements of the

LH28F040SUTD-Z4:

3 V Read, 5 V Write/Erase Operation
(5 V V

, 3 V V

)

Low Power Capability (2.7 V V

Read)

Improved Write/Erase Performance
(Two-Byte Serial Write, Bank Erase)

Dedicated Block Write/Erase Protection

Command-Controlled Memory Protection
Set/Reset Capability

The LH28F040SUTD-Z4 will be available in a 40-pin,

1.2 mm thick × 10 mm × 20 mm TSOP (Type I) pack-
age. This form factor and pinout allow for very high board
layout densities.

A Command User Interface (CUI) serves as the sys-

tem interface between the microprocessor or micro-
controller and the internal memory operation.

Internal Algorithm Automation allows Byte Writes and

Block Erase operations to be executed using a Two-
Write command sequence to the CUI in the same way
as the LH28F008SA 8M Flash memory.

A Superset of commands have been added to the

basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:

Software Locking of Memory Blocks

Memory Protection Set/Reset Capability

Two-Byte Serial Writes in 8-bit Systems

Bank Erase All Unlocked Blocks

Writing of memory data is performed typically within

20 µs. A Block Erase operation erases one of the 32
blocks in typically 1.5 seconds, independent of the other
blocks.

LH28F040SUTD-Z4 allows to erase all unlocked

blocks for each bank selected by BE

or BE

. It is de-

sirable in case of which you have to implement Erase
operation maximum 32 times.

LH28F040SUTD-Z4 enables Two-Byte serial Write

which is operated by three times command input. This
feature can improve system write performance by up to
typically 17 µs per byte.

All operations are started by a sequence of Write

commands to the device. Status Register (described in
detail later) provide information on the progress of the
requested operation.

Same as the LH28F008SA, LH28F040SUTD-Z4

requires an operation to complete before the next op-
eration can be requested, also it allows to suspend block
erase to read data from any other block, and allow to
resume erase operation.

The LH28F040SUTD-Z4 provides user-selectable

block locking to protect code or data such as Device
Drivers, PCMCIA card information, ROM-Executable OS
or Application Code. Each block has an associated non-
volatile lock-bit which determines the lock status of the
block. In addition, the LH28F040SUTD-Z4 has a soft-
ware controlled master Write Protect circuit which pre-
vents any modifications to memory blocks whose lock-
bits are set.

When the device power-up, Write Protect Set/

Confirm command must be written both in bank0 and
bank1. Otherwise, all lock bits in the device remain
being locked, can't perform the Write to each block and
single Block Erase. Write Protect Set/Confirm command
must be written to reflect the actual lock status. How-
ever, when the device power-on, Erase All Unlocked
Blocks can be used. If used, Erase is performed with
reflecting actual lock status, and after that Write and
Block Erase can be used.

The LH28F040SUTD-Z4 contains Status Register to

accomplish various functions:

A Compatible Status Register (CSR) which is
100% compatible with the LH28F008SA Flash
memory's Status Register. This register, when used
alone, provides a straightforward upgrade capabil-
ity to the LH28F040SUTD-Z4 from a LH28F008SA
based design.

The LH28F040SUTD-Z4 is specified for a maximum

access time of 150 ns (t

ACC

) at 3.3 V operation (3.0 to

3.6 V) over the commercial temperature range (-20 to
+70°C). A corresponding maximum access time of
190 ns (t

ACC

) at 2.7 V (-20 to +70°C) is achieved for

reduced power consumption applications.

4M (512K × 8) Flash Memory

LH28F040SUTD-Z4

Figure 3. Memory Map

MEMORY MAP

The LH28F040SUTD-Z4 incorporates an Automatic

Power Saving (APS) feature which substantially reduces
the active current when the device is in static mode of
operation (addresses not switching).

In APS mode, the typical I

current is 2 mA at 3.3 V.

A bank reset mode of operation is enabled when

whole BE

(or BE

), WE

and OE

hold low more than 5

µs. In this mode, all operations are aborted, the internal
control circuit is reset and CSR register is cleared. When
the device power up, this bank reset operation must be
executed for each bank to initialize the control circuit. If
BE

(either BE

or BE

which is in low state) and or

and or OE

and or goes high, chip reset mode will

be finished. It needs more than 750 ns from one of the
BE

, WE

or OE

goes high until output data are valid. It

is impossible to reset the whole chip at once, the bank
reset must be executed separately for bank0 and bank1.

A CMOS Standby mode of operation is enabled when

transitions high with all input control pins at CMOS

levels. In this mode, the device draws an I

standby

current of 20 µA.

Please do not execute reprogramming 0 for the bit

which has already been programmed 0. Overwrite op-
eration may generate unerasable bit. In case of repro-
gramming 0 to the data which has been programmed 1.

Program 0 for the bit in which you want to change
data from 1 to 0.

Program 1 for the bit which has already been pro-
grammed 0.

For example, changing data from 10111101 to

10111100 requires 11111110 programming.

3FFFFH

Bank0 (BE

= Low)

Bank1 (BE

= Low)

3C000H

3BFFFH

38000H

37FFFH

34000H

33FFFH

30000H

2FFFFH

2C000H

2BFFFH

28000H

27FFFH

24000H

23FFFH

20000H

1FFFFH

1C000H

1BFFFH

18000H

17FFFH

14000H

13FFFH

10000H

0FFFFH

0C000H

0BFFFH

08000H

07FFFH

04000H

03FFFH

00000H

16KB BLOCK

3FFFFH

3C000H

3BFFFH

38000H

37FFFH

34000H

33FFFH

30000H

2FFFFH

2C000H

2BFFFH

28000H

27FFFH

24000H

23FFFH

20000H

1FFFFH

1C000H

1BFFFH

18000H

17FFFH

14000H

13FFFH

10000H

0FFFFH

0C000H

0BFFFH

08000H

07FFFH

04000H

03FFFH

00000H

16KB BLOCK

28F040SUZ4-3

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LH28F040SUTD-Z4

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LH28F040SUTD-Z4