LH28F160SGED-L10

16 M-bit (512 kB x 16 x 2-Bank)

SmartVoltage Dual Work Flash Memory

DESCRIPTION

The LH28F160SGED-L10 Dual Work flash memory
with SmartVoltage technology is a high-density,
low-cost, nonvolatile, read/write storage solution for
a wide range of applications. The LH28F160SGED-
L10 is the highest density, highest performance
non-volatile read/write solution for solid-state
storage applications. LH28F160SGED-L10 can
read/write/erase at V

= 2.7 V and V

= 2.7 V.

Its low voltage operation capability realizes longer
battery life and suits for cellular phone application.
Its symmetrically-blocked architecture, flexible
voltage and enhanced cycling capability provide for
highly flexible component suitable for resident flash
arrays, SIMMs and memory cards. Its enhanced
suspend capabilities provide for an ideal solution for
code + data storage applications. For secure code
storage applications, such as networking, where
code is either directly executed out of flash or
downloaded to DRAM, the LH28F160SGED-L10
offers three levels of protection : absolute protection
with V

at GND, selective hardware block locking,

or flexible software block locking. These alternatives
give designers ultimate control of their code security
needs.

FEATURES

· SmartVoltage Dual Work technology

2.7 V, 3.3 V or 5 V V

2.7 V, 3.3 V, 5 V or 12 V V

Capable of performing erase, write and read

for each bank independently (Impossible to
perform read from both banks at a time).

· High performance read access time

100 ns (5.0±0.5 V)/100 ns (3.3±0.3 V)/

120 ns (2.7 to 3.6 V)

· Enhanced automated suspend options

Word write suspend to read
Block erase suspend to word write
Block erase suspend to read

· Enhanced data protection features

Absolute protection with V

= GND

Flexible block locking
Block erase/word write lockout during power

transitions

· SRAM-compatible write interface
· High-density symmetrically-blocked architecture

Thirty-two 32 k-word erasable blocks

· Enhanced cycling capability

100 000 block erase cycles
1.6 million block erase cycles/bank

· Low power management

Deep power-down mode
Automatic power saving mode decreases Icc

in static mode

· Automated word write and block erase

Command user interface
Status register

· ETOX

V nonvolatile flash technology

· Package

48-pin TSOP Type I (TSOP048-P-1220)

Normal bend

ETOX is a trademark of Intel Corporation.

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In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

LH28F160SGED-L10

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PIN DESCRIPTION

SYMBOL

TYPE

NAME AND FUNCTION

-A

INPUT

ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses

are internally latched during a write cycle.

DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs

data during memory array, status register, and identifier code read cycles. Data pins

float to high-impedance when the chip is deselected or outputs are disabled. Data is

internally latched during a write cycle.

BANK ENABLE : Activates the device's control logic, input buffers, decoders, and

sense amplifiers. When BE

# are "low", bank0 is in active. When BE

# are "low", bank1

is in active. Both BE

# and BE

# must not be low at the same time. BE

#, BE

#-high

deselects the device and reduces power consumption to standby levels.

RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets

internal automation. RP#-high enables normal operation. When driven low, RP# inhibits

write operations which provide data protection during power transitions. Exit from deep

power-down sets the device to read array mode.

RP# at V

allows to set permanent lock-bit. Block erase, word write, or lock-bit

configuration with V

RP#

produce spurious results and should not be

attempted.

OE#

INPUT

OUTPUT ENABLE : Controls the device's outputs during a read cycle.

WE#

INPUT

WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are

latched on the rising edge of the WE# pulse.

WP#

INPUT

WRITE PROTECT : Master control for block locking. When V

, locked blocks cannot be

erased and programmed, and block lock-bits cannot be set and reset.

BLOCK ERASE, WORD WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY :

For erasing array blocks, writing words, or configuring lock-bits. With V

PPLK

memory contents cannot be altered. Block erase, word write, and lock-bit configuration

with an invalid V

(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious

results and should not be attempted.

DEVICE POWER SUPPLY : Internal detection configured the device for 2.7 V, 3.3 V or

5 V operation. To switch from one voltage to another, ramp V

down to GND and then

ramp V

to the new voltage. Do not float any power pins. With V

LKO

, all write

attempts to the flash memory are inhibited. Device operations at invalid V

voltage

(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should

not be attempted.

GND

SUPPLY

GROUND : Do not float any ground pins.

NO CONNECT : Lead is not internal connected; recommend to be floated.

-DQ

INPUT/

OUTPUT

INPUT

RP#

INPUT

SUPPLY

LH28F160SGED-L10

1 INTRODUCTION

This datasheet contains LH28F160SGED-L10
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F160SGED-
L10 flash memory documentation also includes
ordering information which is referenced in
Section 7.

1.1

New Features

Key enhancements of LH28F160SGED-L10
SmartVoltage Dual Work flash memory are :

· SmartVoltage Dual Work Technology
· Enhanced Suspend Capabilities
· In-System Block Locking
· Permanent Lock Capability

Note following important differences :

· V

PPLK

has been lowered to 1.5 V to support

3.3 V and 5 V block erase, word write, and lock-
bit configuration operations. Designs that switch
V

off during read operations should make sure

that the V

voltage transitions to GND.

· To take advantage of SmartVoltage technology,

allow V

connection to 2.7 V, 3.3 V or 5 V.

· Once set the permanent lock bit, the blocks

which have been set block lock-bit can not be
erased, written forever.

1.2

Product Overview

The LH28F160SGED-L10 is a high-performance
16 M-bit SmartVoltage Dual Work flash memory
organized as 1 024 k-word of 16 bits. The 1 024 k-
word of data is arranged in thirty-two 32 k-word
blocks which are individually erasable, lockable,
and unlockable in-system. The memory map is
shown in Fig. 1.

All pins except of BE# are shared by both banks,
and BE# is divided to BE

# and BE

# in order to

select one of banks. BE

# is assigned to No. 26

pin which is CE# in LH28F800SGE-L10, BE

is assigned to No. 27 pin which is GND in
LH28F800SGE-L10. To select either bank (bank0)
BE

# must be "L", and to select another bank

(bank1) BE

# must be "L". Selecting both banks

(bank0 and bank1) at a time, except of read
operation (array read, status register read), turns
both BE

# and BE

# to "L".

Operation mode of bank0 and bank1 as follows :
1) Both bank0 and bank1 are in deep power-down

(RP# = "L").

2) Both bank0 and bank1 are in standby

(BE

# = BE

# = "H").

3) Bank0 is in standby and bank1 is in active state

of programming or erase, or bank0 is in active
state of programming or erase and bank1 is in
standby.

4) Both bank0 and bank1 are in active state

(impossible to perform simultaneous read from
both banks). In this case bank0 and bank1
perform independent operation, for example,
after input Erase command to bank0 erase or
program command to bank1 is succeeded,
bank0 and bank1 perform each operation
concurrently.

SmartVoltage technology provides a choice of V

and V

combinations, as shown in Table 1, to

meet system performance and power expectations.
2.7 to 3.6 V V

consumes approximately one-fifth

the power of 5 V V

. But, 5 V V

provides the

highest read performance. V

at 3.3 V and 5 V

eliminates the need for a separate 12 V converter,
while V

= 12 V maximizes block erase and word

write performance. In addition to flexible erase and
program voltages, the dedicated V

pin gives

complete data protection when V

PPLK

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