4M (512K × 8, 256K × 16)

Flash Memory

LH28F400SUB-Z0

Figure 1. CSP Configuration

FEATURES

User-Configurable x8 or x16 Operation

5 V Write/Erase Operation
(5 V V

, 3.3 V V

)

No Requirement for DC/DC Converter to

Write/Erase

150 ns Maximum Access Time
(V

= 3.3 V ± 0.3 V)

Min. 2.7 V Read Capability
160 ns Maximum Access Time

= 2.7 V)

32 Independently Lockable Blocks (16K)

100,000 Erase Cycles per Block

Automated Byte Write/Block Erase
Command User Interface
Status Register
RY

/BY

Status Output

System Performance Enhancement
Erase Suspend for Read
Two-Byte Write
Full Chip Erase

Data Protection
Hardware Erase/Write Lockout during

Power Transition

Software Erase/Write Lockout

Independently Lockable for Write/Erase
on Each Block (Lock Block and Protect
Set/Reset)

4 µA (Typ.) I

in CMOS Standby

0.2 µA (Typ.) Deep Power-Down

State-of-the-Art 0.45 µm ETOXTM Flash
Technology

Extended Temperature Operation
-20°C to +85°C

49-Pin, .67 mm × 8 mm × 8 mm
CSP Package

28F400SUB-1

TOP VIEW

49-PIN CSP

RY/BY

-1

GND

BYTE

4M (512K × 8, 256K × 16) Flash Memory

LH28F400SUB-Z0

PIN DESCRIPTION

SYMBOL

TYPE

NAME AND FUNCTION

- A

-1

INPUT

BYTE-SELECT ADDRESSES:

Selects between high and low byte when device is in

x8 mode. This address is latched in x8 Data Writes. Not used in x16 mode (i.e., the
DQ

-1

Input buffer is turned off when BYTE is high).

- A

INPUT

WORD-SELECT ADDRESSES:

Select a word within one 16K block. These

addresses are latched during Data Writes.

- A

INPUT

BLOCK-SELECT ADDRESSES:

Select 1 of 32 Erase blocks. These addresses are

latched during Data Writes, Erase and Lock-Block operations.

- DQ

INPUT/OUTPUT

LOW-BYTE DATA BUS:

Inputs data and commands during CUI write cycles.

Outputs array, buffer, identifier or status data in the appropriate Read mode.
Floated when the chip is de-selected or the outputs are disabled.

- DQ

INPUT/OUTPUT

HIGH-BYTE DATA BUS:

Inputs data during x16 Data Write operations. Outputs

array, buffer or identifier data in the appropriate Read mode; not used for Status
register reads. Floated when the chip is de-selected or the outputs are disabled.
DQ

-1

is address.

INPUT

CHIP ENABLE INPUT:

Activate the device's control logic, input buffers, decoders

and sense amplifiers. CE

must be low to select the device.

INPUT

RESET/POWER-DOWN:

With RP

low, the device is reset, any current operation is

aborted and device is put into the deep power down mode. When the power is
turned on, RP

pin is turned to low in order to return the device to default con-

figuration. When the power transition is occurred, or the power on/off, RP

required to stay low in order to protect data from noise. When returning from Deep
Power-Down, a recovery time of 750 ns is required to allow these circuits to power-
up. When RP

goes low, any current or pending WSM operation(s) are terminated,

and the device is reset. All Status registers return to ready (with all status flags
cleared). After returning, the device is in read array mode.

INPUT

OUTPUT ENABLE:

Gates device data through the output buffers when low. The

outputs float to tri-state off when OE

is high.

INPUT

WRITE ENABLE:

Controls access to the CUI, Data Queue Registers and Address

Queue Latches. WE is active low, and latches both address and data (command or
array) on its rising edge.

/BY

OPEN DRAIN
OUTPUT

READY/BUSY:

Indicates status of the internal WSM. When low, it indicates that the

WSM is busy performing an operation. When the WSM is ready for new operation or
Erase is Suspended, or the device is in deep power-down mode RY

/BY

pin is floated.

BYTE

INPUT

BYTE ENABLE

BYTE

low places device in x8 mode. All data is then input or

output on DQ

- DQ

, and DQ

- DQ

float. Address A

-1

selects between the high

and low byte.

BYTE

high places the device in x16 mode, and turns off the A

-1

input buffer. Address A

, then becomes the lowest order address.

SUPPLY

ERASE/WRITE POWER SUPPLY (5.0 V ±0.5 V):

For erasing memory array blocks

or writing words/bytes into the flash array.

SUPPLY

DEVICE POWER SUPPLY (3.0 V ±0.3 V):

Do not leave any power pins floating.

GND

SUPPLY

GROUND FOR ALL INTERNAL CIRCUITRY:

Do not leave any ground pins floating.

NO CONNECT:

No internal connection to die, lead may be driven or left floating

LH28F400SUB-Z0

4M (512K × 8, 256K × 16) Flash Memory

INTRODUCTION

Sharp's LH28F400SU 4M Flash Memory is a revolu-

tionary architecture which enables the design of truly
mobile, high performance, personal computing and
communication products. With innovative capabilities,
3.3 V low power operation and very high read/write per-
formance, the LH28F400SU is also the ideal choice for
designing embedded mass storage flash memory
systems.

The LH28F400SU's independently lockable 32 sym-

metrical blocked architecture (16K each) extended
cycling, low power operation, very fast write and read
performance and selective block locking provide a highly
flexible memory component suitable for cellular phone,
facsimile, game, PC, printer and handy terminal. The
LH28F400SU's 5.0 V/3.3 V power supply operation
enables the design of memory cards which can be read
in 3.3 V system and written in 5.0 V/3.3 V systems. Its
x8/x16 architecture allows the optimization of memory
to processor interface. The flexible block locking option
enables bundling of executable application software in
a Resident Flash Array or memory card. Manufactured
on Sharp's 0.45 µm ETOXTM process technology, the
LH28F400SU is the most cost-effective, high-density
3.3 V flash memory.

DESCRIPTION

The LH28F400SU is a high performance 4M

(4,194,304 bit) block erasable non-volatile random
access memory organized as either 256K × 16 or
512K × 8. The LH28F400SU includes thirty-two 16K
(16,384) blocks. A chip memory map is shown in
Figure 3.

The implementation of a new architecture, with many

enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.

Among the significant enhancements of the

LH28F400SU:

3 V Read, 5 V Write/Erase Operation
(5 V V

, 3 V V

)

Low Power Capability (2.7 V V

Read)

Improved Write Performance

Dedicated Block Write/Erase Protection

Command-Controlled Memory Protection
Set/Reset Capability

The LH28F400SU will be available in a 49-pin,

.67 mm thick × 8 mm × 8 mm CSP package. This form
factor and pinout allow for very high board layout densi-
ties.

A Command User Interface (CUI) serves as the sys-

tem interface between the microprocessor or
microcontroller and the internal memory operation.

Internal Algorithm Automation allows Byte Writes and

Block Erase operations to be executed using a Two-
Write command sequence to the CUI in the same way
as the LH28F008SA 8M Flash memory.

A Superset of commands have been added to the

basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:

Software Locking of Memory Blocks

Memory Protection Set/Reset Capability

Two-Byte Serial Writes in 8-bit Systems

Erase All Unlocked Blocks

Writing of memory data is performed typically within

20 µs per byte. Writing of memory data is performed
typically within 30 µs per word. A Block Erase operation
erases one of the 32 blocks in typically 0.8 seconds,
independent of the other blocks.

LH28F400SU allows to erase all unlocked blocks. It

is desirable in case of which you have to implement
Erase operation maximum 32 times.

LH28F400SU enables Two-Byte serial Write which

is operated by three times command input. Writing of
memory data is performed typically within 30 µs per
two-byte. This feature can improve 8-bit system write
performance by up to typically 15 µs per byte.

All operations are started by a sequence of Write

commands to the device. Status Register (described in
detail later) and a RY

/BY

output pin provide informa-

tion on the progress of the requested operation.

Same as the LH28F008SA, LH28F400SU requires

an operation to complete before the next operation can
be requested, also it allows to suspend block erase to
read data from any other block, and allow to resume
erase operation.

The LH28F400SU provides user-selectable block

locking to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable OS or
Application Code. Each block has an associated non-
volatile lock-bit which determines the lock status of the
block. In addition, the LH28F400SU has a software con-
trolled master Write Protect circuit which prevents any
modifications to memory blocks whose lock-bits are set.

4M (512K × 8, 256K × 16) Flash Memory

LH28F400SUB-Z0

Figure 3. Memory Map

MEMORY MAP

When the device power-up or RP

turns High, Write

Protect Set/Confirm command must be written. Other-
wise, all lock bits in the device remain being locked,
can't perform the Write to each block and single Block
Erase. Write Protect Set/Confirm command must be
written to reflect the actual lock status. However, when
the device power-on or RP

turns High, Erase All

Unlocked Blocks can be used. If used, Erase is per-
formed with reflecting actual lock status, and after that
Write and Block Erase can be used.

The LH28F400SU contains a Compatible Status

Register (CSR) which is 100% compatible with the
LH28F008SA Flash memory's Status Register. This reg-
ister, when used alone, provides a straightforward
upgrade capability to the LH28F400SU from a
LH28F008SA-based design.

The LH28F400SU incorporates an open drain

/BY

output pin. This feature allows the user to OR-

tie many RY

/BY

pins together in a multiple memory con-

figuration such as a Resident Flash Array.

The LH28F400SU is specified for a maximum

access time of 150 ns (t

ACC

) at 3.3 V operation (3.0 to

3.6 V) over the extended temperature range (-20 to
+85°C). A corresponding maximum access time of
160 ns (t

ACC

) at 2.7 V (-20 to +85°C) is achieved for

reduced power consumption applications.

The LH28F400SU incorporates an Automatic Power

Saving (APS) feature which substantially reduces the
active current when the device is in static mode of
operation (addresses not switching).

In APS mode, the typical I

current is 1 mA at 3.3 V.

A Deep Power-Down mode of operation is invoked

when the RP

(called PWD on the LH28F008SA) pin

transitions low, any current operation is aborted and the
device is put into the deep power down mode. This mode
brings the device power consumption to less than 8 µA,
and provides additional write protection by acting as a
device reset pin during power transitions. When the
power is turned on, RP

pin is turned to low in order to

return the device to default configuration. When the
power transition is occurred, or at the power on/off, RP

is required to stay low in order to protect data from noise.
A recovery time of 750 ns is required from RP

switch-

ing high until outputs are again valid. In the Deep Power-
Down state, the WSM is reset (any current operation
will abort) and the CSR register is cleared.

A CMOS Standby mode of operation is enabled when

transitions high and RP

stays high with all input

control pins at CMOS levels. In this mode, the device
draws an I

standby current of 15 µA.

7C000H

7FFFFH

7BFFFH

78000H

77FFFH

74000H

73FFFH

70000H

6FFFFH

6C000H

6BFFFH

68000H

67FFFH

64000H

63FFFH

60000H

5FFFFH

5C000H

5BFFFH
58000H

57FFFH

54000H

53FFFH

50000H

4FFFFH

4C000H

4BFFFH

48000H

47FFFH

44000H

43FFFH

40000H

3FFFFH

3C000H

3BFFFH

38000H

37FFFH

34000H

33FFFH

30000H

2FFFFH

2C000H

2BFFFH

28000H

27FFFH

24000H

23FFFH

20000H

1FFFFH

1C000H

1BFFFH

18000H

17FFFH

14000H

13FFFH

10000H

0FFFFH

0C000H

0BFFFH

08000H

07FFFH

04000H

03FFFH

00000H

16KB BLOCK

28F400SUB-3

NOTE: In Byte-wide (x8) mode A

-1

is the lowest order address.

In Word-wide (x16) mode A

-1

don't care, address values are

ignored A

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