- 1 -

In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

LH28F800BG-L/BGH-L
(FOR TSOP, CSP)

8 M-bit (512 kB x 16) SmartVoltage

Flash Memories

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

DESCRIPTION

The LH28F800BG-L/BGH-L flash memories with
SmartVoltage technology are high-density, low-cost,
nonvolatile, read/write storage solution for a wide
range of applications. The LH28F800BG-L/BGH-L
can operate at V

= 2.7 V and V

= 2.7 V. Their

low voltage operation capability realizes longer
battery life and suits for cellular phone application.
Their boot, parameter and main-blocked
architecture, flexible voltage and enhanced cycling
capability provide for highly flexible component
suitable for portable terminals and personal
computers. Their enhanced suspend capabilities
provide for an ideal solution for code + data storage
applications. For secure code storage applications,
such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the
LH28F800BG-L/BGH-L offer two levels of protection
: absolute protection with V

at GND, selective

hardware boot block locking. These alternatives
give designers ultimate control of their code security
needs.

FEATURES

· SmartVoltage technology

2.7 V, 3.3 V or 5 V V

2.7 V, 3.3 V, 5 V or 12 V V

· High performance read access time

LH28F800BG-L85/BGH-L85
85 ns (5.0±0.25 V)/90 ns (5.0±0.5 V)/

100 ns (3.3±0.3 V)/120 ns (2.7 to 3.6 V)

LH28F800BG-L12/BGH-L12
120 ns (5.0±0.5 V)/130 ns (3.3±0.3 V)/

150 ns (2.7 to 3.6 V)

· Enhanced automated suspend options

Word write suspend to read
Block erase suspend to word write
Block erase suspend to read

· Enhanced data protection features

Absolute protection with V

= GND

Block erase/word write lockout during power

transitions

Boot blocks protection with WP# = V

· SRAM-compatible write interface
· Optimized array blocking architecture

Two 4 k-word boot blocks
Six 4 k-word parameter blocks
Fifteen 32 k-word main blocks
Top or bottom boot location

· Enhanced cycling capability

100 000 block erase cycles

· Low power management

Deep power-down mode
Automatic power saving mode decreases I

in static mode

· Automated word write and block erase

Command user interface
Status register

· ETOX

V nonvolatile flash technology

· Packages

48-pin TSOP Type I (TSOP048-P-1220)

Normal bend/Reverse bend

48-ball CSP (FBGA048-P-0808)

ETOX is a trademark of Intel Corporation.

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 2 -

PIN CONNECTIONS

GND

CE#

OE#

WP#

WE#

RP#

GND

RY/BY#

(FBGA048-P-0808)

48-BALL CSP

48-PIN TSOP (Type I)

(TSOP048-P-1220)

NC
NC

WE#

RP#

WP#

RY/BY#

NC
GND
DQ

OE#
GND
CE#
A

VERSIONS

OPERATING

PACKAGE

DC CHARACTERISTICS

WRITE PROTECT FUNCTION

TEMPERATURE

deep power-down current (MAX.)

FOR BOOT BLOCKS

LH28F800BG-L

0 to +70°C

48-pin TSOP (I)

10 µA

Controlled by

(FOR TSOP, CSP)

48-ball CSP

WP# and RP# pins

LH28F800BGH-L

40 to +85°C

48-pin TSOP (I)

20 µA

Controlled by

(FOR TSOP, CSP)

48-ball CSP

WP# and RP# pins

LH28F800BG-L

0 to +70°C

44-pin SOP

10 µA

Controlled by RP# pin

(FOR SOP)

COMPARISON TABLE

1 Refer to the datasheet of LH28F800BG-L (FOR SOP).

NOTE :

Reverse bend available on request.

TOP VIEW

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

BLOCK ORGANIZATION

This product features an asymmetrically-blocked
architecture providing system memory integration.
Each erase block can be erased independently of
the others up to 100 000 times. For the address
locations of the blocks, see the memory map in
Fig. 1.

Boot Blocks : The two boot blocks are intended to
replace a dedicated boot PROM in a micro-
processor or microcontroller-based system. The
boot blocks of 4 k words (4 096 words) feature
hardware controllable write-protection to protect the
crucial microprocessor boot code from accidental
modification. The protection of the boot blocks is
controlled using a combination of the V

, RP# and

WP# pins.

Parameter Blocks : The boot block architecture
includes parameter blocks to facilitate storage of
frequently update small parameters that would
normally require an EEPROM. By using software
techniques, the byte-rewrite functionality of
EEPROMs can be emulated. Each boot block
component contains six parameter blocks of 4 k
words (4 096 words) each. The parameter blocks
are not write-protectable.

Main Blocks : The reminder is divided into main
blocks for data or code storage. Each 8 M-bit
device contains fifteen 32 k words (32 768 words)
blocks.

- 3 -

INPUT

BUFFER

OUTPUT

MULTIPLEXER

CE#

RP#

OE#

IDENTIFIER

COMMAND

USER

INTERFACE

WRITE
STATE

MACHINE

PROGRAM/ERASE
VOLTAGE SWITCH

I/O

LOGIC

STATUS

DATA

COMPARATOR

32 k-WORD

MAIN BLOCKS

DECODER

Y GATING

RY/BY#

GND

-A

INPUT

BUFFER

ADDRESS

LATCH

ADDRESS

COUNTER

BOOT BLOCK 0

BOOT BLOCK 1

PARAMETER BLOCK 0

PARAMETER BLOCK 1

PARAMETER BLOCK 2

PARAMETER BLOCK 3

PARAMETER BLOCK 4

PARAMETER BLOCK 5

MAIN BLOCK 0

MAIN BLOCK 1

MAIN BLOCK 13

MAIN BLOCK 14

WP#

WE#

OUTPUT

-DQ

BLOCK DIAGRAM

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 4 -

PIN DESCRIPTION

SYMBOL

TYPE

NAME AND FUNCTION

-A

INPUT

ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses

are internally latched during a write cycle.

DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs

data during memory array, status register and identifier code read cycles. Data pins float

to high-impedance when the chip is deselected or outputs are disabled. Data is

internally latched during a write cycle.

CE#

INPUT

CHIP ENABLE : Activates the device's control logic, input buffers, decoders and sense

amplifiers. CE#-high deselects the device and reduces power consumption to standby

levels.

RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets

internal automation. RP#-high enables normal operation. When driven low, RP# inhibits

write operations which provide data protection during power transitions. Exit from deep

power-down sets the device to read array mode. With RP# = V

, block erase or word

write can operate to all blocks without WP# state. Block erase or word write with V

RP# < V

produce spurious results and should not be attempted.

OE#

INPUT

OUTPUT ENABLE : Gates the device's outputs during a read cycle.

WE#

INPUT

WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are

latched on the rising edge of the WE# pulse.

WP#

INPUT

WRITE PROTECT : Master control for boot blocks locking. When V

, locked boot

blocks cannot be erased and programmed.

READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is

performing an internal operation (block erase or word write). RY/BY#-high indicates that

the WSM is ready for new commands, block erase is suspended, and word write is

inactive, word write is suspended, or the device is in deep power-down mode. RY/BY#

is always active and does not float when the chip is deselected or data outputs are

disabled.

SUPPLY

BLOCK ERASE AND WORD WRITE POWER SUPPLY : For erasing array blocks or

writing words. With V

PPLK

, memory contents cannot be altered. Block erase and

word write with an invalid V

(see Section 6.2.3 "DC CHARACTERISTICS") produce

spurious results and should not be attempted.

DEVICE POWER SUPPLY : Internal detection configures the device for 2.7 V, 3.3 V or

5 V operation. To switch from one voltage to another, ramp V

down to GND and then

ramp V

to the new voltage. Do not float any power pins. With V

LKO

, all write

attempts to the flash memory are inhibited. Device operations at invalid V

voltage

(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should

not be attempted.

GND

SUPPLY

GROUND : Do not float any ground pins.

NO CONNECT : Lead is not internal connected; recommend to be floated.

-DQ

INPUT/

OUTPUT

RP#

INPUT/

RY/BY#

OUTPUT

SUPPLY

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

1 INTRODUCTION

This datasheet contains LH28F800BG-L/BGH-L
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4 and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F800BG-L/
BGH-L flash memories documentation also includes
ordering information which is referenced in
Section 7.

1.1

New Features

Key enhancements of LH28F800BG-L/BGH-L
SmartVoltage flash memories are :

· SmartVoltage Technology
· Enhanced Suspend Capabilities
· Boot Block Architecture

Note following important differences :

· V

PPLK

has been lowered to 1.5 V to support

2.7 V, 3.3 V and 5 V block erase and word
write operations. Designs that switch V

off

during read operations should make sure that
the V

voltage transitions to GND.

· To take advantage of SmartVoltage technology,

allow V

connection to 2.7 V, 3.3 V or 5 V.

1.2

Product Overview

The LH28F800BG-L/BGH-L are high-performance
8 M-bit SmartVoltage flash memories organized as
512 k-word of 16 bits. The 512 k-word of data is
arranged in two 4 k-word boot blocks, six 4 k-word
parameter blocks and fifteen 32 k-word main blocks
which are individually erasable in-system. The
memory map is shown in Fig. 1.

SmartVoltage technology provides a choice of V

and V

combinations, as shown in Table 1, to

meet system performance and power expectations.
2.7 V V

consumes approximately one-fifth the

power of 5 V V

and 3.3 V V

consumes

approximately one-fourth the power of 5 V V

But, 5 V V

provides the highest read

performance. V

at 2.7 V, 3.3 V and 5 V

eliminates the need for a separate 12 V converter,
while V

PP =

12 V maximizes block erase and word

write performance. In addition to flexible erase and
program voltages, the dedicated V

pin gives

complete data protection when V

PPLK

Table 1 V

and V

Voltage Combinations

Offered by SmartVoltage Technology

Internal V

and V

detection circuitry auto-

matically configures the device for optimized read
and write operations.

A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase and word write
operations.

A block erase operation erases one of the device's
32 k-word blocks typically within 0.39 second (5 V
V

, 12 V V

), 4 k-word blocks typically within

0.25 second (5 V V

, 12 V V

) independent of

other blocks. Each block can be independently
erased 100 000 times. Block erase suspend mode
allows system software to suspend block erase to
read data from, or write data to any other block.

Writing memory data is performed in word
increments of the device's 32 k-word blocks
typically within 8.4 µs (5 V V

, 12 V V

), 4 k-

word blocks typically within 17 µs (5 V V

, 12 V

). Word write suspend mode enables the

VOLTAGE

2.7 V

2.7 V, 3.3 V, 5 V, 12 V

3.3 V

3.3 V, 5 V, 12 V

5 V

5 V, 12 V

- 5 -

- 6 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

system to read data from, or write to any other
flash memory array location.

The boot block is located at either the top or the
bottom of the address map in order to
accommodate different micro-processor protect for
boot code location. The hardware-lockable boot
block provides complete code security for the
kernel code required for system initialization.
Locking and unlocking of the boot block is
controlled by WP# and/or RP# (see Section 4.9 for
details). Block erase or word write for boot block
must not be carried out by WP# to low and RP# to
V

The status register indicates when the WSM's block
erase or word write operation is finished.

The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using RY/BY#
minimizes both CPU overhead and system power
consumption. When low, RY/BY# indicates that the
WSM is performing a block erase or word write.
RY/BY#-high indicates that the WSM is ready for a
new command, block erase is suspended (and
word write is inactive), word write is suspended, or
the device is in deep power-down mode.

The access time is 85 ns (t

AVQV

) at the V

supply

voltage range of 4.75 to 5.25 V over the
temperature range, 0 to +70°C (LH28F800BG-L)/
40 to +85°C (LH28F800BGH-L). At 4.5 to 5.5 V
V

, the access time is 90 ns or 120 ns. At lower

voltage, the access time is 100 ns or 130 ns

(3.0 to 3.6 V) and 120 ns or 150 ns (2.7 to 3.6 V).

The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical I

CCR

current is 1 mA at

5 V V

and 3 mA at 2.7 V and 3.3 V V

When CE# and RP# pins are at V

, the I

CMOS standby mode is enabled. When the RP#
pin is at GND, deep power-down mode is enabled
which minimizes power consumption and provides
write protection during reset. A reset time (t

PHQV

) is

required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (t

PHEL

)

from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset
and the status register is cleared.

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 7 -

32 k-Word Main Block

7FFFF

78000
77FFF

6FFFF

70000

68000
67FFF

60000
5FFFF

58000
57FFF

50000
4FFFF

48000
47FFF

40000
3FFFF

38000
37FFF

30000
2FFFF

28000
27FFF

20000
1FFFF

18000
17FFF

10000
0FFFF

08000
07FFF

07000
06FFF

06000
05FFF

05000
04FFF

04000
03FFF

03000
02FFF

02000
01FFF

01000
00FFF

00000

4 k-Word Parameter Block

4 k-Word Boot Block

Bottom Boot

4 k-Word Boot Block

4 k-Word Parameter Block

32 k-Word Main Block

7FFFF

7F000
7EFFF

7DFFF

7E000

7D000
7CFFF

7C000
7BFFF

7B000
7AFFF

7A000
79FFF

79000
78FFF

78000
77FFF

70000
6FFFF

68000
67FFF

60000
5FFFF

58000
57FFF

50000
4FFFF

48000
47FFF

40000
3FFFF

38000
37FFF

30000
2FFFF

28000
27FFF

20000
1FFFF

18000
17FFF

10000
0FFFF

08000
07FFF

00000

32 k-Word Main Block

Top Boot

Fig. 1 Memory Map

BLOCK CONFIGURATION

VERSIONS

Top Boot

LH28F800BG-TL

LH28F800BGH-TL

Bottom Boot

LH28F800BG-BL

LH28F800BGH-BL

NOTES :

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

2 PRINCIPLES OF OPERATION

The LH28F800BG-L/BGH-L SmartVoltage flash
memories include an on-chip WSM to manage
block erase and word write functions. It allows for :
100% TTL-level control inputs, fixed power supplies
during block erasure and word write, and minimal
processor overhead with RAM-like interface timings.

After initial device power-up or return from deep
power-down mode (see Table 2 "Bus Operations"),
the device defaults to read array mode.
Manipulation of external memory control pins allow
array read, standby and output disable operations.

Status register and identifier codes can be
accessed through the CUI independent of the V

voltage. High voltage on V

enables successful

block erasure and word writing. All functions
associated with altering memory contents--block
erase, word write, status and identifier codes--are
accessed via the CUI and verified through the
status register.

Commands are written using standard micro-
processor write timings. The CUI contents serve as
input to the WSM, which controls the block erase
and word write. The internal algorithms are
regulated by the WSM, including pulse repetition,
internal verification and margining of data.
Addresses and data are internally latched during
write cycles. Writing the appropriate command
outputs array data, accesses the identifier codes or
outputs status register data.

Interface software that initiates and polls progress
of block erase and word write can be stored in any
block. This code is copied to and executed from
system RAM during flash memory updates. After
successful completion, reads are again possible via
the Read Array command. Block erase suspend
allows system software to suspend a block erase to
read/write data from/to blocks other than that which
is suspended. Word write suspend allows system

software to suspend a word write to read data from
any other flash memory array location.

2.1

Data Protection

Depending on the application, the system designer
may choose to make the V

power supply

switchable (available only when memory block
erases or word writes are required) or hardwired to
V

PPH1/2/3

. The device accommodates either design

practice and encourages optimization of the
processor-memory interface.

When V

PPLK

, memory contents cannot be

altered. The CUI, with two-step block erase or word
write command sequences, provides protection
from unwanted operations even when high voltage
is applied to V

. All write functions are disabled

when V

is below the write lockout voltage V

LKO

or when RP# is at V

. The device's boot blocks

locking capability for WP# provides additional
protection from inadvertent code or data alteration
by block erase and word write operations.

3 BUS OPERATION

The local CPU reads and writes flash memory in-
system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.

3.1

Read

Information can be read from any block, identifier
codes or status register independent of the V

voltage. RP# can be at either V

or V

The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes or
Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep power-
down mode, the device automatically resets to read
array mode. Five control pins dictate the data flow
in and out of the component : CE#, OE#, WE#,
RP# and WP#. CE# and OE# must be driven
active to obtain data at the outputs. CE# is the

- 8 -

- 9 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

device selection control, and when active enables
the selected memory device. OE# is the data
output (DQ

-DQ

) control and when active drives

the selected memory data onto the I/O bus. WE#
must be at V

and RP# must be at V

or V

Fig. 11 illustrates read cycle.

3.2

Output Disable

With OE# at a logic-high level (V

), the device

outputs are disabled. Output pins (DQ

-DQ

) are

placed in a high-impedance state.

3.3

Standby

CE# at a logic-high level (V

) places the device in

standby mode which substantially reduces device
power consumption. DQ

-DQ

outputs are placed

in a high-impedance state independent of OE#. If
deselected during block erase or word write, the
device continues functioning, and consuming active
power until the operation completes.

3.4

Deep Power-Down

RP# at V

initiates the deep power-down mode.

In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low
for a minimum of 100 ns. Time t

PHQV

is required

after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI is
reset to read array mode and status register is set
to 80H.

During block erase or word write modes, RP#-low
will abort the operation. RY/BY# remains low until
the reset operation is complete. Memory contents
being altered are no longer valid; the data may be
partially erased or written. Time t

PHWL

is required

after RP# goes to logic-high (V

) before another

command can be written.

As with any automated device, it is important to

assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase or
word write modes. If a CPU reset occurs with no
flash memory reset, proper CPU initialization may
not occur because the flash memory may be
providing status information instead of array data.
SHARP's flash memories allow proper CPU
initialization following a system reset through the
use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that resets
the system CPU.

3.5

Read Identifier Codes Operation

The read identifier codes operation outputs the
manufacture code and device code (see Fig. 2).
Using the manufacture and device codes, the
system CPU can automatically match the device
with its proper algorithms.

Fig. 2 Device Identifier Code Memory Map

3.6

Write

Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
V

= V

CC1/2/3/4

and V

= V

PPH1/2/3

, the CUI

additionally controls block erasure and word write.

The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Word Write command requires the
command and address of the location to be written.

7FFFF

00002

00001

00000

Reserved for

Future Implementation

Device Code

Manufacture Code

- 10 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are
active. The address and data needed to execute a
command are latched on the rising edge of WE# or
CE# (whichever goes high first). Standard
microprocessor write timings are used. Fig. 12 and
Fig. 13 illustrate WE# and CE# controlled write
operations.

4 COMMAND DEFINITIONS

When the V

voltage

PPLK

, read operations

from the status register, identifier codes, or blocks
are enabled. Placing V

PPH1/2/3

on V

enables

successful block erase and word write operations.

Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.

Table 2 Bus Operations

MODE

NOTE

RP#

CE#

OE#

WE#

ADDRESS

0-15

RY/BY#

Read

1, 2, 3, 8 V

or V

OUT

Output Disable

or V

High Z

Standby

or V

High Z

Deep Power-Down

High Z

Read Identifier Codes

or V

See Fig. 2

(NOTE 5)

Write

3, 6, 7, 8 V

or V

NOTES :

Refer to Section 6.2.3 "DC CHARACTERISTICS".

When V

PPLK

, memory contents can be read, but

not altered.

X can be V

or V

for control pins and addresses, and

PPLK

or V

PPH1/2/3

for V

. See Section 6.2.3 "DC

CHARACTERISTICS" for V

PPLK

and V

PPH1/2/3

voltages.

RY/BY# is V

when the WSM is executing internal

block erase or word write algorithms. It is V

during

when the WSM is not busy, in block erase suspend

mode (with word write inactive), word write suspend

mode or deep power-down mode.

RP# at GND±0.2 V ensures the lowest deep power-

down current.

See Section 4.2 for read identifier code data.

Command writes involving block erase or word write are

reliably executed when V

= V

PPH1/2/3

and V

CC1/2/3/4

. Block erase or word write with V

< RP# <

produce spurious results and should not be

attempted.

Refer to Table 3 for valid D

during a write operation.

Don't use the timing both OE# and WE# are V

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 11 -

COMMAND

BUS CYCLES

NOTE

FIRST BUS CYCLE

SECOND BUS CYCLE

REQ

Oper

(NOTE 1)

Addr

(NOTE 2)

Data

(NOTE 3)

Oper

(NOTE 1)

Addr

(NOTE 2)

Data

(NOTE 3)

Read Array/Reset

Write

FFH

Read Identifier Codes

Write

90H

Read

Read Status Register

Write

70H

Read

SRD

Clear Status Register

Write

50H

Block Erase

Write

20H

Write

D0H

Word Write

5, 6

Write

40H or 10H

Write

Block Erase and

Write

B0H

Word Write Suspend

Block Erase and

Write

D0H

Word Write Resume

Table 3 Command Definitions

(NOTE 7)

NOTES :

Bus operations are defined in Table 2.

X = Any valid address within the device.

IA = Identifier code address : see Fig. 2.

BA = Address within the block being erased.

WA = Address of memory location to be written.

SRD = Data read from status register. See Table 6 for a

description of the status register bits.

WD = Data to be written at location WA. Data is latched

on the rising edge of WE# or CE# (whichever

goes high first).

ID = Data read from identifier codes.

Following the Read Identifier Codes command, read

operations access manufacture and device codes. See

Section 4.2 for read identifier code data.

If the block is boot block, WP# must be at V

or RP#

must be at V

to enable block erase or word write

operations. Attempts to issue a block erase or word write

to a boot block while WP# is V

or RP# is V

Either 40H or 10H is recognized by the WSM as the

word write setup.

Commands other than those shown above are reserved

by SHARP for future device implementations and should

not be used.

- 12 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

4.1

Read Array Command

Upon initial device power-up and after exit from
deep power-down mode, the device defaults to
read array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase or word write, the device will not
recognize the Read Array command until the WSM
completes its operation unless the WSM is
suspended via an Erase Suspend or Word Write
Suspend command. The Read Array command
functions independently of the V

voltage and

RP# can be V

or V

4.2

Read Identifier Codes Command

The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Fig. 2 retrieve the manufacture and device codes
(see Table 4 for identifier code values). To
terminate the operation, write another valid
command. Like the Read Array command, the
Read Identifier Codes command functions
independently of the V

voltage and RP# can be

or V

. Following the Read Identifier Codes

command, the following information can be read :

Table 4 Identifier Codes

4.3

Read Status Register Command

The status register may be read to determine when
a block erase or word write is complete and
whether the operation completed successfully. It
may be read at any time by writing the Read Status
Register command. After writing this command, all
subsequent read operations output data from the
status register until another valid command is
written. The status register contents are latched on

the falling edge of OE# or CE#, whichever occurs.
OE# or CE# must toggle to V

before further reads

to update the status register latch. The Read Status
Register command functions independently of the
V

voltage. RP# can be V

or V

4.4

Clear Status Register Command

Status register bits SR.5, SR.4, SR.3 or SR.1 are
set to "1"s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 6). By
allowing system software to reset these bits,
several operations (such as cumulatively erasing
multiple blocks or writing several words in
sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.

To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied V

voltage. RP# can

be V

or V

. This command is not functional

during block erase or word write suspend modes.

4.5

Block Erase Command

Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
first written, followed by a block erase confirm.
This command sequence requires appropriate
sequencing and an address within the block to be
erased (erase changes all block data to FFFFH).
Block preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written,
the device automatically outputs status register data
when read (see Fig. 3). The CPU can detect block
erase completion by analyzing the output data of
the RY/BY# pin or status register bit SR.7.

When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error
is detected, the status register should be cleared
before system software attempts corrective actions.

CODE

ADDRESS

DATA

Manufacture Code

00000H

00B0H

Device Code (Top Boot)

00001H

0060H

Device Code (Bottom Boot)

00001H

0062H

- 13 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

The CUI remains in read status register mode until
a new command is issued.

This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to "1". Also,
reliable block erasure can only occur when V

CC1/2/3/4

and V

= V

PPH1/2/3

. In the absence of

this high voltage, block contents are protected
against erasure. If block erase is attempted while
V

PPLK

, SR.3 and SR.5 will be set to "1".

Successful block erase for boot blocks requires that
the corresponding if set, that WP# = V

or RP# =

. If block erase is attempted to boot block when

the corresponding WP# = V

or RP# = V

, SR.1

and SR.5 will be set to "1". Block erase operations
with V

< RP# < V

produce spurious results and

should not be attempted.

4.6

Word Write Command

Word write is executed by a two-cycle command
sequence. Word write setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the word write and write verify algorithms
internally. After the word write sequence is written,
the device automatically outputs status register data
when read (see Fig. 4). The CPU can detect the
completion of the word write event by analyzing the
RY/BY# pin or status register bit SR.7.

When word write is complete, status register bit
SR.4 should be checked. If word write error is
detected, the status register should be cleared. The
internal WSM verify only detects errors for "1"s that
do not successfully write to "0"s. The CUI remains
in read status register mode until it receives another
command.

Reliable word writes can only occur when V

CC1/2/3/4

and V

= V

PPH1/2/3

. In the absence of

this high voltage, memory contents are protected
against word writes. If word write is attempted while
V

PPLK

, status register bits SR.3 and SR.4 will

be set to "1". Successful word write for boot blocks
requires that the corresponding if set, that WP# =
V

or RP# = V

. If word write is attempted to

boot block when the corresponding WP# = V

RP# = V

, SR.1 and SR.4 will be set to "1". Word

write operations with V

< RP# < V

produce

spurious results and should not be attempted.

4.7

Block Erase Suspend Command

The Block Erase Suspend command allows block
erase interruption to read or word write data in
another block of memory. Once the block erase
process starts, writing the Block Erase Suspend
command requests that the WSM suspend the
block erase sequence at a predetermined point in
the algorithm. The device outputs status register
data when read after the Block Erase Suspend
command is written. Polling status register bits
SR.7 and SR.6 can determine when the block
erase operation has been suspended (both will be
set to "1"). RY/BY# will also transition to V

Specification t

WHRH2

defines the block erase

suspend latency.

At this point, a Read Array command can be
written to read data from blocks other than that
which is suspended. A Word Write command
sequence can also be issued during erase suspend
to program data in other blocks. Using the Word
Write Suspend command (see Section 4.8), a
word write operation can also be suspended.
During a word write operation with block erase
suspended, status register bit SR.7 will return to "0"
and the RY/BY# output will transition to V

However, SR.6 will remain "1" to indicate block
erase suspend status.

- 14 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear
and RY/BY# will return to V

. After the Erase

Resume command is written, the device
automatically outputs status register data when
read (see Fig. 5). V

must remain at V

PPH1/2/3

(the same V

level used for block erase) while

block erase is suspended. RP# must also remain at
V

or V

(the same RP# level used for block

erase). WP# must also remain at V

or V

(the

same WP# level used for block erase). Block erase
cannot resume until word write operations initiated
during block erase suspend have completed.

4.8

Word Write Suspend Command

The Word Write Suspend command allows word
write interruption to read data in other flash memory
locations. Once the word write process starts,
writing the Word Write Suspend command requests
that the WSM suspend the word write sequence at
a predetermined point in the algorithm. The device
continues to output status register data when read
after the Word Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can
determine when the word write operation has been
suspended (both will be set to "1"). RY/BY# will
also transition to V

. Specification t

WHRH1

defines

the word write suspend latency.

At this point, a Read Array command can be
written to read data from locations other than that
which is suspended. The only other valid
commands while word write is suspended are Read
Status Register and Word Write Resume. After
Word Write Resume command is written to the
flash memory, the WSM will continue the word
write process. Status register bits SR.2 and SR.7
will automatically clear and RY/BY# will return to
V

. After the Word Write Resume command is

written, the device automatically outputs status
register data when read (see Fig. 6). V

must

remain at V

PPH1/2/3

(the same V

level used for

word write) while in word write suspend mode. RP#
must also remain at V

or V

(the same RP#

level used for word write). WP# must also remain
at V

or V

(the same WP# level used for word

write).

4.9

Block Locking

This Boot Block flash memory architecture features
two hardware-lockable boot blocks so that the
kernel code for the system can be kept secure
while other blocks are programmed or erased as
necessary.

4.9.1 V

= V

FOR COMPLETE PROTECTION

The V

programming voltage can be held low for

complete write protection of all blocks in the flash
device.

4.9.2 WP# = V

FOR BLOCK LOCKING

The lockable blocks are locked when WP# = V

;

any program or erase operation to a locked block
will result in an error, which will be reflected in the
status register. For top configuration, the top two
boot blocks are lockable. For the bottom
configuration, the bottom two boot blocks are
lockable. Unlocked blocks can be programmed or
erased normally (Unless V

is below V

PPLK

4.9.3 BLOCK UNLOCKING

WP# = V

or RP# = V

unlocks all lockable

blocks.

These blocks can now be programmed or erased.

WP# or RP# controls all block locking and V

provides protection against spurious writes. Table 5
defines the write protection methods.

- 15 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

Table 6 Status Register Definition

WSMS

ESS

WWS

VPPS

WWSS

DPS

SR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready

0 = Busy

SR.6 = ERASE SUSPEND STATUS (ESS)

1 = Block Erase Suspended

0 = Block Erase in Progress/Completed

SR.5 = ERASE STATUS (ES)

1 = Error in Block Erase

0 = Successful Block Erase

SR.4 = WORD WRITE STATUS (WWS)

1 = Error in Word Write

0 = Successful Word Write

SR.3 = V

STATUS (VPPS)

1 = V

Low Detect, Operation Abort

0 = V

SR.2 = WORD WRITE SUSPEND STATUS (WWSS)

1 = Word Write Suspended

0 = Word Write in Progress/Completed

SR.1 = DEVICE PROTECT STATUS (DPS)

1 = WP# or RP# Lock Detected, Operation Abort

0 = Unlock

SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)

NOTES :

Check RY/BY# or SR.7 to determine block erase or word

write completion. SR.6-0 are invalid while SR.7 =

If both SR.5 and SR.4 are

s after a block erase attempt, an

improper command sequence was entered.

SR.3 does not provide a continuous indication of V

level.

The WSM interrogates and indicates the V

level only after

Block Erase or Word Write command sequences.

SR.3 is not guaranteed to reports accurate feedback only

when V

PPH1/2/3

The WSM interrogates the WP# and RP# only after Block

Erase or Word Write command sequences. It informs the

system, depending on the attempted operation, if the WP# is

not V

, RP# is not V

SR.0 is reserved for future use and should be masked out

when polling the status register.

OPERATION

RP# WP#

EFFECT

All Blocks Locked.

Block Erase

All Blocks Locked.

> V

PPLK

All Blocks Unlocked.

Word Write

2 Boot Blocks Locked.

All Blocks Unlocked.

Table 5 Write Protection Alternatives

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 16 -

Block Erase

Complete

Start

Write 20H,

Block Address

Write D0H,

Block Address

Read

Status Register

SR.7 =

Full Status

Check if Desired

Repeat for subsequent block erasures.

Full status check can be done after each block erase or after
a sequence of block erasures.

Write FFH after the last block erase operation to place device
in read array mode.

BUS

OPERATION

Write

Read

Standby

COMMAND

Erase Setup

COMMENTS

Data = 20H
Addr = Within Block to be Erased

Data = D0H
Addr = Within Block to be Erased

Status Register Data

Check SR.7
1 = WSM Ready
0 = WSM Busy

SR.3 =

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Range Error

SR.1 =

Device Protect Error

BUS

OPERATION

COMMAND

COMMENTS

Standby

Check SR.1
1 = Device Protect Detect

Check SR.5
1 = Block Erase Error

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command in cases where multiple blocks
are erased before full status is checked.

If error is detected, clear the status register before attempting
retry or other error recovery.

Suspend

Block Erase

Yes

Suspend Block

Erase Loop

Erase

Confirm

Block Erase

Successful

SR.4, 5 =

Command Sequence

Error

SR.5 =

Block Erase

Error

Standby

Check SR.3
1 = V

Error Detect

Standby

Check SR.4, 5
Both 1 = Command Sequence Error

Fig. 3 Automated Block Erase Flowchart

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 17 -

Word Write

Complete

Start

Write 40H or 10H,

Address

Write Word

Data and Address

Read

Status Register

SR.7 =

Full Status

Check if Desired

Repeat for subsequent word writes.

SR full status check can be done after each word write or after
a sequence of word writes.

Write FFH after the last word write operation to place device
in read array mode.

BUS

OPERATION

Write

Read

Standby

COMMAND

Setup

Word Write

COMMENTS

Data = 40H or 10H
Addr = Location to be Written

Data = Data to be Written
Addr = Location to be Written

Status Register Data

Check SR.7
1 = WSM Ready
0 = WSM Busy

SR.3 =

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Range Error

SR.1 =

Device Protect Error

BUS

OPERATION

COMMAND

COMMENTS

Standby

Check SR.1
1 = Device Protect Detect

SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple locations are
written before full status is checked.

If error is detected, clear the status register before attempting
retry or other error recovery.

Suspend

Word Write

Yes

Suspend Word

Write Loop

Word Write

Successful

SR.4 =

Word Write Error

Standby

Check SR.3
1 = V

Error Detect

Standby

Check SR.4
1 = Data Write Error

Fig. 4 Automated Word Write Flowchart

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

5 DESIGN CONSIDERATIONS

5.1

Three-Line Output Control

The device will often be used in large memory
arrays. SHARP provides three control inputs to
accommodate multiple memory connections. Three-
line control provides for :

a. Lowest possible memory power consumption.
b. Complete assurance that data bus contention

will not occur.

To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system's
READ# control line. This assures that only selected
memory devices have active outputs while
deselected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.

5.2

RY/BY#, Block Erase and Word
Write Polling

RY/BY# is a full CMOS output that provides a
hardware method of detecting block erase and
word write completion. It transitions low after block
erase or word write commands and returns to V

when the WSM has finished executing the internal
algorithm.

RY/BY# can be connected to an interrupt input of
the system CPU or controller. It is active at all
times. RY/BY# is also V

when the device is in

block erase suspend (with word write inactive),
word write suspend or deep power-down modes.

5.3

Power Supply Decoupling

Flash memory power switching characteristics
require careful device decoupling. System
designers are interested in three supply current
issues; standby current levels, active current levels

and transient peaks produced by falling and rising
edges of CE# and OE#. Transient current
magnitudes depend on the device outputs'
capacitive and inductive loading. Two-line control
and proper decoupling capacitor selection will
suppress transient voltage peaks. Each device
should have a 0.1 µF ceramic capacitor connected
between its V

and GND and between its V

and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to
package leads. Additionally, for every eight devices,
a 4.7 µF electrolytic capacitor should be placed at
the array's power supply connection between V

and GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.

5.4

Trace on Printed Circuit Boards

Updating flash memories that reside in the target
system requires that the printed circuit board
designers pay attention to the V

power supply

trace. The V

pin supplies the memory cell current

for word writing and block erasing. Use similar trace
widths and layout considerations given to the V

power bus. Adequate V

supply traces and

decoupling will decrease V

voltage spikes and

overshoots.

5.5

, V

, RP# Transitions

Block erase and word write are not guaranteed if
V

falls outside of a valid V

PPH1/2/3

range, V

falls

outside of a valid V

CC1/2/3/4

range, or RP#

. If V

error is detected, status register bit SR.3

is set to "1" along with SR.4 or SR.5, depending on
the attempted operation. If RP# transitions to V

during block erase or word write, RY/BY# will
remain low until the reset operation is complete.
Then, the operation will abort and the device will
enter deep power-down. The aborted operation may
leave data partially altered. Therefore, the command
sequence must be repeated after normal operation
is restored. Device power-off or RP# transitions to
V

clear the status register.

- 20 -

- 21 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

The CUI latches commands issued by system
software and is not altered by V

or CE#

transitions or WSM actions. Its state is read array
mode upon power-up, after exit from deep power-
down or after V

transitions below V

LKO

After block erase or word write, even after V

transitions down to V

PPLK

, the CUI must be placed

in read array mode via the Read Array command if
subsequent access to the memory array is desired.

5.6

Power-Up/Down Protection

The device is designed to offer protection against
accidental block erasure or word writing during
power transitions. Upon power-up, the device is
indifferent as to which power supply (V

or V

)

powers-up first. Internal circuitry resets the CUI to
read array mode at power-up.

A system designer must guard against spurious
writes for V

voltages above V

LKO

when V

active. Since both WE# and CE# must be low for a
command write, driving either to V

will inhibit

writes. The CUI's two-step command sequence
architecture provides added level of protection
against data alteration.

WP# provides additional protection from inadvertent
code or data alteration. The device is disabled
while RP# = V

regardless of its control inputs

state.

5.7

Power Consumption

When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory's nonvolatility
increases usable battery life because data is
retained when system power is removed.

In addition, deep power-down mode ensures
extremely low power consumption even when
system power is applied. For example, portable
computing products and other power sensitive
applications that use an array of devices for solid-
state storage can consume negligible power by
lowering RP# to V

standby or sleep modes. If

access is again needed, the devices can be read
following the t

PHQV

and t

PHWL

wake-up cycles

required after RP# is first raised to V

. See Section

6.2.4 through 6.2.6 "AC CHARACTERISTICS -
READ-ONLY and WRITE OPERATIONS" and
Fig. 11, Fig. 12 and Fig.13 for more information.

- 22 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

6 ELECTRICAL SPECIFICATIONS

6.1

Absolute Maximum Ratings

Operating Temperature

· LH28F800BG-L

During Read, Block Erase and
Word Write ............................. 0 to +70°C

(NOTE 1)

Temperature under Bias............. 10 to +80°C

· LH28F800BGH-L

During Read, Block Erase and
Word Write ........................ 40 to +85°C

(NOTE 2)

Temperature under Bias............. 40 to +85°C

Storage Temperature........................ 65 to +125°C

Voltage On Any Pin

(except V

, V

, and RP#) .... 2.0 to +7.0 V

(NOTE 3)

Supply Voltage................. 2.0 to +7.0 V

(NOTE 3)

Update Voltage during

Block Erase and
Word Write .................. 2.0 to +14.0 V

(NOTE 3, 4)

RP# Voltage ........................ 2.0 to +14.0 V

(NOTE 3, 4)

Output Short Circuit Current............... 100 mA

(NOTE 5)

WARNING : Stressing the device beyond the

Absolute Maximum Ratings" may cause

permanent damage. These are stress ratings only.
Operation beyond the "Operating Conditions" is not
recommended and extended exposure beyond the
"Operating Conditions" may affect device reliability.

NOTES :

Operating temperature is for commercial product defined

by this specification.

Operating temperature is for extended temperature

product defined by this specification.

All specified voltages are with respect to GND. Minimum

DC voltage is 0.5 V on input/output pins and 0.2 V on

and V

pins. During transitions, this level may

undershoot to 2.0 V for periods < 20 ns. Maximum DC

voltage on input/output pins and V

is V

+0.5 V

which, during transitions, may overshoot to V

+2.0 V

for periods < 20 ns.

Maximum DC voltage on V

and RP# may overshoot

to +14.0 V for periods < 20 ns.

Output shorted for no more than one second. No more

than one output shorted at a time.

NOTICE : The specifications are subject to
change without notice. Verify with your local
SHARP sales office that you have the latest
datasheet before finalizing a design.

SYMBOL

PARAMETER

NOTE

MIN.

MAX.

UNIT

VERSIONS

Operating Temperature

+70

°C

LH28F800BG-L

+85

°C

LH28F800BGH-L

CC1

Supply Voltage (2.7 to 3.6 V)

2.7

3.6

CC2

Supply Voltage (3.3±0.3 V)

3.0

3.6

CC3

Supply Voltage (5.0±0.25 V)

4.75

5.25

LH28F800BG-L85/BGH-L85

CC4

Supply Voltage (5.0±0.5 V)

4.50

5.50

6.2

Operating Conditions

NOTE :

Test condition : Ambient temperature

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 23 -

6.2.2 AC INPUT/OUTPUT TEST CONDITIONS

TEST POINTS

INPUT

OUTPUT

1.35

2.7

0.0

Fig. 7 Transient Input/Output Reference Waveform for V

= 2.7 to 3.6 V

1.5

3.0

0.0

TEST POINTS

INPUT

OUTPUT

Fig. 8 Transient Input/Output Reference Waveform for V

= 3.3±0.3 V and

= 5.0±0.25 V (High Speed Testing Configuration)

AC test inputs are driven at 2.7 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output

timing ends, at 1.35 V. Input rise and fall times (10% to 90%) < 10 ns.

AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output

timing ends, at 1.5 V. Input rise and fall times (10% to 90%) < 10 ns.

2.0

0.8

2.0

0.8

2.4

0.45

TEST POINTS

INPUT

OUTPUT

Fig. 9 Transient Input/Output Reference Waveform for

= 5.0±0.5 V (Standard Testing Configuration)

AC test inputs are driven at V

(2.4 V

TTL

) for a Logic "1" and V

(0.45 V

TTL

) for a Logic "0". Input timing

begins at V

(2.0 V

TTL

) and V

(0.8 V

TTL

). Output timing ends at V

and V

. Input rise and fall times (10% to

90%) < 10 ns.

NOTE :

Sampled, not 100% tested.

SYMBOL

PARAMETER

TYP.

MAX.

UNIT

CONDITION

Input Capacitance

= 0.0 V

OUT

Output Capacitance

OUT

= 0.0 V

6.2.1 CAPACITANCE

(NOTE 1)

= +25

C, f = 1 MHz

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 25 -

6.2.3 DC CHARACTERISTICS

SYMBOL

PARAMETER

NOTE

= 2.7 to 3.6 V V

= 5.0±0.5 V

UNIT

TEST

TYP.

MAX.

TYP.

MAX.

CONDITIONS

Input Load Current

±0.5

±1

µA

= V

Max.

= V

or GND

Output Leakage Current

±0.5

±10

µA

= V

Max.

OUT

= V

or GND

CMOS Inputs

100

µA

= V

Max.

CCS

Standby Current

1, 3, 6

CE# = RP# = V

±0.2 V

TTL Inputs

0.2

0.4

= V

Max.

CE# = RP# = V

CCD

Deep Power- LH28F800BG-L

µA

RP# = GND±0.2 V

Down Current

LH28F800BGH-L

OUT

(RY/BY#) = 0 mA

CMOS Inputs

= V

Max.

CE# = GND

f = 5 MHz (3.3 V, 2.7 V),

8 MHz (5 V)

CCR

Read Current

1, 5, 6

OUT

= 0 mA

TTL Inputs

= V

Max.

CE# = GND

f = 5 MHz (3.3 V, 2.7 V),

8 MHz (5 V)

OUT

= 0 mA

= 2.7 to 3.6 V

CCW

Word Write Current

1, 7

= 5.0±0.5 V

= 12.0±0.6 V

= 2.7 to 3.6 V

CCE

Block Erase Current

1, 7

= 5.0±0.5 V

= 12.0±0.6 V

CCWS

Word Write or Block

1, 2

CE# = V

CCES

Erase Suspend Current

PPS

Standby or Read Current

±2

±15

±2

±15

µA

PPR

200

µA

> V

PPD

Deep Power-Down

0.1

µA

RP# = GND±0.2 V

Current

= 2.7 to 3.6 V

PPW

Word Write Current

1, 7

= 5.0±0.5 V

= 12.0±0.6 V

= 2.7 to 3.6 V

PPE

Block Erase Current

1, 7

= 5.0±0.5 V

= 12.0±0.6 V

PPWS

Word Write or Block

200

µA

= V

PPH1/2/3

PPES

Erase Suspend Current

- 26 -

SYMBOL

PARAMETER

NOTE

= 2.7 to 3.6 V V

= 5.0±0.5 V

UNIT

TEST

MIN.

MAX.

MIN.

MAX.

CONDITIONS

Input Low Voltage

0.5

0.8

0.5

0.8

Input High Voltage

2.0

+0.5

= V

Min.

Output Low Voltage

3, 7

0.4

0.45

= 5.8 mA (5 V)

= 2.0 mA (3.3 V, 2.7 V)

Output High Voltage

= V

Min.

OH1

(TTL)

3, 7

2.4

= 2.5 mA (5 V)

= 2.0 mA (3.3 V, 2.7 V)

0.85

= V

Min.

OH2

Output High Voltage

3, 7

= 2.5 mA

(CMOS)

= V

Min.

0.4

= 100 µA

PPLK

Lockout Voltage during

4, 7

1.5

Normal Operations

PPH1

Voltage during Word Write

2.7

3.6

or Block Erase Operations

PPH2

Voltage during Word Write

4.5

5.5

4.5

5.5

or Block Erase Operations

PPH3

Voltage during Word Write

11.4

12.6

11.4

12.6

or Block Erase Operations

LKO

Lockout Voltage

2.0

RP# Unlock Voltage

8, 9

11.4

12.6

11.4

12.6

Unavailable WP#

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

6.2.3 DC CHARACTERISTICS (contd.)

NOTES :

All currents are in RMS unless otherwise noted. Typical

values at nominal V

voltage and T

= +25°C. These

currents are valid for all product versions (packages and

speeds).

CCWS

and I

CCES

are specified with the device de-

selected. If reading or word writing in erase suspend

mode, the device's current draw is the sum of I

CCWS

CCES

and I

CCR

or I

CCW

, respectively.

Includes RY/BY#.

Block erases and word writes are inhibited when V

PPLK

, and not guaranteed in the range between V

PPLK

(max.) and V

PPH1

(min.), between V

PPH1

(max.) and

PPH2

(min.), between V

PPH2

(max.) and V

PPH3

(min.),

and above V

PPH3

(max.).

Automatic Power Saving (APS) reduces typical I

CCR

1 mA at 5 V V

and 3 mA at 2.7 V and 3.3 V V

static operation.

CMOS inputs are either V

±0.2 V or GND±0.2 V. TTL

inputs are either V

or V

Sampled, not 100% tested.

Boot block erases and word writes are inhibited when

the corresponding RP# = V

or WP# = V

. Block erase

and word write operations are not guaranteed with V

RP# < V

and should not be attempted.

RP# connection to a V

supply is allowed for a

maximum cumulative period of 80 hours.

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 27 -

6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS

(NOTE 1)

= 2.7 to 3.6 V, T

= 0 to +70

C or 40 to +85

VERSIONS

LH28F800BG-L85

LH28F800BG-L12

LH28F800BGH-L85

LH28F800BGH-L12 UNIT

SYMBOL

PARAMETER

NOTE

MIN.

MAX.

MIN.

MAX.

AVAV

Read Cycle Time

120

150

AVQV

Address to Output Delay

120

150

ELQV

CE# to Output Delay

120

150

PHQV

RP# High to Output Delay

600

GLQV

OE# to Output Delay

ELQX

CE# to Output in Low Z

EHQZ

CE# High to Output in High Z

GLQX

OE# to Output in Low Z

GHQZ

OE# High to Output in High Z

Output Hold from Address, CE# or

OE# Change, Whichever Occurs First

VERSIONS

LH28F800BG-L85

LH28F800BG-L12

LH28F800BGH-L85

LH28F800BGH-L12 UNIT

SYMBOL

PARAMETER

NOTE

MIN.

MAX.

MIN.

MAX.

AVAV

Read Cycle Time

100

130

AVQV

Address to Output Delay

100

130

ELQV

CE# to Output Delay

100

130

PHQV

RP# High to Output Delay

600

GLQV

OE# to Output Delay

ELQX

CE# to Output in Low Z

EHQZ

CE# High to Output in High Z

GLQX

OE# to Output in Low Z

GHQZ

OE# High to Output in High Z

Output Hold from Address, CE# or

OE# Change, Whichever Occurs First

NOTES :

See AC Input/Output Reference Waveform (Fig. 7 through Fig. 9) for maximum allowable input slew rate.

OE# may be delayed up to t

ELQV

-t

GLQV

after the falling edge of CE# without impact on t

ELQV

Sampled, not 100% tested.

· V

= 3.3±0.3 V, T

= 0 to +70°C or 40 to +85

- 28 -

SYMBOL

PARAMETER

NOTE

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

AVAV

Read Cycle Time

120

AVQV

Address to Output Delay

120

ELQV

CE# to Output Delay

120

PHQV

RP# High to Output Delay

400

GLQV

OE# to Output Delay

ELQX

CE# to Output in Low Z

EHQZ

CE# High to Output in High Z

GLQX

OE# to Output in Low Z

GHQZ

OE# High to Output in High Z

Output Hold from Address,

CE# or OE# Change,

Whichever Occurs First

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

NOTES :

See AC Input/Output Reference Waveform (Fig. 7

through Fig. 9) for maximum allowable input slew rate.

OE# may be delayed up to t

ELQV

-t

GLQV

after the falling

edge of CE# without impact on t

ELQV

Sampled, not 100% tested.

See Fig. 8 "Transient Input/Output Reference

Waveform"

and

Fig. 10 "Transient Equivalent Testing

Load Circuit" (High Speed Configuration) for testing

characteristics.

See Fig. 9 "Transient Input/Output Reference

Waveform" and

Fig. 10 "Transient Equivalent Testing

Load Circuit" (Standard Configuration) for testing

characteristics.

VERSIONS

±0.25 V

±0.5 V

(NOTE 4)

LH28F800BG-L85

LH28F800BGH-L85

(NOTE 5)

LH28F800BG-L12

LH28F800BGH-L12

(NOTE 5)

LH28F800BG-L85

LH28F800BGH-L85

UNIT

6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS (contd.)

(NOTE 1)

· V

= 5.0±0.25 V, 5.0±0.5 V, T

= 0 to +70°C or 40 to +85

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 30 -

6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS

(NOTE 1)

= 2.7 to 3.6 V, T

= 0 to +70

C or 40 to +85

VERSIONS

LH28F800BG-L85

LH28F800BG-L12

LH28F800BGH-L85

LH28F800BGH-L12 UNIT

SYMBOL

PARAMETER

NOTE

MIN.

MAX.

MIN.

MAX.

AVAV

Write Cycle Time

120

150

PHWL

RP# High Recovery to WE# Going Low

µs

ELWL

CE# Setup to WE# Going Low

WLWH

WE# Pulse Width

PHHWH

RP# V

Setup to WE# Going High

100

SHWH

WP# V

Setup to WE# Going High

100

VPWH

Setup to WE# Going High

100

AVWH

Address Setup to WE# Going High

DVWH

Data Setup to WE# Going High

WHDX

Data Hold from WE# High

WHAX

Address Hold from WE# High

WHEH

CE# Hold from WE# High

WHWL

WE# Pulse Width High

WHRL

WE# High to RY/BY# Going Low

100

WHGL

Write Recovery before Read

QVVL

Hold from Valid SRD, RY/BY# High

2, 4

QVPH

RP# V

Hold from Valid SRD, RY/BY# High

2, 4

QVSL

WP# V

Hold from Valid SRD, RY/BY# High

2, 4

NOTES :

Read timing characteristics during block erase and word

write operations are the same as during read-only

operations. Refer to Section 6.2.4 "AC CHARAC-

TERISTICS" for read-only operations.

Sampled, not 100% tested.

Refer to Table 3 for valid A

and D

for block erase or

word write.

should be held at V

PPH1/2/3

(and if necessary RP#

should be held at V

) until determination of block erase

or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,

SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).

- 31 -

VERSIONS

LH28F800BG-L85

LH28F800BG-L12

LH28F800BGH-L85

LH28F800BGH-L12 UNIT

SYMBOL

PARAMETER

NOTE

MIN.

MAX.

MIN.

MAX.

AVAV

Write Cycle Time

100

130

PHWL

RP# High Recovery to WE# Going Low

µs

ELWL

CE# Setup to WE# Going Low

WLWH

WE# Pulse Width

PHHWH

RP# V

Setup to WE# Going High

100

SHWH

WP# V

Setup to WE# Going High

100

VPWH

Setup to WE# Going High

100

AVWH

Address Setup to WE# Going High

DVWH

Data Setup to WE# Going High

WHDX

Data Hold from WE# High

WHAX

Address Hold from WE# High

WHEH

CE# Hold from WE# High

WHWL

WE# Pulse Width High

WHRL

WE# High to RY/BY# Going Low

100

WHGL

Write Recovery before Read

QVVL

Hold from Valid SRD, RY/BY# High

2, 4

QVPH

RP# V

Hold from Valid SRD, RY/BY# High

2, 4

QVSL

WP# V

Hold from Valid SRD, RY/BY# High

2, 4

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS (contd.)

(NOTE 1)

· V

= 3.3±0.3 V, T

= 0 to +70°C or 40 to +85

NOTES :

Read timing characteristics during block erase and word

write operations are the same as during read-only

operations. Refer to Section 6.2.4 "AC CHARAC-

TERISTICS" for read-only operations.

Sampled, not 100% tested.

Refer to Table 3 for valid A

and D

for block erase or

word write.

should be held at V

PPH1/2/3

(and if necessary RP#

should be held at V

) until determination of block erase

or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,

SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 32 -

NOTES :

Read timing characteristics during block erase and word

write operations are the same as during read-only

operations. Refer to Section 6.2.4 "AC CHARAC-

TERISTICS" for read-only operations.

Sampled, not 100% tested.

Refer to Table 3 for valid A

and D

for block erase or

word write.

should be held at V

PPH1/2/3

(and if necessary RP#

should be held at V

) until determination of block erase

or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,

SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).

See Fig. 8 "Transient Input/Output Reference

Waveform" and

Fig. 10 "Transient Equivalent Testing

Load Circuit" (High Seed Configuration) for testing

characteristics.

See Fig. 9 "Transient Input/Output Reference

Waveform" and

Fig. 10 "Transient Equivalent Testing

Load Circuit" (Standard Configuration) for testing

characteristics.

SYMBOL

PARAMETER

NOTE

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

AVAV

Write Cycle Time

120

PHWL

RP# High Recovery to WE#

µs

Going Low

ELWL

CE# Setup to WE# Going Low

WLWH

WE# Pulse Width

PHHWH

RP# V

Setup to WE# Going High

100

SHWH

WP# V

Setup to WE# Going High

100

VPWH

Setup to WE# Going High

100

AVWH

Address Setup to WE# Going High

DVWH

Data Setup to WE# Going High

WHDX

Data Hold from WE# High

WHAX

Address Hold from WE# High

WHEH

CE# Hold from WE# High

WHWL

WE# Pulse Width High

WHRL

WE# High to RY/BY# Going Low

WHGL

Write Recovery before Read

QVVL

Hold from Valid SRD,

2, 4

RY/BY# High

QVPH

RP# V

Hold from Valid SRD,

2, 4

RY/BY# High

QVSL

WP# V

Hold from Valid SRD,

2, 4

RY/BY# High

VERSIONS

±0.25 V

±0.5 V

(NOTE 5)

LH28F800BG-L85

LH28F800BGH-L85

(NOTE 6)

LH28F800BG-L12

LH28F800BGH-L12

(NOTE 6)

LH28F800BG-L85

LH28F800BGH-L85

UNIT

6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS (contd.)

(NOTE 1)

· V

= 5.0±0.25 V, 5.0±0.5 V, T

= 0 to +70°C or 40 to +85

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 33 -

(NOTE 1) (NOTE 2)

(NOTE 3)

(NOTE 4)

(NOTE 5)

(NOTE 6)

PPLK

PPH1/2/3

ADDRESSES (A)

CE# (E)

OE# (G)

WE# (W)

DATA (D/Q)

RP# (P)

(V)

RY/BY# (R)

AVAV

AVWH

ELWL

WHEH

WHGL

WHWL

WHQV1/2/3/4

WLWH

DVWH

WHDX

Valid

SRD

PHWL

WHRL

VPWH

QVVL

High Z

WP# (S)

PHHWH

QVPH

SHWH

QVSL

WHAX

NOTES :

power-up and standby.

Write block erase or word write setup.

Write block erase confirm or valid address and data.

Automated erase or program delay.

Read status register data.

Write Read Array command.

Fig. 12 AC Waveform for WE#-Controlled Write Operations

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 34 -

6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES

(NOTE 1)

· V

= 2.7 to 3.6 V, T

= 0 to +70°C or 40 to +85

VERSIONS

LH28F800BG-L85

LH28F800BG-L12

LH28F800BGH-L85

LH28F800BGH-L12 UNIT

SYMBOL

PARAMETER

NOTE

MIN.

MAX.

MIN.

MAX.

AVAV

Write Cycle Time

120

150

PHEL

RP# High Recovery to CE# Going Low

µs

WLEL

WE# Setup to CE# Going Low

ELEH

CE# Pulse Width

PHHEH

RP# V

Setup to CE# Going High

100

SHEH

WP# V

Setup to CE# Going High

100

VPEH

Setup to CE# Going High

100

AVEH

Address Setup to CE# Going High

DVEH

Data Setup to CE# Going High

EHDX

Data Hold from CE# High

EHAX

Address Hold from CE# High

EHWH

WE# Hold from CE# High

EHEL

CE# Pulse Width High

EHRL

CE# High to RY/BY# Going Low

100

EHGL

Write Recovery before Read

QVVL

Hold from Valid SRD, RY/BY# High

2, 4

QVPH

RP# V

Hold from Valid SRD, RY/BY# High

2, 4

QVSL

WP# V

Hold from Valid SRD, RY/BY# High

2, 4

NOTES :

In systems where CE# defines the write pulse width

(within a longer WE# timing waveform), all setup, hold,

and inactive WE# times should be measured relative to

the CE# waveform.

Sampled, not 100% tested.

Refer to Table 3 for valid A

and D

for block erase or

word write.

should be held at V

PPH1/2/3

(and if necessary RP#

should be held at V

) until determination of block erase

or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,

SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 35 -

6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES (contd.)

(NOTE 1)

· V

= 3.3±0.3 V, T

= 0 to +70°C or 40 to +85

VERSIONS

LH28F800BG-L85

LH28F800BG-L12

LH28F800BGH-L85

LH28F800BGH-L12 UNIT

SYMBOL

PARAMETER

NOTE

MIN.

MAX.

MIN.

MAX.

AVAV

Write Cycle Time

100

130

PHEL

RP# High Recovery to CE# Going Low

µs

WLEL

WE# Setup to CE# Going Low

ELEH

CE# Pulse Width

PHHEH

RP# V

Setup to CE# Going High

100

SHEH

WP# V

Setup to CE# Going High

100

VPEH

Setup to CE# Going High

100

AVEH

Address Setup to CE# Going High

DVEH

Data Setup to CE# Going High

EHDX

Data Hold from CE# High

EHAX

Address Hold from CE# High

EHWH

WE# Hold from CE# High

EHEL

CE# Pulse Width High

EHRL

CE# High to RY/BY# Going Low

100

EHGL

Write Recovery before Read

QVVL

Hold from Valid SRD, RY/BY# High

2, 4

QVPH

RP# V

Hold from Valid SRD, RY/BY# High

2, 4

QVSL

WP# V

Hold from Valid SRD, RY/BY# High

2, 4

NOTES :

In systems where CE# defines the write pulse width

(within a longer WE# timing waveform), all setup, hold,

and inactive WE# times should be measured relative to

the CE# waveform.

Sampled, not 100% tested.

Refer to Table 3 for valid A

and D

for block erase or

word write.

should be held at V

PPH1/2/3

(and if necessary RP#

should be held at V

) until determination of block erase

or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,

SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 36 -

SYMBOL

PARAMETER

NOTE

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

AVAV

Write Cycle Time

120

PHEL

RP# High Recovery to CE#

µs

Going Low

WLEL

WE# Setup to CE# Going Low

ELEH

CE# Pulse Width

PHHEH

RP# V

Setup to CE# Going High

100

SHEH

WP# V

Setup to CE# Going High

100

VPEH

Setup to CE# Going High

100

AVEH

Address Setup to CE# Going High

DVEH

Data Setup to CE# Going High

EHDX

Data Hold from CE# High

EHAX

Address Hold from CE# High

EHWH

WE# Hold from CE# High

EHEL

CE# Pulse Width High

EHRL

CE# High to RY/BY# Going Low

EHGL

Write Recovery before Read

QVVL

Hold from Valid SRD,

2, 4

RY/BY# High

QVPH

RP# V

Hold from Valid SRD,

2, 4

RY/BY# High

QVSL

WP# V

Hold from Valid SRD,

2, 4

RY/BY# High

VERSIONS

±0.25 V

±0.5 V

(NOTE 5)

LH28F800BG-L85

LH28F800BGH-L85

(NOTE 6)

LH28F800BG-L12

LH28F800BGH-L12

(NOTE 6)

LH28F800BG-L85

LH28F800BGH-L85

UNIT

NOTES :

In systems where CE# defines the write pulse width

(within a longer WE# timing waveform), all setup, hold,

and inactive WE# times should be measured relative to

the CE# waveform.

Sampled, not 100% tested.

Refer to Table 3 for valid A

and D

for block erase or

word write.

should be held at V

PPH1/2/3

(and if necessary RP#

should be held at V

) until determination of block erase

or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,

SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).

See Fig. 8 "Transient Input/Output Reference

Waveform" and

Fig. 10 "Transient Equivalent Testing

Load Circuit" (High Seed Configuration) for testing

characteristics.

See Fig. 9 "Transient Input/Output Reference

Waveform" and

Fig. 10 "Transient Equivalent Testing

Load Circuit" (Standard Configuration) for testing

characteristics.

6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES (contd.)

(NOTE 1)

· V

= 5.0±0.25 V, 5.0±0.5 V, T

= 0 to +70°C or 40 to +85

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 37 -

PPLK

PPH1/2/3

ADDRESSES (A)

WE# (W)

OE# (G)

CE# (E)

DATA (D/Q)

RP# (P)

(V)

RY/BY# (R)

WP# (S)

AVAV

AVEH

WLEL

EHWH

EHGL

EHEL

EHQV1/2/3/4

Valid

SRD

PHEL

EHRL

VPEH

QVVL

High Z

PHHEH

QVPH

SHEH

EHAX

ELEH

DVEH

EHDX

QVSL

(NOTE 1) (NOTE 2)

(NOTE 3)

(NOTE 4)

(NOTE 5)

(NOTE 6)

NOTES :

power-up and standby.

Write block erase or word write setup.

Write block erase confirm or valid address and data.

Automated erase or program delay.

Read status register data.

Write Read Array command.

Fig. 13 AC Waveform for CE#-Controlled Write Operations

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 38 -

6.2.7 RESET OPERATIONS

RP# (P)

RY/BY# (R)

RP# (P)

2.7 V/3.3 V/5 V

RP# (P)

(A) Reset During Read Array Mode

(B) Reset During Block Erase or Word Write

PLPH

PLRH

PLPH

235VPH

Fig. 14 AC Waveform for Reset Operation

Reset AC Specifications

(NOTE 1)

NOTES :

These specifications are valid for all product versions

(packages and speeds).

If RP# is asserted while a block erase or word write

operation is not executing, the reset will complete within

100 ns.

A reset time, t

PHQV

, is required from the latter of RY/BY#

or RP# going high until outputs are valid.

When the device power-up, holding RP#-low minimum

100 ns is required after V

has been in predefined

range and also has been in stable there.

= 2.7 to 3.6 V

= 3.3±0.3 V

= 5.0±0.5 V

SYMBOL

PARAMETER

NOTE

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

UNIT

RP# Pulse Low Time

PLPH

(If RP# is tied to V

, this

100

specification is not applicable)

PLRH

RP# Low to Reset during

2, 3

µs

Block Erase or Word Write
V

2.7 V to RP# High

235VPH

3.0 V to RP# High

100

4.5 V to RP# High

- 39 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

6.2.8 BLOCK ERASE AND WORD WRITE PERFORMANCE

(NOTE 3, 4)

· V

= 2.7 to 3.6 V, T

= 0 to +70°C or 40 to +85

= 2.7 to 3.6 V

= 5.0±0.5 V

= 12.0±0.6 V

SYMBOL

PARAMETER

NOTE

MIN. TYP.

(NOTE 1)

MAX.

MIN. TYP.

(NOTE 1)

MAX.

MIN. TYP.

(NOTE 1)

MAX.

UNIT

32 k-Word

44.6

17.7

12.6

µs

WHQV1

Word Write Block

EHQV1

Time

4 k-Word

45.9

26.1

24.5

µs

Block
32 k-Word

1.46

0.58

0.42

Block Write Block
Time

4 k-Word

0.19

0.11

Block
32 k-Word

1.14

0.61

0.51

WHQV2

Block Erase Block

EHQV2

Time

4 k-Word

0.38

0.32

0.31

Block

WHRH1

Word Write Suspend

µs

EHRH1

Latency Time to Read

WHRH2

Erase Suspend Latency

µs

EHRH2

Time to Read

· V

= 3.3±0.3 V, T

= 0 to +70°C or 40 to +85

NOTES :

Typical values measured at T

= +25°C and nominal

voltages. Subject to change based on device

characterization.

Excludes system-level overhead.

These performance numbers are valid for all speed

versions.

Sampled, not 100% tested.

= 3.3±0.3 V

= 5.0±0.5 V

= 12.0±0.6 V

SYMBOL

PARAMETER

NOTE

MIN. TYP.

(NOTE 1)

MAX.

MIN. TYP.

(NOTE 1)

MAX.

MIN. TYP.

(NOTE 1)

MAX.

UNIT

32 k-Word

17.3

12.3

µs

WHQV1

Word Write Block

EHQV1

Time

4 k-Word

25.6

µs

Block
32 k-Word

1.44

0.57

0.41

Block Write Block
Time

4 k-Word

0.19

0.11

0.1

Block
32 k-Word

1.11

0.59

0.5

WHQV2

Block Erase Block

EHQV2

Time

4 k-Word

0.37

0.31

0.3

Block

WHRH1

Word Write Suspend

µs

EHRH1

Latency Time to Read

WHRH2

Erase Suspend Latency

16.2

9.6

µs

EHRH2

Time to Read

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 40 -

NOTES :

Typical values measured at T

= +25°C and nominal

voltages. Subject to change based on device

characterization.

Excludes system-level overhead.

These performance numbers are valid for all speed

versions.

Sampled, not 100% tested.

= 5.0±0.5 V

= 12.0±0.6 V

SYMBOL

PARAMETER

NOTE

MIN. TYP.

(NOTE 1)

MAX.

MIN. TYP.

(NOTE 1)

MAX.

UNIT

WHQV1

Word Write Time

32 k-Word Block

12.2

8.4

µs

EHQV1

4 k-Word Block

18.3

µs

Block Write Time

32 k-Word Block

0.4

0.28

4 k-Word Block

0.08

0.07

WHQV2

Block Erase Time

32 k-Word Block

0.46

0.39

EHQV2

4 k-Word Block

0.26

0.25

WHRH1

Word Write Suspend Latency Time to Read

µs

EHRH1

WHRH2

Erase Suspend Latency Time to Read

9.6

µs

EHRH2

6.2.8 BLOCK ERASE AND WORD WRITE PERFORMANCE (contd.)

(NOTE 3, 4)

· V

= 5.0 V±0.25 V, 5.0±0.5 V, T

= 0 to +70°C or 40 to +85

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 41 -

7 ORDERING INFORMATION

L H 2 8 F 8 0 0 B G (H) E

L 8 5

Device Density
800 = 8 M-bit

Access Speed (ns)
85 : 85 ns (5.0

0.25 V), 90 ns (5.0

0.5 V)

100 ns (3.3

0.3 V), 120 ns (2.7 to 3.6 V)

12 : 120 ns (5.0

0.5 V), 130 ns (3.3

0.3 V),

150 ns (2.7 to 3.6 V)

Package
E = 48-pin TSOP (I) (TSOP048-P-1220) Normal bend
R = 48-pin TSOP (I) (TSOP048-P-1220) Reverse bend
B = 48-ball CSP (FBGA048-P-0808)

Architecture
B = Boot Block

Power Supply Type
G = SmartVoltage Technology

Operating Temperature

Blank = 0 to +70

H = 40 to +85

Product line designator for all SHARP Flash products

Block Locate Option
T = Top Boot
B = Bottom Boot

VALID OPERATIONAL COMBINATIONS

= 2.7 to 3.6 V

= 3.3±0.3 V

= 5.0±0.5 V

= 5.0±0.25 V

OPTION

ORDER CODE

50 pF load,

100 pF load,

30 pF load,

1.35 V I/O Levels

1.5 V I/O Levels

TTL I/O Levels

1.5 V I/O Levels

LH28F800BGXX-XL85

120 ns

100 ns

90 ns

85 ns

LH28F800BGXX-XL12

150 ns

130 ns

120 ns

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LH28F800BGEBL12

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LH28F800BGEBL12