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LH51BV1000J
CMOS 1M (128K
8) Static Ram
FEATURES
Access time: 70 ns (MAX.)
Current consumption:
Operating: 30 mA (MAX.)
5 mA (MAX.) (t
RC
, t
WC
= 1
s)
Standby: 60
A (MAX.)
Data Retention:
1.0
A (MAX.) (V
CCDR
= 3 V, T
A
= 25
C)
Single power supply: 2.7 V to 3.6 V
Operating temperature: -25
C to +85
C
Fully-static operation
Three-state output
Not designed or rated as radiation
hardened
Package: 32-pin 6
10 mm CSP
N-type bulk silicon
DESCRIPTION
The LH51BV1000JY is a static RAM organized as
131,072
8 bits which provides low power standby
mode. It is fabricated using silicon-gate CMOS process
technology.
PIN CONNECTIONS
A
2
A
3
A
1
A
4
NC
A
5
A
6
A
12
A
14
A
15
A
8
A
9
A
11
A
13
CE
2
WE
V
CC
A
16
A
7
A
0
GND
I/O
7
I/O
8
I/O
4
I/O
1
I/O
2
I/O
5
I/O
3
I/O
6
A
10
OE
CE
1
1
A
B
C
D
E
F
2
3
4
5
8
6
7
51BV1000-1
Figure 1. Pin Connections for CSP Package
1
TRUTH TABLE
CE
1
CE
2
WE
OE
MODE
I/O
1
I/O
8
SUPPLY CURRENT
H
Standby
High impedance
Standby (I
SB
)
L
Standby
High impedance
Standyby (I
SB
)
L
H
L
Write
Data input
Active (I
CC
)
L
H
H
L
Read
Data output
Active (I
CC
)
L
H
H
H
Output disable
High impedance
Active (I
CC
)
NOTE:
1.
= Don't care, L = Low, H = High
A
7
A
8
A
9
51BV1000-2
MEMORY
CELL ARRAY
(1024 x 128 x 8)
A
6
A
5
A
4
A
3
COLUMN GATE
V
CC
GND
I/O BUFFER
I/O
1
A
2
A
1
CE
1
, CE
2
CONTROL
LOGIC
ADDRESS
BUFFER
OE, WE
CONTROL
LOGIC
WE
OE
ROW
DECODER
COLUMN
DECODER
A
12
A
13
A
14
A
11
A
10
10
1024
A
0
7
128
128 x 8
8
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
A
15
A
16
CE
1
CE
2
Figure 2. LH51BV1000JY Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
A
0
A
16
Address inputs
CE
1
Chip enable 1
CE
2
Chip enable 2
WE
Write enable
OE
Output enable
SIGNAL
PIN NAME
I/O
1
I/O
8
Data inputs and outputs
V
CC
Power supply
GND
Ground
NC
No connection
LH51BV1000J
CMOS 1M (128K
8) Static RAM
2
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
NOTE
Supply voltage
V
CC
0.5 to +4.6
V
1
Input voltage
V
IN
0.5 to V
CC
+ 0.3
V
1, 2
Operating temperature
T
OPR
25 to +85
C
Storage temperature
T
STG
65 to +150
C
NOTE:
1.
The maximum applicable voltage on any pin with respect to GND.
2.
Undershoot of 3.0 V is allowed width of pulse below 50 ns.
RECOMMENDED OPERATING CONDITIONS (T
A
= -25
C to +85
C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Supply voltage
V
CC
2.7
3.0
3.6
V
Input voltage
V
IH
2.2
V
CC
+ 0.3
V
V
IL
0.3
0.4
V
1
NOTE:
1.
Undershoot of 3.0 V is allowed width of pulse below 50 ns.
DC ELECTRICALCHARACTERISTICS (T
A
= -25
C to +85
C, V
CC
= 2.7 V to 3.6 V)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
1
MAX.
UNIT
Input leakage
current
I
LI
V
IN
= 0 V to V
CC
1.0
1.0
A
Output leakage
current
I
LO
CE
1
= V
IH
or CE
2
= V
IL
or
OE = V
IH
or WE = V
IL
V
I/O
= 0 V to V
CC
1.0
1.0
A
Operating supply
current
I
CC1
CE
1
= V
IL
, V
IN
= V
IL
or V
IH
CE
2
= V
IH
, I
I/O
= 0 mA
t
CYCLE
=
MIN.
30
mA
I
CC2
CE
1
= V
IL
, V
IN
= V
IL
or V
IH
CE
2
= V
IH
, I
I/O
= 0 mA
t
CYCLE
=
1.0
s
5
Standby current
I
SB
CE
1
, CE
2
V
CC
0.2 V or CE
2
0.2 V
0.6
60
A
I
SB1
CE
1
= V
IH
or CE
2
= V
IL
1.0
mA
Output voltage
V
OL
I
OL
= 2.0 mA, V
CC
3 V
0.4
V
I
OL
= 0.1 mA
0.2
V
OH
I
OH
= 2. 0 m A, V
CC
3 V
2.4
I
OH
= 0.1 mA
V
CC
0.2
NOTE:
1
Typical values at V
CC
= 5.0 V, T
A
= 25C
AC ELECTRICAL CHARACTERISTICS
AC Test Conditions
PARAMETER
MODE
NOTE
Input pulse level
0.4 V to 2.4 V
Input rise and fall time
5 ns
Input and output timing ref. level
1.5 V
Output load
1 TTL + C
L
(100 pF)
1
NOTE:
1.
Including scope and jig capacitance.
CMOS 1M (128K
8) Static RAM
LH51BV1000J
3
READ CYCLE (T
A
= -25
C to +85
C, V
CC
= 2.7 V to 3.6 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Read cycle time
t
RC
70
ns
Address access time
t
AA
70
ns
CE
1
access time
t
ACE1
70
ns
CE
2
access time
t
ACE2
70
ns
Output enable to output valid
t
OE
40
ns
Output hold from address change
t
OH
10
ns
CE
1
Low to output active
t
LZ1
5
ns
1
CE
2
High to output active
t
LZ2
5
ns
1
OE Low to output active
t
OLZ
0
ns
1
CE
1
High to output in High impedance
t
HZ1
30
ns
1
CE
2
Low to output in High impedance
t
HZ2
30
ns
1
OE High to output in High impedance
t
OHZ
30
ns
1
NOTE:
1.
Active output to High impedance to output active tests specified for a
200 mV transition from steady state levels into the test load.
WRITE CYCLE (T
A
= -25
C to +85
C, V
CC
= 2.7 V to 3.6 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Write cycle time
t
WC
70
ns
Chip enable to end of write
t
CW
60
ns
Address valid to end of write
t
AW
60
ns
Address setup time
t
AS
0
ns
Write pulse width
t
WP
55
ns
Write recovery time
t
WR
0
ns
Input data setup time
t
DW
30
ns
Input data hold time
t
DH
0
ns
WE High to output active
t
OW
5
ns
1
WE Low to output in High impedance
t
WZ
30
ns
1
OE High to output in High impedance
t
OHZ
30
ns
1
NOTE:
1.
Active output to High impedance to output active tests specified for a
200 mV transition from steady state levels into the test load.
LH51BV1000J
CMOS 1M (128K
8) Static RAM
4
DATA RETENTION CHARACTERISTICS (T
A
= -25
C to +850
C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
1
MAX.
UNIT
NOTES
Data retention
supply voltage
V
CCDR
CE
2
0.2 V or
CE
1
V
CCDR
- 0.2 V
2.0
3.6
V
2
Data retention
supply current
I
CCDR
V
CCDR
= 3 V
CE
2
0.2 V or
CE
1
V
CCDR
- 0.2 V
T
A
= 25
C
0.5
1.0
A
T
A
= 40C
3.0
50
A
2
Chip enable
setup time
t
CDR
0
ms
Chip enable
hold time
t
R
5
ms
NOTES:
1.
Typical value at T
A
= 25C
2.
CE
2
V
CCDR
- 0.2 V or CE
2
0.2 V
PIN CAPACITANCE (T
A
= 25
C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
NOTE
Input capacitance
C
IN
V
IN
= 0 V
8
pF
1
I/O capacitance
C
I/O
V
I/O
= 0 V
10
pF
1
NOTE:
1.
This parameter is sampled and not production tested.
CMOS 1M (128K
8) Static RAM
LH51BV1000J
5
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