LH5316P00B
CMOS 16M (2M
8/1M
16) MROM
FEATURES
2,097,152
8 bit organization
(Byte mode: BYTE = V
IL
)
1,048,576
16 bit organization
(Word mode: BYTE = V
IH
)
Access time: 120 ns (MAX.)
Supply current:
Operating: 70 mA (MAX.)
Standby: 100
A (MAX.)
TTL compatible I/O
Three-state output
Single +5 V power supply
Static operation
Package:
44-pin, 600-mil SOP
Item related with COCOM regulation:
Non programmable
Not designed or rated as radiation
hardened
CMOS process (P type silicon
substrate)
DESCRIPTION
The LH5316P00B is a 16M-bit mask-programmable
ROM organized as 2,097,152
8 bits (Byte mode) or
1,048,576
16 bits (Word mode) that can be selected
by a BYTE input pin. It is fabricated using silicon-gate
CMOS process technology.
PIN CONNECTIONS
5316P00B-1
TOP VIEW
5
6
7
8
11
12
34
33
32
31
30
29
26
9
10
28
27
A
15
A
16
BYTE
13
14
15
36
35
A
13
16
25
D
15
/A
-1
(NOTE)
D
13
D
5
D
6
A
14
44-PIN SOP
3
4
38
37
1
2
40
39
A
10
D
14
D
7
24
23
V
CC
D
4
D
12
17
18
19
20
A
9
A
11
A
12
41
A
8
A
19
NC
42
21
OE
A
1
A
0
GND
CE
A
2
D
8
D
9
A
3
A
4
A
5
A
6
D
1
A
7
D
2
D
3
D
10
A
17
A
18
D
0
GND
D
11
22
NC
43
44
NOTE: The D
15
/A
-1
pin becomes LSB address input (A
-1
)
when the BYTE pin is set to be LOW in byte mode and
data output (D
15
) when set to be HIGH in word mode.
The input state of BYTE pin can not be changed during
operation. The BYTE pin must be set to either GND or V
CC
.
Figure 1. Pin Connections
1
5316P00B-2
A
4
A
3
A
13
A
12
A
11
A
10
A
9
37
38
39
40
4
7
8
A
8
A
7
A
5
MEMORY
MATRIX
(2,097,152 x 8)
(1,048,576 x 16)
SENSE AMPLIFIER
42
33
6
A
1
A
0
10
11
A
2
9
41
A
6
5
A
14
36
ADDRESS BUFFER
CE
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
OE
BUFFER
A
15
35
A
16
34
12
TIMING
GENERATOR
A
17
3
BYTE
A
18
2
A
19
43
ADDRESS
BUFFER
BYTE/WORD
SWITCHOVER
CIRCUIT
14
OE
DATA SELECTOR/OUTPUT BUFFER
D
3
D
2
D
1
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
4
D
5
D
13
D
0
D
14
D
15
22
20
18
16
26
19
17
15
21
30
24
25
27
29
31
28
31
A
-1
V
CC
23
GND
13
32
Figure 2. LH5316P00B Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
A
-1
- A
19
Address input
D
0
- D
15
Data output
BYTE
8bit /
16 bit
(Byte/word) mode
select input
CE
Chip enable input
SIGNAL
PIN NAME
OE
Output enable input
V
CC
Power supply
GND
Ground
NC
No connection
LH5316P00B
CMOS 16M (2M x 8/1M x 16) MROM
2
TRUTH TABLE
CE
OE
BYTE
A
-1
(D
15
)
DATA OUTPUT
ADDRESS INPUT
SUPPLY
CURRENT
D
0
- D
7
D
8
- D
15
LSB
MSB
H
X
X
X
High-Z
High-Z
Standby (I
SB
)
L
H
X
X
High-Z
High-Z
Operating
L
L
H
D
0
- D
7
D
8
- D
15
A
0
A
19
Operating
L
L
L
L
D
0
- D
7
High-Z
A
-1
A
19
Operating
L
L
L
H
D
8
- D
15
High-Z
A
-1
A
19
Operating
NOTES:
X = Don't care; High-Z = High-impedance
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
Supply voltage
V
CC
-0.3 to +7.0
V
Input voltage
V
IN
-0.3 to V
CC
+ 0.3
V
Output voltage
V
OUT
-0.3 to V
CC
+ 0.3
V
Operating temperature
T
OPR
0 to +70
C
Storage temperature
T
STG
-65 to +150
C
RECOMMENDED OPERATING CONDITIONS (T
A
= 0 to +70
C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
V
CC
4.5
5.0
5.5
V
DC ELECTICAL CHARACTERISTICS (V
CC
= 5 V
10%, T
A
= 0 to +70
C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Input `High' voltage
V
IH
2.2
V
CC
+ 0.3
V
Input `Low' voltage
V
IL
-0.3
0.8
V
Output `High' voltage
V
OH
I
OH
= -400
A
2.4
V
Output `Low' voltage
V
OL
I
OL
= 2.0 mA
0.4
V
Input leakage current
| I
LI
|
V
IN
= 0 V to V
CC
10
A
Output leakage current
| I
LO
|
V
OUT
= 0 V to V
CC
10
A
1
Operating current
I
CC1
t
RC
= 120 ns
70
mA
2
I
CC2
t
RC
= 1
s
55
Standby current
I
SB1
CE = V
IH
2
mA
I
SB2
CE = V
CC
- 0.2 V
100
A
Input capacitance
C
IN
f = 1 MHz, t
A
= 25
C
10
pF
Output capacitance
C
OUT
10
pF
NOTES:
1.
CE = V
IH
, OE = V
IH
, output is open
2.
V
IN
= V
IH
, V
IL
, CE = V
IL
, output is open
CMOS 16M (2M x 8/1M x 16) MROM
LH5316P00B
3
AC ELECTICAL CHARACTERISTICS (V
CC
= 5 V
10%, T
A
= 0 to +70
C)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Read cycle time
t
RC
120
ns
Address access time
t
AA
120
ns
Chip enable access time
t
ACE
120
ns
Output enable delay time
t
OE
60
ns
Output hold time
t
OH
5
ns
Output floating time
t
CHZ
60
ns
1
t
OHZ
60
ns
NOTE:
1.
Determined by the time for the output to be opened. (Irrespective of output voltage)
AC TEST CONDITIONS
PARAMETER
RATING
Input voltage amplitude
0.6 V to 2.4 V
Input rise/fall time
10 ns
Input signal fall time
10 ns
Input reference level
1.5 V
Output reference level
1.5 V
Output load condition
1TTL + 100 pF
CAUTION
It is recommended that a decoupling capacitor be connected between V
CC
and GND-Pin.
LH5316P00B
CMOS 16M (2M x 8/1M x 16) MROM
4
t
AA
A
-1
- A
19
t
OHZ
t
CHZ
D
0
- D
7
5316P00B-3
t
RC
t
ACE
CE
DATA VALID
(NOTE)
(NOTE)
OE
t
OE
(NOTE)
t
OH
NOTE: The output data becomes valid when the
last intervals, t
AA
, t
ACE
, or t
OE
,
have concluded.
Figure 3. Byte Mode (BYTE = V
IL
)
t
AA
A
0
- A
19
t
OHZ
t
CHZ
5316P00B-4
t
RC
t
ACE
CE
DATA VALID
(NOTE)
(NOTE)
OE
t
OE
(NOTE)
(D
0
- D
15
)
t
OH
NOTE: The output data becomes valid when the
last intervals, t
AA
, t
ACE
, or t
OE
,
have concluded.
Figure 4. Word Mode (BYTE = V
IH
)
CMOS 16M (2M x 8/1M x 16) MROM
LH5316P00B
5
LH5316P00B
Device Type
N
Package
5316P00B-5
Example: LH5316P00N (CMOS 16M (2M x 8 or 1M x 16) Mask-Programmable ROM, 44-pin, 600-mil SOP)
CMOS 16M (2M x 8 or 1M x 16) Mask-Programmable ROM
44-pin, 600-mil SOP (SOP044-P-600)
ORDERING INFORMATION
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
44SOP (SOP044-P-0600)
16.40 [0.646]
15.60 [0.614]
13.40 [0.528]
13.00 [0.512]
14.40 [0.567]
28.40 [1.118]
28.00 [1.102]
0.15 [0.006]
1.275 [0.050]
0.25 [0.010]
0.05 [0.002]
1.275 [0.050]
2.9 [0.114]
2.5 [0.098]
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
44
23
22
1
3.25 [0.128]
2.45 [0.096]
44SOP
2.9 [0.114]
2.5 [0.098]
1.275 [0.050]
0.25 [0.010]
0.05 [0.002]
0.80 [0.031]
0 - 10
SEE
DETAIL
DETAIL
PACKAGE DIAGRAM
LH5316P00B
CMOS 16M (2M x 8/1M x 16) MROM
6
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