LH532048
CMOS 2M (128K
16) MROM
FEATURES
131,072 words
16 bit organization
Access time: 100 ns (MAX.)
Static operation
TTL compatible I/O
Three-state outputs
Single +5 V power supply
Power consumption:
Operating: 412.5 mW (MAX.)
Standby: 550
W (MAX.)
Packages:
40-pin, 600-mil DIP
40-pin, 525-mil SOP
44-pin, 650-mil QFJ (PLCC)
DESCRIPTION
The LH532048 is a 2M-bit mask-programmable ROM
organized as 131,072
16 bits. It is fabricated using
silicon-gate CMOS process technology.
PIN CONNECTIONS
532048-1
TOP VIEW
2
3
4
5
8
9
D
10
D
13
37
36
35
34
33
32
29
26
D
15
D
14
6
7
D
11
D
12
31
30
A
14
A
12
A
10
A
8
A
5
10
11
12
39
38
13
28
A
7
27
A
6
GND
A
13
40-PIN DIP
40-PIN SOP
14
15
16
17
18
19
20
23
25
24
22
21
A
0
D
1
D
0
D
2
D
4
D
3
D
5
OE
A
11
A
4
40
1
CE
NC
V
CC
GND
D
6
D
9
NC
A
16
A
15
A
3
A
2
A
1
D
7
D
8
A
9
Figure 1. Pin Connections for DIP and
SOP Packages
532048-2
TOP VIEW
8
9
10
11
14
15
D
7
D
8
36
35
34
33
32
31
D
10
D
9
12
13
NC
GND
30
29
A
10
A
9
NC
A
7
16
17
38
37
A
11
D
6
D
5
GND
44-PIN PLCC
A
12
A
8
A
6
39
7
D
11
D
12
A
13
18 19 20 21 22 23 24 25 26 27 28
D
3
OE
NC
6
5
4
3
2
1 44 43 42 41 40
D
13
CE
NC
NC
D
4
D
2
D
1
D
0
A
0
A
1
A
2
A
3
A
4
A
5
D
14
D
15
V
CC
NC
A
16
A
15
A
14
Figure 2. Pin Connections for QFJ
(PLCC) Package
1
TRUTH TABLE
CE
OE
DATA OUTPUT
SUPPLY CURRENT
H
X
High-Z
Standby
L
H
High-Z
Operating
L
L
D
0
D
15
Operating
NOTE:
X = H or L, High-Z = High-impedance
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
Supply voltage
V
CC
0.3 to +7.0
V
Input voltage
V
IN
0.3 to V
CC
+ 0.3
V
Output voltage
V
OUT
0.3 to V
CC
+ 0.3
V
Operating temperature
Topr
0 to +70
C
Storage temperature
Tstg
65 to +150
C
RECOMMENDED OPERATING CONDITIONS (T
A
= 0
C to +70
C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
V
CC
4.5
5.0
5.5
V
DC CHARACTERISTICS (V
CC
= 5 V
10%, T
A
= 0
C to +70
C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Input `High' voltage
V
IH
2.2
V
CC
+ 0.3
V
Input `Low' voltage
V
IL
0.3
0.8
V
Output `High' voltage
V
OH
I
OH
= 400
A
2.4
V
Output `Low' voltage
V
OL
I
OL
= 2.0 mA
0.4
V
Input leakage current
| I
Ll
|
V
IN
= 0 V to V
CC
10
A
Output leakage current
| I
LO
|
V
OUT
= 0 V to V
CC
10
A
1
Operating current
I
CC1
t
RC
= 100 ns
75
mA
2
I
CC2
t
RC
= 1
s
65
mA
2
I
CC3
t
RC
= 100 ns
70
mA
3
I
CC4
t
RC
= 1
s
60
mA
3
Standby current
I
SB1
CE = V
IH
3
mA
I
SB2
CE = V
CC
0.2 V
100
A
Input capacitance
C
IN
f = 1 MHz
T
A
= 25
C
10
pF
Output capacitance
C
OUT
10
pF
NOTES:
1.
CE/OE = V
IH
2.
V
IN
= V
IH
or V
IL
, CE = V
IL
, outputs open
3.
V
IN
= (V
CC
0.2 V) or 0.2 V, CE = 0.2 V, outputs open
LH532048
CMOS 2M MROM
4
AC CHARACTERISTICS (V
CC
= 5 V
10%, T
A
= 0
C to +70
C)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Read cycle time
t
RC
100
ns
Address access time
t
AA
100
ns
Chip enable access time
t
ACE
100
ns
Output enable delay time
t
OE
55
ns
Output hold time
t
OH
0
ns
CE to output in High-Z
t
CHZ
50
ns
1
OE to output in High-Z
t
OHZ
ns
NOTE:
1.
This is the time required for the outputs to become high-impedance.
AC TEST CONDITIONS
PARAMETER
RATING
Input voltage amplitude
0.4 V to 2.6 V
Input rise/fall time
10 ns
Input/output reference level
1.5 V
Output load condition
1 TTL + 100 pF
CAUTION
To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between
the V
CC
pin and the GND pin.
A
0
- A
16
t
OHZ
t
CHZ
532048-5
t
RC
CE
OE
t
OH
DATA VALID
NOTE: The output data becomes valid when the last
intervals, t
AA
, t
ACE
, or t
OE
, have concluded.
t
OE
t
ACE
t
AA
D
0
- D
15
(NOTE)
(NOTE)
(NOTE)
Figure 5. Timing Diagram
CMOS 2M MROM
LH532048
5
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