LH53517
CMOS 512K (64K
8) MROM
FEATURES
65,536 words
8 bit organization
Access time: 150 ns (MAX.)
Low-power consumption:
Operating: 165 mW (MAX.)
Standby: 550
W (MAX.)
Static operation
TTL compatible I/O
Three-state outputs
Single +5 V power supply
Mask-programmable OE/OE
Packages:
28-pin, 600-mil DIP
28-pin, 450-mil SOP
28-pin, 8
13.4 mm
2
TSOP (Type I)
DESCRIPTION
The LH53517 is a mask-programmable ROM organ-
ized as 65,536
8 bits. It is fabricated using silicon-gate
CMOS process technology.
PIN CONNECTIONS
53517-1
TOP VIEW
1
2
3
4
7
8
A
2
A
5
26
25
24
23
22
21
18
15
A
7
A
6
5
6
A
3
A
4
20
19
A
15
A
12
GND
A
13
A
8
A
11
A
10
CE
D
7
D
6
D
3
9
10
11
28
27
A
14
A
1
V
CC
12
17
D
5
16
D
4
D
1
D
2
A
0
D
0
A
9
OE/OE
28-PIN DIP
28-PIN SOP
13
14
Figure 1. Pin Connections for DIP and
SOP Packages
2
3
4
5
6
9
10
7
8
A
11
11
1
28
27
26
25
22
21
24
23
20
19
A
10
28-PIN TSOP (Type I)
12
13
14
17
16
18
15
OE/OE
A
8
A
9
A
12
D
2
D
1
A
1
D
7
CE
D
5
D
6
GND
D
4
D
3
D
0
A
0
53517-2
V
CC
A
7
A
6
A
5
A
4
A
3
A
2
TOP VIEW
A
15
A
14
A
13
NOTE: Reverse bend available on request.
Figure 2. Pin Connections for TSOP Package
1
NOTE:
1.
Active level of OE/OE is mask-programmable.
TRUTH TABLE
CE
OE/OE
DATA OUTPUT
CURRENT CONSUMPTION
H
X
High-Z
Standby
L
L/H
Operating
H/L
Output
NOTE:
X = H or L
ABSOLUTE MAXIMUM RATINGS
53517-3
A
2
A
11
A
10
A
9
A
8
A
7
28
23
21
24
25
5
8
A
6
A
5
V
CC
A
3
MEMORY
MATRIX
(65,536 x 8)
SENSE AMPLIFIER
14
4
GND
7
3
A
4
6
A
12
2
OE/OE
ADDRESS BUFFER
CE
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
OE
BUFFER
A
13
26
A
14
27
TIMING
GENERATOR
A
15
1
DATA
OUTPUT BUFFER
A
1
A
0
9
10
22
20
16
17
18
11
19
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
15
12
13
NOTE: Pin numbers apply to the 28-pin DIP or SOP.
Figure 3. LH53517 Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
NOTE
A
0
A
15
Address input
D
0
D
7
Data output
CE
Chip enable input
SIGNAL
PIN NAME
NOTE
OE/OE
Output enable input
1
V
CC
Power supply (+5 V)
GND
Ground
LH53517
CMOS 512K MROM
2
PARAMETER
SYMBOL
RATING
UNIT
Supply voltage
V
CC
0.3 to +7.0
V
Input voltage
V
IN
0.3 to V
CC
+ 0.3
V
Output voltage
V
OUT
0.3 to V
CC
+ 0.3
V
Operating temperature
Topr
0 to +70
C
Storage temperature
Tstg
65 to +150
C
RECOMMENDED OPERATING CONDI-
TIONS (T
A
= 0 to +70
C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
V
CC
4.5
5.0
5.5
V
DC CHARACTERISTICS (V
CC
= 5 V
10%, T
A
= 0 to +70
C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Input `Low' voltage
V
IL
0.3
0.8
V
Input `High' voltage
V
IH
2.2
V
CC
+ 0.3
V
Output `Low' voltage
V
OL
I
OL
= 1.6 mA
0.4
V
Output `High' voltage
V
OH
I
OH
= 400
A
2.4
V
Input leakage current
| I
LI
|
V
IN
= 0 V to V
CC
10
A
Output leakage current
| I
LO
|
V
OUT
= 0 V to V
CC
10
A
1
Operating current
I
CC1
t
RC
= 150 ns
30
mA
2
I
CC2
t
RC
= 1
s
15
I
CC3
t
RC
= 150 ns
25
mA
3
I
CC4
t
RC
= 1
s
12
Standby current
I
SB1
CE = V
IH
2
mA
I
SB2
CE = V
CC
0.2 V
100
A
Input capacitance
C
IN
f = 1 MHz
T
A
= 25
C
10
pF
Output capacitance
C
OUT
10
pF
NOTES:
1.
CE/OE = V
IH
, OE = V
IL
2.
V
IN
= V
IH
/V
IL
, CE = V
IL
, outputs open
3.
V
IN
= (V
CC
0.2 V), 0.2 V, CE = 0.2 V, outputs open
AC CHARACTERISTICS (V
CC
= 5 V
10%, T
A
= 0 to +70
C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Read cycle time
t
RC
150
ns
Address access time
t
AA
150
ns
Chip enable access time
t
ACE
150
ns
Output enable delay time
t
OE
10
80
ns
Output hold time
t
OH
5
ns
CE to output in High-Z
t
CHZ
70
ns
1
OE to output in High-Z
t
OHZ
70
ns
1
NOTE:
1.
This is the time required for the output to become high-imped-
ance.
CMOS 512K MROM
LH53517
3
AC TEST CONDITIONS
PARAMETER
RATING
Input voltage amplitude
0.6 V to 2.4 V
Input rise/fall time
10 ns
Input reference level
1.5 V
Output reference level
0.8 V and 2.2 V
Output load condition
1TTL + 100 pF
CAUTION
To stabilize the power supply, it is recommended that
a high-frequency bypass capacitor be connected be-
tween the V
CC
pin and the GND pin.
t
OE
(NOTE)
t
AA
A
0
- A
15
t
OHZ
t
CHZ
D
0
- D
7
53517-4
t
RC
t
ACE
CE
OE
t
OH
DATA VALID
(NOTE)
(NOTE)
OE
NOTE: Data becomes valid after the intervals t
AA
, t
ACE
, and t
OE
from address
input, chip enable, and output enable, respectively have been met.
Figure 4. Timing Diagram
LH53517
CMOS 512K MROM
4
PACKAGE DIAGRAMS
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
28DIP (DIP028-P-0600)
1
14
15
28
28DIP-2
13.45 [0.530]
12.95 [0.510]
0.51 [0.020] MIN.
5.20 [0.205]
5.00 [0.197]
3.50 [0.138]
3.00 [0.118]
2.54 [0.100]
TYP.
0.60 [0.024]
0.40 [0.016]
0.30 [0.012]
0.20 [0.008]
DETAIL
36.30 [1.429]
35.70 [1.406]
0
TO 15
4.50 [0.177]
4.00 [0.157]
15.24 [0.600]
TYP.
28-pin, 600-mil DIP
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
28SOP (SOP028-P-0450)
12.40 [0.488]
11.60 [0.457]
8.80 [0.346]
8.40 [0.331]
10.60 [0.417]
18.20 [0.717]
17.80 [0.701]
0.15 [0.006]
1.025 [0.040]
0.20 [0.008]
0.00 [0.000]
1.025 [0.040]
2.40 [0.094]
2.00 [0.079]
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
28
15
14
1
1.70 [0.067]
1.70 [0.067]
28SOP
28-pin, 450-mil SOP
CMOS 512K MROM
LH53517
5
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
28TSOP (TSOP028-P-0813)
28
1
28TSOP
14
15
0.28 [0.011]
0.12 [0.005]
0.55 [0.022]
TYP.
12.00 [0.472]
11.60 [0.457]
13.70 [0.539]
13.10 [0.516]
8.20 [0.323]
7.80 [0.307]
0.15 [0.006]
1.10 [0.043]
0.90 [0.035]
1.20 [0.047]
MAX.
12.60 [0.496]
12.20 [0.480]
0.20 [0.008]
0.10 [0.004]
0.20 [0.008]
0.00 [0.000]
1.10 [0.043]
0.90 [0.035]
0.425 [0.017]
0.20 [0.008]
0.00 [0.000]
0 - 10
DETAIL
0.425 [0.017]
28-pin, 8
13 mm
2
TSOP (Type I)
D 28-pin, 600-mil DIP (DIP028-P-0600)
N 28-pin, 450-mil SOP (SOP028-P-0450)
T 28-pin, 8 x 13.4 mm
2
TSOP (Type I) (TSOP028-P-0813)
TR 28-pin, 8 x 13 mm
2
TSOP (Type I) Reverse bend (TSOP028-P-0813)
LH53517
Device Type
X
Package
53517-5
Example: LH53517D (CMOS 512K (64K x 8) Mask Programmable ROM, 28-pin, 600-mil DIP)
CMOS 512K (64K x 8) Mask Programmable ROM
ORDERING INFORMATION
LH53517
CMOS 512K MROM
6
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