LH540203

CMOS 2048

9 Asynchronous FIFO

FEATURES

··

Fast Access Times: 15/20/25/35/50 ns

··

Fast-Fall-Through Time Architecture Based on
CMOS Dual-Port SRAM Technology

··

Input Port and Output Port Have Entirely
Independent Timing

··

Expandable in Width and Depth

··

Full, Half-Full, and Empty Status Flags

··

Data Retransmission Capability

··

TTL-Compatible I/O

··

Pin and Functionally Compatible with Sharp LH5498
and with Am/IDT/MS7203

··

Control Signals Assertive-LOW for Noise Immunity

··

Packages:
28-Pin,

300-mil

PDIP

28-Pin,

300-mil

SOJ

32-Pin

PLCC

PIN CONNECTIONS

FUNCTIONAL DESCRIPTION

The LH540203 is a FIFO (First-In, First-Out) memory

device, based on fully-static CMOS dual-port SRAM tech-
nology, capable of storing up to 2048 nine-bit words. It
follows the industry-standard architecture and package
pinouts for nine-bit asynchronous FIFOs. Each nine-bit
LH540203 word may consist of a standard eight-bit byte,
together with a parity bit or a block-marking/framing bit.

The input and output ports operate entirely inde-

pendently of each other, unless the LH540203 becomes
either totally full or else totally empty. Data flow at a port
is initiated by asserting either of two asynchronous, as-
sertive-LOW control inputs: Write (W) for data entry at the
input port, or Read (R) for data retrieval at the output port.

Full, Half-Full, and Empty status flags monitor the

extent to which the internal memory has been filled. The
system may make use of these status outputs to avoid
the risk of data loss, which otherwise might occur either
by attempting to write additional words into an already-full
LH540203, or by attempting to read additional words from
an already-empty LH540203. When an LH540203 is
operating in a depth-cascaded configuration, the Half-Full
Flag is not available.

540203-2D

FL/RT

XO/HF

28-PIN PDIP
28-PIN SOJ

TOP VIEW

Figure 1. Pin Connections for PDIP and

SOJ * Packages

32 31 30

14 15 16

FL/RT

XO/HF

540203-3D

32-PIN PLCC

TOP VIEW

NOTE:

= No external electrical connections are allowed.

Figure 2. Pin Connections for PLCC Package

* This is a final data sheet; except that all references to the SOJ package have Advance Information status.

Data words are read out from the LH540203's output

port in precisely the same order that they were written in
at its input port; that is, according to a First-In, First Out
(FIFO) queue discipline. Since the addressing sequence
for a FIFO device's memory is internally predefined, no
external addressing information is required for the opera-
tion of the LH540203 device.

Drop-in-replacement compatibility is maintained with

both larger sizes and smaller sizes of industry-standard
nine-bit asynchronous FIFOs. The only change is in the
number of internally-stored data words implied by the
states of the Full Flag and the Half-Full Flag.

The Retransmit (RT) control signal causes the internal

FIFO-memory-array read-address pointer to be set back
to zero, to point to the LH540203's first physical memory
location, without affecting the internal FIFO-memory-
array write-address pointer. Thus, the Retransmit control
signal provides a mechanism whereby a block of data,
delimited by the zero physical address and the current
write-address-pointer value, may be read out

repeatedly

an arbitrary number of times. The only restrictions are that
neither the read-address pointer nor the write-address
pointer may `wrap around' during this entire process, i.e.,
advance past physical location zero after traversing the
entire memory. The retransmit facility is not available
when an LH540203 is operating in a depth-expanded
configuration.

The Reset (RS) control signal returns the LH540203

to an initial state, empty and ready to be filled. An
LH540203 should be reset during every system power-up
sequence. A reset operation causes the internal FIFO-
memory-array write-address pointer, as well as the read-
address pointer, to be set back to zero, to point to the
LH540203's first physical memory location. Any informa-
tion which previously had been stored within the
LH540203 is not recoverable after a reset operation.

A cascading (depth-expansion) scheme may be imple-

mented by using the Expansion In (XI) input signal and
the Expansion Out (XO/HF) output signal. This allows a
deeper `effective FIFO' to be implemented by using two
or more LH540203 devices, without incurring additional
latency (`fallthrough' or `bubblethrough') delays, and with-
out the necessity of storing and retrieving any given data
word more than once. In this cascaded operating mode,
one LH540203 device must be designated as the `first-
load' or `master' device, by grounding its First-Load
(FL/RT) control input; the remaining LH540203 devices
are designated as `slaves,' by tying their FL/RT inputs
HIGH. Because of the need to share control signals on
pins, the Half-Full Flag and the retransmission capability
are not available for either `master' or `slave' LH540203
devices operating in cascaded mode.

FUNCTIONAL DESCRIPTION (cont'd)

DATA OUTPUTS

- Q

FLAG

LOGIC

WRITE

POINTER

READ

POINTER

DATA INPUTS

- D

DUAL-PORT

RAM

ARRAY

2048 x 9

EF
FF

. . .

540203-1

INPUT

PORT

CONTROL

RESET

LOGIC

OUTPUT

PORT

CONTROL

EXPANSION

LOGIC

XO/HF

FL/RT

Figure 3. LH540203 Block Diagram

LH540203

CMOS 2048

9 Asynchronous FIFO

OPERATIONAL DESCRIPTION

Reset

The LH540203 is reset whenever the Reset input (RS)

is taken LOW. A reset operation initializes both the read-
address pointer and the write-address pointer to point to
location zero, the first physical memory location. During
a reset operation, the state of the XI and FL/RT inputs
determines whether the device is in standalone mode or
in depth-cascaded mode. (See Tables 1 and 2.) The reset
operation forces the Empty Flag EF to be asserted
(EF = LOW), and the Half-Full Flag HF and the Full Flag
FF to be deasserted (HF = FF = HIGH); the Data Out pins
(D

) are forced into a high-impedance state.

A reset operation is required whenever the LH540203

first is powered up. The Read (R) and Write (W) inputs
may be in any state when the reset operation is initiated;
but they must be HIGH, before the reset operation is
terminated by a rising edge of RS, by a time t

RRSS

(for

Read) or t

WRSS

(for Write) respectively. (See Figure 10.)

Write

A write cycle is initiated by a falling edge of the Write

(W) control input. Data setup times and hold times must
be observed for the data inputs (D

). Write opera-

tions may occur independently of any ongoing read op-
erations. However, a write operation is possible only if the
FIFO is not full, (i.e., if the Full Flag FF is HIGH).

At the falling edge of W for the first write operation after

the memory is half filled, the Half-Full Flag is asserted
(HF = LOW). It remains asserted until the difference
between the write pointer and the read pointer indicates
that the data words remaining in the LH540203 are filling
the FIFO memory to less than or equal to one-half of its
total capacity. The Half-Full Flag is deasserted
(HF = HIGH) by the appropriate rising edge of R. (See
Table 3.)

The Full Flag is asserted (FF = LOW) at the falling edge

of W for the write operation which fills the last available
location in the FIFO memory array. FF = LOW inhibits
further write operations until FF is cleared by a valid read

operation. The Full Flag is deasserted (FF = HIGH) after
the next rising edge of R releases another memory loca-
tion. (See Table 3.)

Read

A read cycle is initiated by a falling edge of the Read

(R) control input. Read data becomes valid at the data
outputs (Q

) after a time t

from the falling edge of

R. After R goes HIGH, the data outputs return to a
high-impedance state. Read operations may occur inde-
pendently of any ongoing write operations. However, a
read operation is possible only if the FIFO is not empty
(i.e., if the Empty Flag EF is HIGH).

The LH540203's internal read-address and write-

address pointers operate in such a way that consecutive
read operations always access data words in the same
order that they were written. The Empty Flag is asserted
(EF = LOW) after that falling edge of R which accesses
the last available data word in the FIFO memory. EF is
deasserted (EF = HIGH) after the next rising edge of W
loads another valid data word. (See Table 3.)

Data Flow-Through

Read-data flow-through mode occurs when the Read

(R) control input is brought LOW while the FIFO is empty,
and is held LOW in anticipation of a write cycle. At the end
of the next write cycle, the Empty Flag EF momentarily is
deasserted, and the data word just written becomes
available at the data outputs (Q

) after a maxi-

mum time of t

WEF

+ t

. Additional write operations may occur

while the R input remains LOW; but only data from the
first write operation flows through to the data outputs.
Additional data words, if any, may be accessed only by
toggling R.

Write-data flow-through mode occurs when the Write

(W) input is brought LOW while the FIFO is full, and is
held LOW in anticipation of a read cycle. At the end of the
read cycle, the Full Flag momentarily is deasserted, but
then immediately is reasserted in response to W being
held LOW. A data word is written into the FIFO on the
rising edge of W, which may occur no sooner than
t

RFF

+ t

WPW

after the read operation.

PIN DESCRIPTIONS

PIN

PIN TYPE

DESCRIPTION

Input Data Bus

O/Z

Output Data Bus

Write Request

Read Request

Empty Flag

Full Flag

PIN

PIN TYPE

DESCRIPTION

XO/HF

Expansion Out/Half-Full Flag

Expansion In

FL/RT

First Load/Retransmit

Reset

Positive Power Supply

Ground

NOTE:
1.

I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level

CMOS 2048

9 Asynchronous FIFO

LH540203

OPERATIONAL DESCRIPTION (cont'd)

Retransmit

The FIFO can be made to reread previously-read data

by means of the Retransmit function. A retransmit opera-
tion is initiated by pulsing the RT input LOW. Both R and
W must be deasserted (HIGH) for the duration of the
retransmit pulse. The FIFO's internal read-address
pointer is reset to point to location zero, the first physical
memory location, while the internal write-address
pointer remains unchanged.

After a retransmit operation, those data words in the

region in between the read-address pointer and the
write-address pointer may be reaccessed by subsequent
read operations. A retransmit operation may affect the
state of the status flags FF, HF, and EF, depending on
the relocation of the read-address pointer. There is no
restriction on the number of times that a block of data
within an LH540203 may be read out, by repeating the
retransmit operation and the subsequent read operations.

The maximum length of a data block which may be

retransmitted is 2048 words. Note that if the write-address
pointer ever `wraps around' (i.e., passes location zero
more than once) during a sequence of retransmit opera-
tions, some data words will be lost.

The Retransmit function is not available when the

LH540203 is operating in depth-cascaded mode,
because the FL/RT control pin must be used for first-load
selection rather than for retransmission control.

Table 1. Grouping-Mode Determination

During a Reset Operation

FL/

MODE

XO/HF

USAGE

FL/RT

USAGE

Cascaded
Slave

Cascaded
Master

Standalone

(none)

NOTES:
1. A reset operation forces XO HIGH for the n

FIFO, thus forcing

XI HIGH for the (n+1)

FIFO.

2. The terms `master' and `slave' refer to operation in depth-cas-

caded grouping mode.

3. H = HIGH; L = LOW; X = Don't Care.

Table 2. Expansion-Pin Usage According to

Grouping Mode

I/O

PIN

STANDALONE

CASCADED

MASTER

CASCADED

SLAVE

Grounded

From XO
(n-1st
FIFO)

XO/HF

Becomes
HF

To XI
(n+1st
FIFO)

FL/RT

Becomes
RT

Grounded
(Logic
LOW)

Logic
HIGH

Table 3. Status Flags

NUMBER OF UNREAD DATA

WORDS PRESENT WITHIN

2048

9 FIFO

1 to 1024

1025 to 2047

2048

LH540203

CMOS 2048

9 Asynchronous FIFO

OPERATIONAL MODES

Standalone Configuration

When depth cascading is not required for a given

application, the LH540203 is placed in standalone mode
by tying the Expansion In input (XI) to ground. This
input is internally sampled during a reset operation. (See
Table 1.)

Width Expansion

Word-width expansion is implemented by placing mul-

tiple LH540203 devices in parallel. Each LH540203
should be configured for standalone mode. In this ar-
rangement, the behavior of the status flags is identical for
all devices; so, in principle, a representative value for
each of these flags could be derived from any one device.
In practice, it is better to derive `composite' flag values
using external logic, since there may be minor speed
variations between different actual devices. (See Figures
4, 5, and 6.)

WRITE

DATA IN

- D

FULL FLAG

RESET

RETRANSMIT

EMPTY FLAG

READ

LH540203

DATA OUT

- Q

540203-17

Figure 4. Standalone FIFO (2048

WRITE

FULL FLAG

RESET

READ

EMPTY FLAG

540203-18

RETRANSMIT

LH540203

DATA IN

- D

DATA OUT

- Q

Figure 5. FIFO Word-Width Expansion (2048

18)

CMOS 2048

9 Asynchronous FIFO

LH540203

OPERATIONAL MODES (cont'd)

Depth Cascading

Depth cascading is implemented by configuring the

required number of LH540203s in depth-cascaded mode.
In this arrangement, the FIFOs are connected in a circular
fashion, with the Expansion Out output (XO) of each
device tied to the Expansion In input (XI) of the next
device. One FIFO in the cascade must be designated as
the `first-load' device, by tying its First Load input (FL/RT)
to ground. All other devices must have their FL/RT inputs
tied HIGH. In this mode, W and R signals are shared by
all devices, while logic within each LH540203 controls the
steering of data. Only one LH540203 is enabled during
any given write cycle; thus, the common Data In inputs of

all devices are tied together. Likewise, only one
LH540203 is enabled during any given read cycle; thus,
the common Data Out outputs of all devices are wire-
ORed together.

In depth-cascaded mode, external logic should be

used to generate a composite Full Flag and a composite
Empty Flag, by ANDing the FF outputs of all LH540203
devices together and ANDing the EF outputs of all devices
together. Since FF and EF are assertive-LOW signals,
this `ANDing' actually is implemented using an asser-
tive-HIGH physical OR gate. The Half-Full Flag and the
Retransmit function are not available in depth-cascaded
mode.

LH540203

Vcc

540203-19

EMPTY

FULL

LH540203

DATA IN

- D

DATA OUT

- Q

Figure 6. FIFO Depth Cascading (6144

LH540203

CMOS 2048

9 Asynchronous FIFO

OPERATIONAL MODES (cont'd)

Compound FIFO Expansion

A combination of word-width expansion and depth

cascading may be implemented easily by operating
groups of depth-cascaded FIFOs in parallel.

Bidirectional FIFO Operation

Bidirectional data buffering between two systems may

be implemented by operating LH540203 devices in par-
allel, but in opposite directions. The Data In inputs of each

LH540203 are tied to the corresponding Data Out outputs
of another LH540203, which is operating in the opposite
direction, to form a single bidirectional bus interface. Care
must be taken to assure that the appropriate read, write,
and flag signals are routed to each system. Both word-
width expansion and depth cascading may be used in
bidirectional applications.

LH540203

DEPTH EXPANSION

BLOCK

LH540203

DEPTH EXPANSION

BLOCK

LH540203

DEPTH EXPANSION

BLOCK

- Q

DATA OUT

N-9

N-1

- D

N-1

- D

N-1

- D

N-1

DATA IN

- Q

N-1

- Q

540203-20

ARRAY STORES
N-BIT WORDS.

- Q

N-10

Figure 7. Compound FIFO Expansion

LH540203

SYSTEM A

SYSTEM B

0 - 8

EFa

HFa

RTa

FFb

RTb

HFb

EFb

540203-21

FFa

Figure 8. Bidirectional FIFO Operation

(2048

CMOS 2048

9 Asynchronous FIFO

LH540203

ABSOLUTE MAXIMUM RATINGS

PARAMETER

RATING

Supply Voltage to V

Potential

0.5 V to 7 V

Signal Pin Voltage to V

Potential

0.5 V to V

+ 0.5 V (not to exceed 7 V)

DC Output Current

50 mA

Storage Temperature Range

C to 150

Power Dissipation (Package Limit)

1.0 W

DC Voltage Applied to Outputs In High-Z State

0.5 V to V

+ 0.5 V (not to exceed 7 V)

NOTES:
1.

Stresses greater than those listed under `Absolute Maximum Ratings' may cause permanent damage to the device.
This is a stress rating for transient conditions only. Functional operation of the device at these or any other conditions
outside of those indicated in the `Operating Range' of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.

Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle.

Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time.

OPERATING RANGE

SYMBOL

PARAMETER

MIN

MAX

UNIT

Temperature, Ambient

Supply Voltage

4.5

5.5

Supply Voltage

Logic LOW Input Voltage

0 .5

0.8

Logic HIGH Input Voltage

2.0

+ 0.5

NOTE:

Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle.

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Input Leakage Current

= 5.5 V, V

= 0 V to V

Output Leakage Current

, 0 V

OUT

Output HIGH Voltage

= 2 .0 mA

2.4

Output LOW Voltage

= 8.0 mA

0.4

Average Supply Current

Measured at f = 40 MHz

100

CC2

Average Standby Current

All Inputs = V

CC3

Power Down Current

All Inputs = V

0.2 V

NOTE:

, I

CC2

, and I

CC3

are dependent upon actual output loading and cycle rates. Specified values are with outputs open.

LH540203

CMOS 2048

9 Asynchronous FIFO

AC ELECTRICAL CHARACTERISTICS

(Over Operating Range)

SYMBOL

PARAMETER

= 15 ns

= 20 ns

= 25 ns

= 35 ns

= 50 ns

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN MAX

READ CYCLE TIMING

Read Cycle Time

Access Time

Read Recovery Time

RPW

Read Pulse Width

RLZ

Data Bus Active from Read LOW

WLZ

Data Bus Active from Write HIGH

3,4

Data Valid from Read Pulse HIGH

RHZ

Data Bus High-Z from Read HIGH

WRITE CYCLE TIMING

Write Cycle Time

WPW

Write Pulse Width

Write Recovery Time

Data Setup Time

Data Hold Time

RESET TIMING

RSC

Reset Cycle Time

Reset Pulse Width

RSR

Reset Recovery Time

RRSS

Read HIGH to RS HIGH

WRSS

Write HIGH to RS HIGH

RETRANSMIT TIMING

RTC

Retransmit Cycle Time

Retransmit Pulse Width

RTR

Retransmit Recovery Time

FLAG TIMING

EFL

Reset LOW to Empty Flag LOW

HFH,FFH

Reset LOW to Half-Full and Full
Flags HIGH

REF

Read LOW to Empty Flag LOW

RFF

Read HIGH to Full Flag HIGH

WEF

Write HIGH to Empty Flag HIGH

WFF

Write LOW to Full Flag LOW

WHF

Write LOW to Half-Full Flag LOW

RHF

Read HIGH to Half-Full Flag HIGH

EXPANSION TIMING

XOL

Expansion Out LOW

XOH

Expansion Out HIGH

Expansion In Pulse Width

XIR

Expansion In Recovery Time

XIS

Expansion in Setup Time

NOTES:

1. All timing measurements are performed at `AC Test Condition' levels.
2. Pulse widths less than minimum value are not allowed.

LH540203

CMOS 2048

9 Asynchronous FIFO

ORDERING INFORMATION

15
20
25
35
50

LH540203

Device Type

Package

- ##

Speed

540203MD

CMOS 2048 x 9 FIFO

Example: LH540203U-25 (CMOS 2048 x 9 FIFO, 32-pin PLCC, 25 ns)

Access Time (ns)

D 28-pin, 300-mil Plastic DIP (DIP28-W-300)
K 28-pin, 300-mil SOJ * (SOJ28-P-300)
U 32-pin Plastic Leaded Chip Carrier (PLCC32-P-R450)

* Contact a Sharp representative for availability of SOJ package.

1.27 [0.050]

4 SIDES BSC

14.05 [0.553]
13.89 [0.547]

15.11 [0.595]
14.86 [0.585]

11.51 [0.453]
11.35 [0.447]

12.57 [0.495]
12.32 [0.485]

3.56 [0.140]
3.12 [0.123]

2.41 [0.095]
1.52 [0.060]

0.81 [0.032]
0.66 [0.026]

0.53 [0.021]
0.33 [0.013]

32PLCC

MAXIMUM LIMIT

MINIMUM LIMIT

DIMENSIONS IN MM (INCHES)

0.38 [0.015]

MIN

DETAIL

10.92 [0.430]

9.91 [0.390]

13.46 [0.530]
12.45 [0.490]

0.10 [0.004]

32PLCC (PLCC32-P-R450)

32-pin, 450-mil PLCC

CMOS 2048

9 Asynchronous FIFO

LH540203

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