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LH543611/21

FEATURES

··

Pin-Compatible and Functionally
Upwards-Compatible with Sharp LH5420 and
LH543601, but Deeper

··

Expanded Control Register that is Fully
Readable as well as Writeable

··

Fast Cycle Times: 18/20/25/30/35 ns

··

Improved Input Setup and Flag Out Timing

··

Two 512

36-bit FIFO Buffers (LH543611) or

Two 1024

36-bit FIFO Buffers (LH543621)

··

Full 36-bit Word Width

··

Selectable 36/18/9-bit Word Width on Port B;
Selection May be Changed Without Resetting
the BiFIFO

··

Programmable Byte-Order Reversal
`Big-Endian

Little-Endian Conversion'

··

Independently-Synchronized (`Fully-Asynchronous')
Operation of Port A and Port B

··

`Synchronous' Enable-Plus-Clock Control at
Both Ports

··

R/W, Enable, Request, and Address Control Inputs
are Sampled on the Rising Clock Edge

··

Synchronous Request/Acknowledge `Handshake'
Capability; Use is Optional

··

Device Comes Up Into a Known Default State at
Reset; Programming is Allowed, but is not Required

··

Asynchronous Output Enables

··

Five Status Flags per Port: Full, Almost-Full,
Half-Full, Almost-Empty, and Empty

··

All Flags are Independently Programmable for
Either Synchronous or Asynchronous Operation

··

Almost-Full Flag and Almost-Empty Flag Have
Programmable Offsets

··

Mailbox Registers with Synchronized Flags

··

Data-Bypass Function

··

Data-Retransmit Function

··

Automatic Byte Parity Checking with
Programmable Parity Flag Latch

··

Programmable Byte Parity Generation

··

Programmable Byte, Half-Word, or Full-Word
Oriented Parity Operations

··

8 mA-I

High-Drive Three-State Outputs with

Built-In Series Resistor

··

TTL/CMOS-Compatible I/O

··

Space-Saving PQFP and TQFP Packages

FUNCTIONAL DESCRIPTION

The LH543611 and LH543621 contain two FIFO buff-

ers, FIFO #1 and FIFO #2. These operate in parallel, but
in opposite directions, for bidirectional data buffering.
FIFO #1 and FIFO #2 each are organized as 512 or 1024
by 36 bits. The LH543611 and LH543621 are ideal either
for wide unidirectional applications or for bidirectional
data applications; component count and board area are
reduced.

The LH543611 and LH543621 have two 36-bit ports,

Port A and Port B. Each port has its own port-synchro-
nous clock, but the two ports may operate asynchro-
nously relative to each other. Data flow is initiated at a port
by the rising edge of the appropriate clock; it is gated by
the corresponding edge-sampled enable, request, and
read/write control signals. At the maximum operating
frequency, the clock duty cycle may vary from 40% to
60%. At lower frequencies, the clock waveform may be
quite asymmetric, as long as the minimum pulse-width
conditions for clock-HIGH and clock-LOW remain satis-
fied; the LH543611 and LH543621 are fully-static parts.

Conceptually, the port clocks CK

and CK

are free-

running, periodic `clock' waveforms, used to control other
signals which are edge-sensitive. However, there actually
is not any absolute requirement that these `clock' wave-
forms must be periodic. An `asynchronous' mode of op-
e ration is p os sib le, in o ne o r bo th direc tio ns,
independently, if the appropriate enable and request in-
puts are continuously asserted, and enough aperiodic
`clock' pulses of suitable duration are generated by exter-
nal logic to cause all necessary actions to occur.

A synchronous request/acknowledge handshake

facility is provided at each port for FIFO data access. This
request/ acknowledge handshake resolves FIFO full and
empty boundary conditions, when the two ports are op-
erated asynchronously relative to each other.

FIFO status flags monitor the extent to which each

FIFO buffer has been filled. Full, Almost-Full, Half-Full,
Almost-Empty, and Empty flags are included for

each

FIFO. Each of these flags may be independently pro-
grammed for either synchronous or asynchronous opera-
tion. Also, the Almost-Full and Almost-Empty flags are
programmable over the entire FIFO depth, but are auto-
matically initialized to eight locations from the respective
FIFO boundaries at reset. A data block of 512 (LH543611)
or 1024 (LH543621) or fewer words may be retransmitted
any desired number of times.

512

2 / 1024

Synchronous Bidirectional FIFO

BOLD = Additions over the 5420/3601 feature set

Two mailbox registers provide a separate path for

passing control words or status words between ports.
Each mailbox has a New-Mail-Alert Flag, which is syn-
chronized to the reading port's clock. This mailbox func-
tion facilitates the synchronization of data transfers
between asynchronous systems.

Data-bypass mode allows Port A to directly transfer

data to or from Port B at reset. In this mode, the device
acts as a registered transceiver under the control of
Port A. For instance, a master processor on Port A can
use the data bypass feature to send or receive initializa-
tion or configuration information directly, to or from a
peripheral device on Port B, during system startup.

A word-width-select option is provided on Port B for

36-bit, 18-bit, or 9-bit data access. This feature allows
word-width matching between Port A and Port B, with no
additional logic needed. It also ensures maximum utiliza-
tion of bus band widths. Subject to meeting timing require-
ments, the word-width selection may be changed at any
time during the operation of an LH543611 or LH543621,
without the need either for a reset operation or for passing
dummy words through Port B immediately after the

change; except that if the change is not made at a
full-word boundary, at least one dummy word must be
passed through Port B before any actual data words
are transmitted.

A Byte Parity Check Flag at each port monitors data

integrity. Control-Register bit 00 (zero) selects the parity
mode, odd or even. This bit is initialized for odd data parity
at reset; but it may be reprogrammed for even parity, or
back again to odd parity, as desired. The parity flags may
be programmed to operate either in a latched mode or in
a flowthrough mode. The parity checking may be per-
formed over 36-bit full-words, over 18-bit half-words, or
over 9-bit single bytes.

Parity generation may be selected as well as parity

checking, and may likewise be performed over full-words
or half-words or single bytes. In any case, a parity bit of
the proper mode is generated over the least-significant
eight bits of a byte, and then is stored in the most-signifi-
cant bit position of the byte as it passes through the
LH543611/21, overwriting whatever bit was present in
that bit position previously.

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

116

115
114
113
112

111

110
109
108
107
106
105
104
103
102

101

100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84

19
20
21
22

23
24
25
26
27
28
29
30
31
32

33
34

36
37
38
39

41
42
43
44
45
46
47
48

CCO

10A

SSO

10B

11B

CCO

SSO

CCO

SSO

CCO

49
50

CCO

24A

25A

26A

SSO

27A

28A

29A

30A

31A

32A

33A

34A

35A

35B

34B

33B

32B

31B

30B

29B

28B

27B

26B

25B

CCO

SSO

CCO

SSO

CCO

Pin 1

Pin 132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

12A

13A

14A

SSO

15A

16A

17A

R/W

ACK

MBF

18A

19A

20A

21A

22A

REQ

SSO

11A

12B

13B

14B

SSO

15B

16B

17B

REQ

R/W

18B

19B

20B

21B

22B

SSO

MBF

ACK

543611-1

TOP VIEW

CHAMFERED

EDGE

132-PIN PQFP

Figure 1. Pin Connections for 132-Pin PQFP Package

(Top View)

PIN CONNECTIONS

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

19
20
21
22
23
24
25
26
27
28
29
30
31

24A

25A

27A

28A

30A

31A

33A

34B

33B

31B

30B

28B

27B

32
33

128

127

CCO

10A

SSO

CCO

SSO

CCO

SSO

10B

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

23A

22A

21A

SSO

19A

18A

ACK

REQ

R/W

17A

15A

SSO

14A

13A

24B

23B

SSO

22B

20B

R/W

REQ

ACK

MBF

16B

SSO

17B

15B

14B

TOP VIEW

MBF

543611-2

34
35
36

CCO

11B

CCO

75
74
73

111

110

12A

11A

109

13B

12B

CCO

26A

SSO

29A

CCO

32A

SSO

34A

35A

SSO

32B

CCO

29B

SSO

26B

25B

21B

19B

18B

20A

16A

35B

144-PIN TQFP

SSO

CCO

SSO

Figure 2. Pin Connections for 144-Pin TQFP Package

(Top View)

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

PIN LIST

SIGNAL

NAME

PQFP

PIN NO.

TQFP

PIN NO.

126

125

124

123

121

120

119

118

17A

117

16A

116

15A

115

14A

113

13A

112

12A

111

11A

110

10A

106

105

104

102

101

100

10B

11B

12B

13B

14B

15B

16B

17B

MBF

SIGNAL

NAME

PQFP

PIN NO.

TQFP

PIN NO.

ACK

REQ

R/W

18B

19B

20B

21B

22B

23B

24B

25B

26B

27B

28B

29B

30B

31B

32B

33B

34B

35B

100

35A

101

34A

102

33A

103

32A

105

31A

106

30A

107

29A

109

28A

110

27A

111

26A

113

25A

114

24A

115

23A

117

143

22A

118

142

21A

119

141

SIGNAL

NAME

PQFP

PIN122 NO.

TQFP

PIN NO.

20A

120

140

19A

122

138

18A

123

137

MBF

124

136

125

135

126

134

ACK

127

133

REQ

129

131

130

R/W

131

129

132

128

122

SSO

114

SSO

109

CCO

108

CCO

107

SSO

103

CCO

SSO

CCO

SSO

CCO

SSO

CCO

SSO

CCO

SSO

104

CCO

108

SSO

112

CCO

116

CCO

SSO

144

SSO

121

139

128

132

127

NOTE:

PINS

COMMENTS

Supply internal logic. Connected to each other.

CCO

Supply output drivers only. Connected to each
other.

PINS

COMMENTS

Supply internal logic. Connected to each other.

SSO

Supply output drivers only. Connected to each
other.

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

RESET

LOGIC

PORT A

I/O

PORT A

SYNCH-

RONOUS

CONTROL

LOGIC

READ

POINTER

WRITE

POINTER

FIXED AND

PROGRAMMABLE

STATUS FLAGS

FIFO #1

MEMORY ARRAY

512 x 36 / 1024 x 36

MAILBOX

READ

POINTER

WRITE

POINTER

FIFO #2

MEMORY ARRAY

512 x 36 / 1024 x 36

PORT B

I/O

, WS

- D

35A

ACK

REQ

R/W

- D

35B

ACK

REQ

R/W

COMMAND

PORT AND
REGISTER

RESOURCE

REGISTERS

PARITY

CHECKING

AND

GENERATION

COMMAND

PORT AND
REGISTER

MAILBOX

BYPASS

MBF

PORT B

SYNCH-

RONOUS

CONTROL

LOGIC

FIXED AND

PROGRAMMABLE

STATUS FLAGS

543611-4

PARITY

CHECKING

AND

GENERATION

Figure 3b. Detailed LH543611/21 Block Diagram

FIFO 1

PORT A

I/O

FIFO 2

PORT B

I/O

WRITE

READ

WRITE

READ

PORT A

CONTROL

PORT B

CONTROL

543611-3

Figure 3a. Simplified LH543611/21 Block Diagram

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

PIN DESCRIPTIONS

PIN

PIN TYPE

DESCRIPTION

GENERAL

, V

Power, Ground

Reset

PORT A

Port A Free-Running Clock

R/W

Port A Edge-Sampled Read/Write Control

Port A Edge-Sampled Enable

, A

Port A Edge-Sampled Address Pins

Port A Level-Sensitive Output Enable

REQ

Port A Request/Enable

FIFO #2 Retransmit

35A

I/O/Z

Port A Bidirectional Data Bus

FIFO #1 Full Flag (Write Boundary)

FIFO #1 Programmable Almost-Full Flag (Write Boundary)

FIFO #1 Half-Full Flag

FIFO #2 Programmable Almost-Empty Flag (Read Boundary)

FIFO #2 Empty Flag (Read Boundary)

MBF

New-Mail-Alert Flag for Mailbox #2

Port A Parity Flag

ACK

Port A Acknowledge

PORT B

Port B Free-Running Clock

R/W

Port B Edge-Sampled Read/Write Control

Port B Edge-Sampled Enable

Port B Edge-Sampled Address Pin

Port B Level-Sensitive Output Enable

, WS

Port B Word-Width Select

REQ

Port B Request/Enable

FIFO #1 Retransmit

35B

I/O/Z

Port B Bidirectional Data Bus

FIFO #2 Full Flag (Write Boundary)

FIFO #2 Programmable Almost-Full Flag (Write Boundary)

FIFO #2 Half-Full Flag

FIFO #1 Programmable Almost-Empty Flag (Read Boundary)

FIFO #1 Empty Flag (Read Boundary)

MBF

New-Mail-Alert Flag for Mailbox #1

Port B Parity Flag

ACK

Port B Acknowledge

NOTE:
1.

I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

ABSOLUTE MAXIMUM RATINGS

PARAMETER

RATING

Supply Voltage to V

Potential

0.5 V to 7 V

Signal Pin Voltage to V

Potential

0.5 V to V

+ 0.5 V

DC Output Current

40 mA

Storage Temperature Range

C to 150

Power Dissipation (Package Limit)

2 Watts (Quad Flat Pack)

NOTES:

Stresses greater than those listed under `Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress rating for
transient conditions only. Functional operation of the device at these or any other conditions outside those indicated in the `Operating Range'
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time.

Negative undershoot of 1.5 V in amplitude is permitted for up to 10 ns, once per cycle.

OPERATING RANGE

SYMBOL

PARAMETER

MIN

MAX

UNIT

Temperature, Ambient

Vcc

Supply Voltage

4.5

5.5

Vss

Supply Voltage

Logic LOW
Input Voltage

0.5

0.8

Logic HIGH
Input Voltage

2.2

Vcc + 0.5

NOTE:
1.

Negative undershoot of 1.5 V in amplitude is permitted
for up to 10 ns, once per cycle.

DC ELECTRICAL CHARACTERISTICS (OVER OPERATING RANGE)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input Leakage Current

= 5.5 V, V

= 0 V To V

I/O Leakage Current

, 0 V

OUT

Logic LOW Output Voltage

= 8.0 mA

0.4

Logic HIGH Output Voltage

= 8 .0 mA

2.4

Average Supply Current

1, 2

Measured at f

= MAX

180

280

CC2

Average Standby Supply
Current

1, 3

All Inputs = V

IHMIN

(Clocks idle)

CC3

Power-Down Supply
Current

All Inputs = V

0.2 V (Clocks idle)

0.002

CC4

Power-Down Supply
Current

1, 3

All Inputs = V

0.2 V

(Clocks running at f

= MAX)

NOTES:

, I

CC2

, I

CC3

, and I

CC4

are dependent upon actual output loading, and I

, I

CC4

are also dependent on cycle rates. Specified values are with

outputs open (for I

: C

= 0 pF); and, for I

and I

CC4

, operating at minimum cycle times.

(MAX.) using V

= MAX = 5.5 V and `worst case' data pattern. I

(TYP.) using V

= 5 V and `average' data pattern.

CC2

(TYP.) and I

CC4

(TYP.) using V

= 5 V and T

= 25°C.

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

AC TEST CONDITIONS

PARAMETER

RATING

Input Pulse Levels

to 3 V

Input Rise and Fall Times
(10% to 90%)

5 ns

Output Reference Levels

1.5 V

Input Timing Reference Levels

1.5 V

Output Load, Timing Tests

Figure 5

CAPACITANCE

1,2

PARAMETER

RATING

(Input Capacitance)

8 pF

OUT

(Output Capacitance)

8 pF

NOTES:
1.

Sample tested only.

Capacitances are maximum values at 25

C, measured at 1.0 MHz, with V

= 0 V.

543611-14

+5 V

470

240

DEVICE

UNDER

TEST

30 pF

NOTE:

= Includes jig and scope capacitances

Figure 4. Output Load Circuit

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

AC ELECTRICAL CHARACTERISTICS

= 5 V

+10%, T

= 0

C to 70

SYMBOL

DESCRIPTION

18

20

25

30

35

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Clock Cycle Frequency

28.5

MHz

Clock Cycle Time

Clock HIGH Time

Clock LOW Time

Data Setup Time

7.5

Data Hold Time

0.5

Enable Setup Time

5.5

7.5

8.5

10.5

Enable Hold Time

0.5

RWS

Read/Write Setup Time

5.5

7.5

8.5

10.5

RWH

Read/Write Hold Time

0.5

RQS

Request Setup Time

5.5

7.5

8.5

10.5

RQH

Request Hold Time

0.5

Address Setup Time

7.5

Address Hold Time

0.5

WSS

Width Select Setup Time

5.5

7.5

8.5

10.5

WSH

Width Select Hold Time

0.5

Data Output Access Time

13.8

ACK

Acknowledge Access Time

9.5

Output Hold Time

Output Enable Time, OE LOW to
D

Low-Z

1.5

Output Disable Time, OE HIGH
to D

High-Z

Clock to EF Flag Valid

14.5

Clock to FF Flag Valid

14.5

Clock to HF Flag Valid

14.5

Clock to AE Flag Valid

14.5

Clock to AF Flag Valid

14.5

MBF

Clock to MBF Flag Valid

Data to Parity Flag Valid

Reset/Retransmit Pulse Width

RSS

Reset/Retransmit Setup Time

RSH

Reset/Retransmit Hold Time

7.2

Reset LOW to Flag Valid

FRL

First Read Latency

FWL

First Write Latency

Bypass Data Setup

8.5

Bypass Data Hold

Bypass Data Access

15.5

SKEW1

Skew Time Read-to-Write Clock

14.5

SKEW2

Skew Time Write-to-Read Clock

14.5

NOTES:
1.

Timing measurements performed at `AC Test Condition' levels.

, t

address setup times and hold times need only be satisfied at clock edges which occur while the corresponding enables are being as-

serted.

Values are guaranteed by design; not currently production tested.

Measured with Parity Flag operating in flowthrough mode.

When CK

or CK

is enabled; t

= t

RSS

+ t

RSH

RSS

and/or t

RSH

need not be met unless a rising edge of CK

occurs while EN

is being asserted, or else a rising edge of CK

occurs while

is being asserted.

FRL

is the minimum first-write-to-first-read delay, following an empty condition, which is required to assure valid read data.

FWL

is the minimum first-read-to-first-write delay, following a full condition, which is required to assure successful writing of data.

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

OPERATIONAL DESCRIPTION

Reset

The device is reset whenever the asynchronous Reset

(RS) input is taken LOW, and at least one rising edge and
one falling edge of both CK

and CK

occur while RS is

LOW. A reset operation is required after power-up, before
the first write operation may occur. The LH543611/21 is
fully ready for operation after being reset. No device
programming is required if the default states described
below are acceptable.

A reset operation initializes the read-address and

write-address pointers for FIFO #1 and FIFO #2 to those
FIFO's first physical memory locations. If the respective
outputs are enabled, the initial contents of these first
locations appear at the outputs. FIFO and mailbox status
flags are updated to indicate an empty condition. In
addition, the programmable-status-flag offset values are
initialized to eight. Thus, the AE

/AE

flags get asserted

within eight locations of an empty condition, and the
AF

/AF

flags likewise get asserted within eight locations

of a full condition, for FIFO #1/FIFO #2 respectively.

Bypass Operation

During reset (whenever RS is LOW) the device acts

as a registered transceiver, bypassing the internal FIFO
memories. Port A acts as the master port. A write or read
operation on Port A during reset transfers data directly to
or from Port B. Port B is considered to be the slave, and
cannot perform write or read operations independently on
its own during reset.

The direction of the bypass data transmission is deter-

mined by the R/W

control input, which does not get

overridden by the RS input. Here, a `write' operation
means passing data from Port A to Port B, and a `read'
operation means passing data from Port B to Port A.

The bypass capability may be used to pass initializa-

tion or configuration data directly between a master proc-
essor and a peripheral device during reset.

Address Modes

Address pins select the device resource to be

accessed by each port. Port A has three resource-regis-
ter-select inputs, A

, A

1A,

and A

, which select between

FIFO access, mailbox-register access, control-register
access, and programmable flag-offset-value-register ac-
cess. Port B has a single address input, A

, to select

between FIFO access or mailbox-register access.

The status of the resource-register-select inputs is

sampled at the rising edge of an enabled clock (CK

). Resource-register select-input address definitions

are summarized in Table 1.

Table 1. Resource-Register Addresses

RESOURCE

PORT A

FIFO

Mailbox

, AE

, AF

, AE

Flag Offsets

Control Register Flag-
Synchronization and Parity
Operating Mode

Flag Offset Register

RESOURCE

PORT B

FIFO

Mailbox

Control Register

The eighteen Control-Register bits govern the syn-

chronization mode of the fullness-status flags at each
port, the choice of odd or even parity at both ports, the
enabling of parity generation for data flow at each port,
the optional latching behavior of the parity-error flags at
each port, and the selection of a full-word or half-word or
single-byte field for parity checking. A reset operation
initi alizes the LH543611/21 Control Register for
LH5420/LH543601-compatible operation, but it may be
reprogrammed at will at any time during LH543611/21
operation.

FIFO Write

Port A writes to FIFO #1, and Port B writes to FIFO #2.

A write operation is initiated on the rising edge of a clock
(CK

or CK

) whenever: the appropriate enable (EN

) is held HIGH; the appropriate request (REQ

REQ

) is held HIGH; the appropriate Read/Write control

(R/W

or R/W

) is held LOW; the FIFO address is

selected for the address inputs (A

or A

); and

the prescribed setup times and hold times are observed
for all of these signals. Setup times and hold times must
also be observed on the data-bus pins (D

35A

35B

Normally, the appropriate Output Enable signal (OE

or OE

) is HIGH, to disable the outputs at that port, so

that the data word present on the bus from external
sources gets stored. However, a `loopback' mode of
operation also is possible, in which the data word supplied
by the outputs of one internal FIFO is `turned around' at
the port and read back into the other FIFO. In this mode,
the outputs at the port are not disabled. To remain within
specification for all timing parameters, the Clock Cycle
Frequency must be reduced slightly below the value

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

which otherwise would be permissible for that speed
grade of LH543611/21.

When a FIFO full condition is reached, write operations

are locked out. Following the first read operation from a
full FIFO, another memory location is freed up, and the
corresponding Full Flag is deasserted (FF = HIGH). The
first write operation should begin no earlier than a First
Write Latency (t

FWL

) after the first read operation from a

full FIFO, to ensure that correct read data are retrieved.
(See Figures 33 and 34.)

FIFO Read

Port A reads from FIFO #2, and Port B reads from FIFO

#1. A read operation is initiated on the rising edge of a
clock (CK

or CK

) whenever: the appropriate enable

(EN

or EN

) is held HIGH; the appropriate request

(REQ

o r R EQ

) is held HIGH; the appropri ate

Read/Write control (R/W

o r R/W

) is held HIGH;

the FIFO address is selected for the address inputs
(A

or A

); and the prescribed setup times and

hold times are observed for all of these signals. Read data
becomes valid on the data-bus pins (D

35A

35B

) by a time t

after the rising clock (CK

) edge, provided that the data outputs are enabled.

and OE

are assertive-LOW, asynchronous, Out-

put Enable control input signals. Their effect is only to
enable or disable the output drivers of the respective port.
Disabling the outputs does

not disable a read operation;

data transmitted to the corresponding output register will
remain available later, when the outputs again are en-
abled, unless it subsequently is overwritten.

When an empty condition is reached, read operations

are locked out until a valid write operation(s) has loaded
additional data into the FIFO. Following the first write to
an empty FIFO, the corresponding empty flag (EF) will be
deasserted (HIGH). The first read operation should begin
no earlier than a First Read Latency (t

FRL

) after the first

write to an empty FIFO, to ensure that correct read data
words are retrieved. (See Figures 31 and 32.)

Dedicated FIFO Status Flags

Six dedicated FIFO status flags are included for Full

(FF

and FF

), Half-Full (HF

and HF

), and Empty (EF

and EF

). FF

, HF

, and EF

indicate the status of FIFO

#1; and FF

, HF

, and EF

indicate the status of FIFO #2.

A Full Flag is asserted following the first subsequent

rising clock edge for a write operation which fills the FIFO.
A Full Flag is deasserted following the first subsequent
falling clock edge for a read operation to a full FIFO. A
Half-Full Flag is updated following the first subsequent
rising clock edge of a read or write operation to a FIFO
which changes its `half-full' status. An Empty Flag is
asserted following the first subsequent rising clock edge
for a read operation which empties the FIFO. An Empty
Flag is deasserted following the falling clock edge for a
write operation to an empty FIFO.

Programmable Status Flags

Four programmable FIFO status flags are provided,

two for Almost-Full (AF

and AF

), and two for Almost-

Empty (AE

and AE

). Thus, each port has two program-

mable flags to monitor the status of the two internal FIFO
buffer memories. The offset values for these flags are
initialized to eight locations from the respective FIFO
boundaries during reset, but can be reprogrammed over
the entire FIFO depth.

An Almost-Full Flag is asserted following the first sub-

sequent rising clock edge after a write operation which
has partially filled the FIFO up to the `almost-full' offset
point. An Almost-Full Flag is deasserted following the first
subsequent falling clock edge after a read operation
which has partially emptied the FIFO down past the
`almost-full' offset point. An Almost-Empty Flag is
asserted following the first subsequent rising clock edge
after a read operation which has partially emptied
the FIFO down to the `almost-empty' offset point. An
Almost-Empty Flag is deasserted following the first sub-
sequent falling clock edge after a write operation which
has partially filled the FIFO up past the `almost-empty'
offset point.

Flag offsets may be written or read through the Port A

data bus. All four programmable FIFO status flag offsets
can be set simultaneously through a single 36-bit status
word; or, each programmable flag offset can be set indi-
vidually, through one of four nine-bit (LH543611) or ten-bit
(LH543621) status words. Tables 3a and 3b illustrate the
data format for flag-programming words. Note that when
all four offsets are set simultaneously in an LH543621,
the settings are limited to magnitudes expressible in nine
bits; for larger offset values, the individual setting option
must be used. (See Figure 3b.)

Also, Tables 4a and 4b define the meaning of each of

the five flags, both the dedicated flags and the program-
mable flags, for the LH543611 and LH543621 respec-
tively.

NOTE: Control inputs which may affect the computation
of flag values at a port generally should not change while
the clock for that port is HIGH, since some updating of
flag values takes place on the

falling edge of the clock.

Mailbox Operation

Two mailbox registers are provided for passing system

hardware or software control/status words between ports.
Each port can read its own mailbox and write to the other
port's mailbox. Mailbox access is performed on the rising
edge of the controlling FIFO's clock, with the mailbox
address selected and the enable (EN

or EN

) HIGH.

That is, writing to Mailbox Register #1, or reading from
Mailbox Register #2, is synchronized to CK

; and writing

to MailboxRegister #2, or reading from Mailbox Register
#1, is synchronized to CK

The R/W

A/B

and OE

A/B

pins control the direction and

availability of mailbox-register accesses. Each mailbox
register has its own New-Mail-Alert Flag (MBF

and

OPERATIONAL DESCRIPTION (cont'd)

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

MBF

), which is synchronized to the reading port's clock.

These New-Mail-Alert Flags are status indicators only,
and cannot inhibit mailbox-register read or write operations.

Request Acknowledge Handshake

A synchronous request-acknowledge handshake fea-

ture is provided for each port, to perform boundary syn-
chronization between asynchronously-operated ports.
The use of this feature is optional. When it is used, the
Request input (REQ

A/B

) is sampled at a rising clock edge.

With REQ

A/B

HIGH, R/W

A/B

determines whether a FIFO

read operation or a FIFO write operation is being re-
quested. The Acknowledge output (ACK

A/B

) is updated

during the following clock cycle(s). ACK

A/B

meets the

setup and hold time requirements of the Enable input
(EN

or EN

). Therefore, ACK

A/B

may be tied back to the

enable input to directly gate FIFO accesses, at a slight
decrease in maximum operating frequency.

The assertion of ACK

A/B

signifies that REQ

A/B

was

asserted. However, ACK

A/B

does not depend logically on

A/B

; and thus the assertion of ACK

A/B

does

not prove

that a FIFO write access or a FIFO read access actually
took place. While REQ

A/B

and EN

A/B

are being held

HIGH, ACK

A/B

may be considered as a synchronous,

predictive boundary flag. That is, ACK

A/B

acts as a

synchronized predictor of the Almost-Full Flag AF for write
operations, or as a synchronized predictor of the Almost-
Empty Flag AE for read operations.

Outside the `almost-full' region and the `almost-empty'

region, ACK

A/B

remains continuously HIGH whenever

REQ

A/B

is held continuously HIGH. Within the `almost-full'

region or the `almost-empty' region, ACK

A/B

occurs only

on every

third cycle, to prevent an overrun of the FIFO's

actual full or empty boundaries and to ensure that the t

FWL

(first write latency) and t

FRL

(first read latency) specifica-

tions are satisfied before ACK

A/B

is received.

The `almost-full region' is defined as `that region, where

the Almost-Full Flag is being asserted'; and the `almost-
empty region' as `that region, where the Almost-Empty
Flag is being asserted.' Thus, the extent of these `almost'
regions depends on how the system has programmed the
offset values for the Almost-Full Flags and the Almost-
Empty Flags. If the system has

not programmed them,

then these offset values remain at their default values,
eight in each case.

If a write attempt is unsuccessful because the corre-

sponding FIFO is full, or if a read attempt is unsuccessful
because the corresponding FIFO is empty, ACK

A/B

not

asserted in response to REQ

A/B

If the REQ/ACK handshake is not used, then the

REQ

A/B

input may be used as a second enable input, at

a possible minor loss in maximum operating speed. In this
case, the ACK

A/B

output may be ignored.

WARNING: Whether or not the REQ/ACK handshake is
being used, the REQ

A/B

input for a port

must be asserted

for that port to function at all for FIFO, mailbox, or data-
bypass operation.

Data Retransmit

A retransmit operation resets the read-address pointer of

the corresponding FIFO (#1 or #2) back to the first FIFO
physical memory location, so that data may be reread. The
write pointer is not affected. The status flags are updated;
and a block of up to 512 or 1024 data words, which
previously had been written into and read from a FIFO, can
be retrieved. The block to be retransmitted is bounded by
the first FIFO memory location, and the FIFO memory
location addressed by the write pointer. FIFO #1 retransmit
is initiated by strobing the RT

pin LOW. FIFO #2 retransmit

is initiated by strobing the RT

pin LOW. Read and write

operations to a FIFO should be stopped while the corre-
sponding Retransmit signal is being asserted.

Parity Checking

The Parity Check Flags, PF

and PF

, are asserted

(LOW) whenever there is a parity error in the data word
present on the Port A data bus or the Port B data bus
respectively. The inputs to the parity-evaluation logic
come directly (via isolation transistors) from the data-bus
bonding

pads, in each case. Thus, PF

and PF

provide

parity-error indications for whatever 36-bit words are
present at Port A and Port B respectively, regardless of
whether those words originated within the LH543611/21
or in the external system.

The four bytes of a 36-bit data word are grouped as

, D

, and D

. The parity of

each nine-bit byte is individually checked, and the four
single-bit parity indications are logically ORed and inverted
to produce the Parity-Flag output.

If the Parity Policy bit (Control-Register bit 09) is HIGH,

then parity at Port B will be computed over the field
defined by the Word-Width Selection control inputs WS

and WS

, and then may be for full-words, for half-words,

or for single bytes. Otherwise, parity will be computed
over full-words regardless of the setting of WS

and WS

Parity checking is initialized for odd parity at reset, but

can be reprogrammed for even parity or for odd parity
during operation. Control-Register bit 00 (zero) selects
the parity mode, odd or even. (See Tables 3, 5, and 6, and
Figure 10.)

OPERATIONAL DESCRIPTION (cont'd)

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

All nine bits of each byte are treated alike by the parity

logic. The byte parity over the nine bits is compared with
the Parity Mode bit in the Control Register, to generate a
byte-parity-error indication. Then, the four byte-parity-
error signals are NORed together, to compute the asser-
tive-LOW parity-flag value. This value may pass through
to the output pin on a flowthrough basis, or it may be
latched, according to the setting of the Control-Register
latching bit for that port (bit 02 or bit 11). (See Figure 6 for
an example of parity checking.)

Parity Generation

Unlike parity checking, parity generation at a port

operates only when it is explicitly invoked by setting the
corresponding Control-Register bit for that port (bit 01 or
bit 10) HIGH. The presumed division of words into bytes
still remains the same as for parity checking. However, it
is no longer true that all nine bits of each byte are treated
alike; now, the most-significant bit of each byte is explicitly
designated as the parity bit for that byte. The parity-gen-
eration process records a new value into that bit position
for each byte passing through the port. (See Figure 6 for
an example of parity generation.)

If the Parity Policy bit (Control Register bit 09), is HIGH,

parity at Port B will be generated for full-words, for half-
words, or for single bytes according to the setting of the
Word-Width Selection control inputs WS

and WS

. Oth-

erwise, parity will be generated for full-words regardless
of the setting of WS

and WS

The parity bits generated may be even or odd, accord-

ing to the setting of Control-Register bit 00, which is the
same bit that governs their interpretation during parity
checking.

Word-Width Selection and Byte-Order Reversal on
Port B

The word width of data access on Port B is selected

by the WS

and WS

control inputs. WS

and WS

both

are tied HIGH for 36-bit access; they both are tied LOW
for single-byte access. For double-byte access, WS

tied LOW; WS

is tied HIGH for straight-through transmis-

sion of 36-bit words, or tied LOW for on-the-fly byte-order
reversal of the four bytes in the word (`big-endian

little-endian conversion'). (See Table 2a and 2b.)

In the single-byte-access or double-byte-access modes,

FIFO write operations on Port B essentially pack the data to
form 36-bit words, as viewed from Port A. Similarly, single-
byte or double-byte FIFO read operations on Port B essen-
tially unpack 36-bit words through a series of shift
operations. FIFO status flags are updated following the last
access which forms a complete 36-bit transfer.

Since the values for each status flag are computed by

logic directly associated with one of the two FIFO-memory
arrays, and not by logic associated with Port B,

the flag

values reflect the array fullness situation in terms of com-
plete 36-bit words, and not in terms of bytes or double bytes.

However, there is no such restriction for switching from

writing to reading, or from reading to writing, at Port B. As
long as t

RWS

, t

, and t

are satisfied, R/W

may change

state after

any single-byte or double-byte access, and not

only after a full 36-bit-word access.

Also, WS

and WS

may be changed between full-

words during FIFO operation, without the need for any
reset operation, or for passing any dummy words on
through in advance of real data. If such a change is made
other than at a full-word boundary, however, at least one
dummy word should be used.

Also, the word-width-matching feature continues to

operate properly in `loopback' mode.

Note that the programmable word-width-matching fea-

ture is

only supported for FIFO accesses. Mailbox and

Data Bypass operations do

not support word-width

matching between Port A and Port B. Tables 2a and 2b
and Figures 7, 8, and 9, summarize word-width selection
for Port B.

Table 2a. Port B Word-Width Selection

PORT B DATA WIDTH

36-Bit

36-Bit with

Byte-Order Reversal

18-Bit

9-Bit

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

543611-52

DA35

DA27

DA26

DA18

DA17

DA9

DA8

DA0

DB35

DB27

DB26

DB18

DB17

DB9

DB8

DB0

LH543611/21

B0
BYTE #1

B4
BYTE #5

B1
BYTE #2

B5
BYTE #6

B2
BYTE #3

B6
BYTE #7

B3
BYTE #4

B7
BYTE #8

INPUT

OUTPUT: WS[1:0]= 2 (HL)

CKA

CKB

. . .

.
. .

. . .

.
. .

. . .

B1
BYTE #2

B5
BYTE #6

B2
BYTE #3

B6
BYTE #7

B3
BYTE #4

B7
BYTE #8

B0
BYTE #1

B4
BYTE #5

. . .

Bus Example: IBM, Motorala, etc.

Bus Example: Intel, DEC, etc.

Figure 7. Example of 36-to-36 Byte Order Reversal

PARITY CHECKING

A/B

Output word:

100111100

000111100

100111000

000111000

Odd parity:

Parity of Bytes = 0110; (1 = Byte Parity Error) PF = L

Even parity:

Parity of Bytes = 1001; (1 = Byte Parity Error) PF = L

PARITY GENERATION

A/B

Input word:

100111100

000111100

100111000

000111000

Output, odd parity:

100111100

000111000

Output, even parity:

000111100

100111000

Figure 6. Example of Parity Checking and Generation

Table 2b. Bus Funneling/Defunneling *

DA[35:0]

WS = 3 (HH)

WS = 2 (HL)

WS = 1 (LH)

WS = 0 (LL)

DB[35:0]

DB[35:18] DB[17:0]

DB[35:9]

DB[8:0]

* NOTE: B0, B1, . . ., represent data bytes.

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

18-Bit Data Streams

36-Bit Data Stream

Bits 18-35
(2nd Halfword)

Bits 18-35

(2nd Halfword)

Bits 0-17

(1st Halfword)

Bits 0-17
(1st Halfword)

2nd Halfword, then 1st Halfword

1st Halfword, then 2nd Halfword

35A

18A

17A

35B

18B

17B

PORT

543611-15

Figure 8a. 36-to-18 Funneling Through FIFO #1

9-Bit Data Streams

36-Bit Data Stream

Bits 27-35
(4th Byte)

4th Byte, then 1st Byte, then 2nd Byte, then 3rd Byte

35A

27A

26A

18A

35B

27B

26B

18B

PORT

17A

17B

Bits 18-26
(3rd Byte)

Bits 9-17
(2nd Byte)

Bits 0-8
(1st Byte)

3rd Byte, then 4th Byte, then 1st Byte, then 2nd Byte

2nd Byte, then 3rd Byte, then 4th Byte, then 1st Byte

1st Byte, then 2nd Byte, then 3rd Byte, then 4th Byte

543611-16

Figure 8b. 36-to-9 Funneling Through FIFO #1

PORT B WORD-WIDTH SELECTION

NOTES:

The heavy black borders on register segments indicate the main
data path, suitable for most applications. Alternate paths feature
a different ordering of bytes within a word, at Port B.

The funneling process does not change the ordering of bits within
a byte. Halfwords (Figure 8a) or bytes (Figure 8b) are trans-
ferred in parallel form from Port A to Port B.

The word-width setting may be changed during system operation;

however, two clock intervals should be allowed for these signals
to settle, before again attempting to read D

35B

. Also, in-

complete data words may occur, when the word width is
changed from shorter to longer at an inappropriate point in the
data block passing through the FIFO.

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

18-Bit Data Stream

36-Bit Data Stream

Bits 18-35

(2nd Halfword)

Bits 0-17
(1st Halfword)

1st Halfword, then 2nd Halfword

35A

18A

17A

35B

18B

17B

PORT

543611-17

Figure 9a. 18-to-36 Defunneling Through FIFO #2

9-Bit Data Stream

36-Bit Data Stream

Bits 27-35
(4th Byte)

35A

27A

26A

18A

35B

27B

26B

18B

PORT

17A

17B

Bits 18-26
(3rd Byte)

Bits 9-17
(2nd Byte)

Bits 0-8
(1st Byte)

1st Byte, then 2nd Byte, then 3rd Byte, then 4th Byte

543611-18

Figure 9b. 9-to-36 Defunneling Through FIFO #2

PORT B WORD-WIDTH SELECTION

NOTES:

The heavy black borders on register segments indicate the only
data paths used. The other byte segments of Port B do not par-
ticipate in the data path during defunneling.

The defunneling process does not change the ordering of bits
within a byte. Halfwords (Figure 9a) or bytes (Figure 9b) are
transferred in parallel form from Port B to Port A.

The word-width setting may be changed during system operation;

however, two clock intervals should be allowed for these signals
to settle, before again attempting to send data. Also, incomplete
data words may occur, when the word width is changed from
shorter to longer at an inappropriate point in the data block pass-
ing through the FIFO.

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

Table 3a. LH543611 Resource-Register Programming

RESOURCE-

REGISTER

ADDRESS

RESOURCE-REGISTER CONTENTS

NORMAL FIFO OPERATION

35A

X...

...X

MAILBOX

35A

X...

...X

, AE

, AF

, AE

FLAG REGISTER (36-BIT MODE)

35A

. . . D

27A

26A

. . . D

18A

17A

. . . D

Offset

CONTROL REGISTER: FLAG SYNCHRONIZATION, PARITY CONFIGURATION

35A

18A

17A

X...

...X

Port B Control

Port A Control

9-BIT AE

FLAG OFFSET REGISTER

35A

. . . D

X...

...X

Offset

9-BIT AF

FLAG OFFSET REGISTER

35A

. . . D

X...

..X

Offset

9-BIT AE

FLAG OFFSET REGISTER

35A

. . . D

X...

...X

Offset

9-BIT AF

FLAG OFFSET REGISTER

35A

. . . D

X...

...X

Offset

NOTES:

All four programmable-flag-offset values are initialized to eight (8) during a reset operation.

Parity Mode: Odd parity = HIGH; even parity = LOW. The parity mode is initialized to odd during a reset operation.

See Tables 5 and 6 and Figure 10 for the detailed format of the Control Register word.

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

Table 3b. LH543621 Resource-Register Programming

RESOURCE-

REGISTER

ADDRESS

RESOURCE-REGISTER CONTENTS

NORMAL FIFO OPERATION

35A

X...

...X

MAILBOX

35A

X...

...X

, AE

, AF

, AE

FLAG REGISTER (36-BIT MODE)

35A

. . . D

27A

26A

. . . D

18A

17A

. . . D

Offset

CONTROL REGISTER: FLAG SYNCHRONIZATION, PARITY CONFIGURATION

35A

18A

17A

X...

...X

Port B Control

Port A Control

10-BIT AE

FLAG OFFSET REGISTER

35A

10A

. . . D

X...

...X

Offset

10-BIT AF

FLAG OFFSET REGISTER

35A

10A

. . . D

X...

...X

Offset

10-BIT AE

FLAG OFFSET REGISTER

35A

10A

. . . D

X...

...X

Offset

10-BIT AF

FLAG OFFSET REGISTER

35A

10A

. . . D

X...

...X

Offset

NOTES:

All four programmable-flag-offset values are initialized to eight (8) during a reset operation.

Parity Mode: Odd parity = HIGH; even parity = LOW. The parity mode is initialized to odd during a reset operation.

See Tables 5 and 6 and Figure 10 for the detailed format of the Control Register word.

For 36-bit Flag Register Control word, with only only 9 bits to program per flag offset:

Offset is limited to a value of 511. If a greater value is desired, individual flag offset register programming is required.

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

Table 4a. LH543611 Flag Definition Table

FLAG

VALID READ CYCLES REMAINING

VALID WRITE CYCLES REMAINING

FLAG = LOW

FLAG = HIGH

FLAG = LOW

FLAG = HIGH

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

512

511

512

512-p

512

511-p

p + 1

512

257

512

256

255

256

512

q + 1

512

512-q

512

511-q

512

511

NOTE:

q = Programmable-Almost-Empty Offset value. (Default value: q = 8.)

p = Programmable-Almost-Full Offset value. (Default value: p = 8.)

Table 4b. LH543621 Flag Definition Table

FLAG

VALID READ CYCLES REMAINING

VALID WRITE CYCLES REMAINING

FLAG = LOW

FLAG = HIGH

FLAG = LOW

FLAG = HIGH

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

1024

1023

1024

1024-p

1024

1023-p

p + 1

1024

513

1024

512

511

512

1024

q + 1

1024

1024-q

1024

1023-q

1024

1023

NOTE:

q = Programmable-Almost-Empty Offset value. (Default value: q = 8.)

p = Programmable-Almost-Full Offset value. (Default value: p = 8.)

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

PORT

COMMAND

REGISTER

BITS

CODE

VALUE

AFTER
RESET

FLAG

AFFECTED,

IF ANY

DESCRIPTION

NOTES

A, B

, PF

EVEN parity in effect.

A correct 9-bit byte has an even
number of ones.

ODD parity in effect.

A correct 9-bit byte has an odd number
of ones.

Disable Port A parity generation.

No overwriting of parity bits.

Enable Port A parity generation.

Parity bit over eight least-significant bits
of each byte is overwritten into the
most-significant bit of that byte.

Port A parity-error flag operates
'flowthrough.'

is subject to transient glitches

while data bus is changing.

Port A parity-error flag is latched
by CK

is subject to transient glitches

while data bus is changing.

Set by

, reset by

Asynchronous flag clocking.

Set and reset by

Synchronous flag clocking.

Set by

, reset by

Asynchronous flag clocking.

Set and reset by

Synchronous flag clocking.

05, 06

Set by

, reset by

Asynchronous flag clocking.

Set and reset by

Synchronous flag clocking by
Port B clock.

HL, HH

Set and reset by

Synchronous flag clocking by
Port A clock.

Set by

, reset by

Asynchronous flag clocking.

Set and reset by

CKA.

Synchronous flag clocking.

Set by

, reset by

Asynchronous flag clocking.

Set and reset by

Synchronous flag clocking.

Parity check computed over all
four bytes of each word.

Full-word parity-error indication
regardless of WS

setting.

Parity check computed over half-
word or single-byte according to
WS

setting.

Full-word, half word, or single-byte
parity-error indication according to
WS

setting.

Disable Port B parity generation.

No overwriting of parity bits.

Enable Port B parity generation.

Parity bit over eight least-significant bits
of each byte is overwritten into the
most-significant bit of that byte.

Port B parity-error flag operates
'flowthrough'.

is subject to transient glitches

while data bus is changing.

Port B parity-error flag is latched
by CK

remains steady until its value

should change.

Set by

CKB, reset by

Asynchronous flag clocking.

Set and reset by

CKB.

Synchronous flag clocking.

Set by

, reset by

Asynchronous flag clocking.

Set and reset by

Synchronous flag clocking.

14, 15

Set and reset by

Asynchronous flag clocking.

Set and reset by

Synchronous flag clocking by Port A
clock.

HL, HH

Set and reset by

Synchronous flag clocking by Port B
clock.

Table 5. Control-Register Format

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

Table 6. Controllable Functions

TYPE

DESCRIPTION

CONTROL-REGISTER BIT

PORT A

PORT B

Parity

Even/Odd

Policy for 9/18-Bit Word-Width Selection

Generation: Enable/Disable

Flag Behavior: Latched/Flowthrough

Flag Synchronization

EF Synchronous/Asynchronous

AE Synchronous/Asynchronous

HF Synchronous-With-Write/Synchronous-With-Read

5 6

1 4 1 5

AF Synchronous/Asynchronous

FF Synchronous/Asynchronous

NOTE:
1.

LH5420/LH543601 also have this Control-Register function. The same Control-Register bit, bit 00, controls both Port A and Port B functionality.

FLAG

SYNCHRONIZATION

PARITY

PORT B

FLAG

SYNCHRONIZATION

PARITY

PORT A

543611-12

LH5420 / LH543601 CONTROL REGISTER (WRITE-ONLY)

(FOR COMPARISON PURPOSES)

LH543611 / 21 CONTROL REGISTER (READ/WRITE)

Figure 10. LH5420/LH543601 and LH543611/21

Control-Register Formats

Table 5. Control-Register Format (cont'd)

PORT

COMMAND

REGISTER

BITS

CODE

VALUE
AFTER
RESET

FLAG

AFFECTED,

IF ANY

DESCRIPTION

NOTES

Set by

, reset by

Asynchronous flag clocking.

Set and reset by

Synchronous flag clocking.

Set by

, reset by

Asynchronous flag clocking.

Set and reset by

Synchronous flag clocking.

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

TIMING DIAGRAMS

RS, FR

, FR

HF, AF, FF, MBF

EF, AE

RSS

RSH

RSS

RSH

RSS

NOTES:
1. RS overrides all other input signals, except for R/W

, EN

, and REQ

. It operates

asynchronously. RS, FR

, and FR

operates whether or not EN

and/or EN

are asserted.

At least one rising edge and one falling edge of both CK

and CK

must occur while

RS is being asserted (is LOW), with timing as defined by t

RSS

and t

RSH

2. Otherwise, t

RSS

, t

RSH

need not be met unless the rising edge of CK

and/or CK

occurs while that clock is enabled.
3. The parity-check even/odd selection (Control Register bit 00) is initialized to odd byte
parity at reset (HIGH). All other Control Register bits are initialized LOW. FR

and FR

do not alter the configuration, flags reflect the absence of data.
4. The AE and AF flag offsets are initialized to eight locations from the boundary at reset
controlled by RS.

543611-19

REQ

RQS

RQH

REQ

RQS

RQH

RQS

RQH

RQS

RQH

Figure 11. Reset Timing

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

TIMING DIAGRAMS (cont'd)

R/W

RWH

RWS

RSS

RSH

BYPASS IN

BYPASS DATA OUT

BYPASS

OUT

BYPASS

PREVIOUS DATA

NOTES:
1. t

RSS

, t

RSH

need not be met unless the rising edge of CK

or CK

occurs while that clock is enabled.

2. Port A is considered the master port for bypass operation. Thus, CK

, R/W

, EN

, and REQ

control

the transmission of data between ports at reset.

- D

35B

- D

35A

RWS

RWH

543611-20

REQ

RQH

RQS

RQH

Figure 12. Data Bypass Timing

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

TIMING DIAGRAMS (cont'd)

DATA OUT N2

READ FROM

FIFO #2

WRITE TO

FIFO #1

DATA OUT

NOTES:
1. The Port A Parity Error Flag (PF

) reflects the parity status of data present

on the data bus, after a delay t

, when operated asynchronously.

2. The Port A Parity Error Flag (PF

) reflects the parity status of data present

on the data bus during the previous clock cycle, and meeting the setup
time at CK

, when operated synchronously.

3. The status of OE

does not gate read or write operations.

4. If OE

is left LOW during a write operation, then the previous data held in

the output latch is written back into FIFO #1.

R/W

- D

35A

RWH

RWS

DATA IN N4

VALID PF

FOR N1

VALID PF FOR N2

VALID PF

FOR N3

543611-21

RQS

RQH

REQ

RQS

RQH

RWH

RWS

RQH

RQS

DATA N1

VALID PF

FOR N4

VALID PF FOR N1

VALID PF FOR N2

VALID PF FOR N4

ASYNCHRONOUS

SYNCHRONOUS

READ FROM

FIFO #2

RWS

Figure 13. Port A FIFO Read/Write

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

TIMING DIAGRAMS (cont'd)

DATA OUT N2

READ FROM

FIFO #1

WRITE TO

FIFO #2

DATA OUT

NOTES:
1. The Port B Parity Error Flag (PF

) reflects the parity status of data present

on the data bus, after a delay t

, when operated asynchronously.

2. The Port B Parity Error Flag (PF

) reflects the parity status of data present

on the data bus during the previous clock cycle, and meeting the setup
time at CK

, when operated synchronously.

3. The status of OE

does not gate read or write operations.

4. If OE

is left LOW during a write operation, then the previous data held in

the output latch is written back into FIFO #2.

R/W

- D

35B

RWH

RWS

DATA IN N4

VALID PF

FOR N1

VALID PF FOR N2

VALID PF

FOR N3

543611-22

RQS

RQH

REQ

RQS

RQH

DATA N1

VALID PF

FOR N4

VALID PF FOR N1

VALID PF FOR N2

VALID PF FOR N4

ASYNCHRONOUS

SYNCHRONOUS

READ FROM

FIFO #1

RWS

RWH

RWS

RQS

RQH

Figure 14. Port B FIFO Read/Write

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

TIMING DIAGRAMS (cont'd)

R/W

MBF

MAILBOX IN

WRITE TO

MAILBOX #1

READ FROM

MAILBOX #2

MBF

MAXIMUM OF 2 CK

CYCLES LATENCY

MAILBOX OUT

NOTES:
1. Both edges of MBF

are synchronized to the Port A clock, CK

2. Both edges of MBF

are synchronized to the Port B clock, CK

3. There is a maximum of two CK

clock cycles of synchronization latency before MBF

is asserted to indicate valid new mailbox data.
4. The status of mailbox flags does not prevent mailbox read or write operations.

35A

RWH

RWS

RWH

RWS

MBF

543611-23

REQ

RQS

RQH

RQS

RQH

Figure 15. Port A Mailbox Access

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

TIMING DIAGRAMS (cont'd)

MAILBOX IN

WRITE TO

MAILBOX #2

READ FROM

MAILBOX #1

MBF

MAXIMUM OF 2 CK

CYCLES LATENCY

MAILBOX OUT

NOTES:
1. Both edges of MBF

are synchronized to the Port A clock, CK

2. Both edges of MBF

are synchronized to the Port B clock, CK

3. There is a maximum of two CK

clock cycles of synchronization latency before MBF

is asserted to indicate valid new mailbox data.
4. The status of mailbox flags does not prevent mailbox read or write operations.

R/W

MBF

- D

35B

RWH

RWS

RWH

RWS

MBF

543611-24

REQ

RQS

RQH

RQS

RQH

Figure 16. Port B Mailbox Access

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

TIMING DIAGRAMS (cont'd)

R/W

FLAG DATA IN

FLAG DATA OUT

LOAD FLAG

POSITIONS

READ FLAG

POSITIONS

, AE

, AF

NOTES:
1. For valid flag address codes and data formats, see Table 3.
2. If flag status is altered by flag programming, the updated flags will be valid within a time t

RF.

3. The Control Register may be loaded or read back as shown here, with A

, A

= HLL.

- D

35A

RWH

RWS

RWH

RWS

543611-25

REQ

RQS

RQH

RQS

RQH

Figure 17. Flag Programming

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

TIMING DIAGRAMS (cont'd)

543611-26

(EF

)

CK (CK )

EN (EN )

CK (CK )

B A

R/W (R/W )

REQ

(REQ

)

NOTES:
1. A

and A

all are held HIGH for FIFO access at Port A.

is held HIGH for FIFO access at Port B.

2. Parameters without parentheses apply to FIFO #2 operation.
Parameters with parentheses apply to FIFO #1 operation.
3. Assertion of the Empty Flags is controlled by rising clock
edges; whereas, deassertion of the Empty Flags is controlled
by falling clock edges.

RWH

RWS

RWH

RWS

RQS

RQH

EN (EN )

RQS

RQH

REQ

(REQ

)

Figure 18. Empty Flag Timing, When Asynchronous

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

543611-44

(CK

)

R/W

(R/W

)

R/W

(R/W

)

(EN

)

RWS

RQS

RQH

RWS

RWH

RQS

RQH

SKEW2

(4)

RWH

REQ

(REQ

)

(EN

)

REQ

(REQ

)

(CK

)

(EF

)

NOTES:
1. A

, A

, and A

all are held HIGH for FIFO access at Port A.

is held HIGH for FIFO access at Port B.

2. Parameters without parentheses apply to FIFO #2 operation.
Parameters with parentheses apply to FIFO #1 operation.
3. Assertion of the Empty Flags is controlled by rising clock
edges; whereas, internal deassertion of the Empty Flags
is controlled by falling clock edges, and their external deassertion
is controlled by rising clock edges.
4. t

SKEW2

is the minimum time between a falling CK

(CK

) edge

and a rising CK

(CK

) edge for EF to change predictably during

the current clock cycle. If the time between the falling edge of
CK

(CK

) and the rising edge of CK

(CK

) is less than t

SKEW2

then it is not guaranteed that EF will change state until the next
following CK

(CK

) edge.

Figure 19. Empty Flag Timing, When Synchronous

TIMING DIAGRAMS (cont'd)

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

(AE

)

CK (CK )

EN (EN )

CK (CK )

R/W (R/W )

RWH

RWS

RWH

RWS

543611-27

NOTES:
1. A

and A

all are held HIGH for FIFO access at Port A.

is held HIGH for FIFO access at Port B.

2. Parameters without parentheses apply to FIFO #2 operation.
Parameters with parentheses apply to FIFO #1 operation.
3. Assertion of the Almost-Empty Flags is controlled by rising clock
edges; whereas, deassertion of the Almost-Empty Flags is controlled
by falling clock edges.

RQH

RQS

REQ (REQ )

EN (EN )

REQ (REQ )

RQH

RQS

Figure 20. Almost-Empty Flag Timing, When Asynchronous

TIMING DIAGRAMS (cont'd)

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

TIMING DIAGRAMS (cont'd)

543611-45

(CK

)

R/W

(R/W

)

R/W

(R/W

)

(EN

)

RWS

RQS

RQH

RWS

RWH

RQS

RQH

SKEW2

(4)

RWH

REQ

(REQ

)

(EN

)

REQ

(REQ

)

(CK

)

(AE

)

NOTES:
1. A

, A

, and A

all are held HIGH for FIFO access at Port A.

is held HIGH for FIFO access at Port B.

2. Parameters without parentheses apply to FIFO #2 operation.
Parameters with parentheses apply to FIFO #1 operation.
3. Assertion of the Almost-Empty Flags is controlled by rising clock
edges; whereas, internal deassertion of the Almost-Empty Flags
is controlled by falling clock edges, and their external deassertion
is controlled by rising clock edges.
4. t

SKEW2

is the minimum time between a falling CK

(CK

) edge

and a rising CK

(CK

) edge for AE to change predictably during

the current clock cycle. If the time between the falling edge of
CK

(CK

) and the rising edge of CK

(CK

) is less than t

SKEW2

then it is not guaranteed that AE will change state until the next
following CK

(CK

) edge.

Figure 21. Almost-Empty Flag Timing, When Synchronous

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

TIMING DIAGRAMS (cont'd)

(FF

)

CK (CK )

EN (EN )

CK (CK )

R/W (R/W )

EN (EN )

RWH

RWS

RWH

RWS

543611-28

NOTES:
1. A

and A

all are held HIGH for FIFO access at Port A.

is held HIGH for FIFO access at Port B.

2. Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
3. Assertion of the Full Flags is controlled by rising clock
edges; whereas, deassertion of the Full Flags is controlled
by falling clock edges.

RQS

RQH

REQ

(REQ

)

REQ

(REQ

)

RQS

RQH

Figure 22. Full Flag Timing, When Asynchronous

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

543611-46

(CK

)

R/W

(R/W

)

R/W

(R/W

)

(EN

)

RWS

RQS

RQH

RWS

RWH

RQS

RQH

SKEW1

(4)

RWH

REQ

(REQ

)

(EN

)

REQ

(REQ

)

(CK

)

(FF

)

NOTES:
1. A

, A

, and A

all are held HIGH for FIFO access at Port A.

is held HIGH for FIFO access at Port B.

2. Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
3. Assertion of the Full Flags is controlled by rising clock edges;
whereas, internal deassertion of the Full Flags is controlled by
falling clock edges, and their external deassertion is controlled
by rising clock edges.
4. t

SKEW1

is the minimum time between a falling CK

(CK

) edge

and a rising CK

(CK

) edge for FF to change predictably during

the current clock cycle. If the time between the falling edge of
CK

(CK

) and the rising edge of CK

(CK

) is less than t

SKEW1

then it is not guaranteed that FF will change state until the next
following CK

(CK

) edge.

Figure 23. Full Flag Timing, When Synchronous

TIMING DIAGRAMS (cont'd)

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

TIMING DIAGRAMS (cont'd)

(AF

)

CK (CK )

EN (EN )

CK (CK )

R/W (R/W )

RWH

RWS

RWH

RWS

543611-29

NOTES:
1. A

and A

all are held HIGH for FIFO access at Port A.

is held HIGH for FIFO access at Port B.

2. Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
3. Assertion of the Almost-Full Flags is controlled by rising clock
edges; whereas, deassertion of the Almost-Full Flags is controlled
by falling clock edges.

RQS

RQH

REQ

(REQ

)

EN (EN )

RQS

RQH

REQ

(REQ

)

Figure 24. Almost-Full Flag Timing, When Asynchronous

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

TIMING DIAGRAMS (cont'd)

543611-47

(CK

)

R/W

(R/W

)

R/W

(R/W

)

(EN

)

RWS

RQS

RQH

RWS

RWH

RQS

RQH

SKEW1

(4)

RWH

REQ

(REQ

)

(EN

)

REQ

(REQ

)

(CK

)

(AF

)

NOTES:
1. A

, A

, and A

all are held HIGH for FIFO access at Port A.

is held HIGH for FIFO access at Port B.

2. Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
3. Assertion of the Almost-Full Flags is controlled by rising clock
edges; whereas, internal deassertion of the Almost-Full Flags
is controlled by falling clock edges, and their external deassertion
is controlled by rising clock edges.
4. t

SKEW1

is the minimum time between a falling CK

(CK

) edge

and a rising CK

(CK

) edge for AF to change predictably during

the current clock cycle. If the time between the falling edge of
CK

(CK

) and the rising edge of CK

(CK

) is less than t

SKEW1

then it is not guaranteed that AF will change state until the next
following CK

(CK

) edge.

Figure 25. Almost-Full Flag Timing, When Synchronous

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

TIMING DIAGRAMS (cont'd)

(HF

)

CK (CK )

EN (EN )

CK (CK )

R/W (R/W )

EN (EN )

RWH

RWS

RWH

RWS

543611-30

NOTES:
1. A

and A

all are held HIGH for FIFO access at Port A.

is held HIGH for FIFO access at Port B.

2. Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
3. Both assertion and deassertion of the Half-Full Flags are controlled
entirely by rising clock edges, rather than by falling clock edges.

RQS

RQH

REQ

(REQ

)

RQS

RQH

REQ

(REQ

)

Figure 26. Half-Full Flag Timing, When Asynchronous

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

543611-48

(CK

)

R/W

(R/W

)

R/W

(R/W

)

(EN

)

RWS

RQS

RQH

RWS

RWH

RQS

RQH

SKEW2

(4)

RWH

REQ

(REQ

)

(EN

)

REQ

(REQ

)

(CK

)

(HF

)

NOTES:
1. A

, A

, and A

all are held HIGH for FIFO access at Port A.

is held HIGH for FIFO access at Port B.

2. Parameters without parentheses apply to FIFO #2 operation.
Parameters with parentheses apply to FIFO #1 operation.
3. Both assertion and deassertion of the Half-Full Flags are controlled
entirely by rising clock edges, rather than by falling clock edges.
4. t

SKEW2

is the minimum time between a falling CK

(CK

) edge

and a rising CK

(CK

) edge for HF to change predictably during

the current clock cycle. If the time between the falling edge of
CK

(CK

) and the rising edge of CK

(CK

) is less than t

SKEW2

then it is not guaranteed that HF will change state until the next
following CK

(CK

) edge.

Figure 27. Half-Full Flag Timing, When Synchronized

to a Port Clock Doing Reading

TIMING DIAGRAMS (cont'd)

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

543611-49

(CK

)

R/W

(R/W

)

R/W

(R/W

)

(EN

)

RWS

RQS

RQH

RWS

RWH

RQS

RQH

SKEW1

(4)

RWH

REQ

(REQ

)

(EN

)

REQ

(REQ

)

(CK

)

(HF

)

NOTES:
1. A

, A

, and A

all are held HIGH for FIFO access at Port A.

is held HIGH for FIFO access at Port B.

2. Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
3. Both assertion and deassertion of the Half-Full Flags are
controlled entirely by rising clock edges, rather than by falling clock edges.
4. t

SKEW1

is the minimum time between a falling CK

(CK

) edge

and a rising CK

(CK

) edge for HF to change predictably during

the current clock cycle. If the time between the falling edge of
CK

(CK

) and the rising edge of CK

(CK

) is less than t

SKEW1

then it is not guaranteed that HF will change state until the next
following CK

(CK

) edge.

Figure 28. Half-Full Flag Timing, When Synchronized

to a Port Clock Doing Writing

TIMING DIAGRAMS (cont'd)

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

R/W

RSH

RSS

RWS

NOTES:

1. t

RSS

and t

RSH

need not be met unless a rising edge of CK

or CK

occurs while that clock is enabled.

2. t

RSS

is the time needed to deassert RT

before returning to a normal FIFO cycle.

3. t

RSH

is the time needed before asserting RT

after a normal FIFO cycle.

4. Read and write operations to FIFO #2 should be disabled while RT

is being asserted.

543611-31

RQS

RQH

RQS

RQH

RQS

REQ

RQS

RQH

RQS

RQH

RQS

Figure 29. FIFO #2 Retransmit

TIMING DIAGRAMS (cont'd)

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

TIMING DIAGRAMS (cont'd)

R/W

RSS

RSH

RWS

NOTES:

1. t

RSS

and t

RSH

need not be met unless a rising edge of CK

or CK

occurs while that clock is enabled.

2. t

RSS

is the time needed to deassert RT

before returning to a normal FIFO cycle.

3. t

RSH

is the time needed before asserting RT

after a normal FIFO cycle.

4. Read and write operations to FIFO #1 should be disabled while RT

is being asserted.

RSH

543611-32

RQS

RQH

REQ

RQS

RQH

RQS

REQ

RQS

RQH

RQS

RQH

RQS

Figure 30. FIFO #1 Retransmit

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

TIMING DIAGRAMS (cont'd)

R/W

PREVIOUS DATA

FRL

NOTES:
1. A

, A

, and A

are all held HIGH for FIFO access.

2. OE

is held HIGH.

3. OE

is held LOW.

4. t

FRL

(First Read Latency) - The first read following an empty condition

may begin no earlier than t

FRL

after the first write to an empty FIFO,

to ensure that valid read data is retrieved.

- D

35A

- D

35B

RWH

RWS

RWH

RWS

RWH

RWS

RWH

RWS

543611-33

RQS

RQH

REQ

RQS

RQH

RQS

RQH

REQ

RQS

RQH

Figure 31. FIFO #1 Write and Read Operation in

Near-Empty Region

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

TIMING DIAGRAMS (cont'd)

R/W

FRL

NOTES:
1. A

, A

, and A

are all held HIGH for FIFO access.

2. OE

is held HIGH.

3. OE

is held LOW.

4. t

FRL

(First Read Latency) - The first read following an empty condition

may begin no earlier than t

FRL

after the first write to an empty FIFO,

to ensure that valid read data is retrieved.

- D

35B

- D

35A

RWH

RWS

RWH

RWS

RWH

RWS

RWH

RWS

PREVIOUS DATA

543611-34

RQS

RQH

REQ

RQS

RQH

REQ

RQS

RQH

RQS

Figure 32. FIFO #2 Write and Read Operation in

Near-Empty Region

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

TIMING DIAGRAMS (cont'd)

R/W

PREVIOUS DATA

FWL

NOTES:
1. A

and A

all are held HIGH for FIFO access at Port A.

is held HIGH for FIFO access at Port B.

2. OE

is held HIGH.

3. OE

is held LOW.

4. t

FWL

(First Write Latency) - The first write following a full condition

may begin no earlier than t

FWL

after the first read from a full FIFO,

to ensure that valid write data is written.

- D

35A

- D

35B

RWH

RWS

RWH

RWS

RWH

RWS

RWH

RWS

543611-35

RQS

RQH

REQ

RQS

RQH

RQS

RQH

REQ

RQS

RQH

Figure 33. FIFO #1 Read and Write Operation in

Near-Full Region

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

TIMING DIAGRAMS (cont'd)

R/W

NOTES:
1. A

and A

all are held HIGH for FIFO access at Port A.

is held HIGH for FIFO access at Port B.

2. OE

is held HIGH.

3. OE

is held LOW.

4. t

FWL

(First Write Latency) - The first write following a full condition

may begin no earlier than t

FWL

after the first read from a full FIFO,

to ensure that valid write data is written.

- D

35B

- D

35A

PREVIOUS DATA

FWL

RWH

RWS

RWH

RWS

RWH

RWS

RWH

RWS

543611-36

RQS

RQH

REQ

RQS

RQH

RQS

RQH

REQ

RQS

RQH

Figure 34. FIFO #2 Read and Write Operation in

Near-Full Region

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

TIMING DIAGRAMS (cont'd)

R/W

WORD # n+1

WORD # n

NOTES:
1. A

is held HIGH for FIFO access.

2. OE

is held LOW.

3. WS

is held HIGH and WS

is held LOW for double-byte access.

4. Data-access time t

, after the rising edge of CK

, shown for the

first read cycle, applies similarly for all subsequent read cycles.

- D

17B

18B

- D

35B

RWS

WORD # n+2

WORD # n+1

WORD # n

WORD # n+2

BITS

0-17

BITS

18-35

BITS

0-17

BITS

18-35

BITS

0-17

BITS

18-35

BITS

0-17

BITS

18-35

BITS

0-17

BITS

18-35

543611-37

RQS

REQ

Figure 35. Port B Double-Byte FIFO #1 Read Access for

36-to-18 Funneling

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

R/W

WORD # n

WORD # n+1

WORD # n+2

NOTES:
1. A

is held HIGH for FIFO access.

2. OE

is held HIGH.

3. WS

is held HIGH and WS

is held LOW for double-byte access.

4. Data-setup time t

and data-hold time t

, before and after

the rising edge of CK

, shown for the first write cycle, apply

similarly for all subsequent write cycles.

- D

17B

RWS

BITS

0-17

BITS

18-35

BITS

0-17

BITS

18-35

BITS

0-17

BITS

18-35

543611-38

RQS

REQ

Figure 36. Port B Double-Byte FIFO #2 Write Access for

18-to-36 Defunneling

TIMING DIAGRAMS (cont'd)

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

TIMING DIAGRAMS (cont'd)

R/W

BITS

0-8

WORD # n+1

WORD # n

NOTES:
1. A

is held HIGH for FIFO access.

2. OE

is held LOW.

3. WS

and WS

both are held LOW for single-byte access.

4. Data-access time t

, after the rising edge of CK

, shown for the

first read cycle, applies similarly for all subsequent read cycles.

BITS

9-17

BITS

18-26

BITS

27-35

BITS

0-8

BITS

9-17

BITS

18-26

BITS

27-35

BITS

0-8

BITS

9-17

BITS

18-26

BITS

27-35

BITS

0-8

BITS

9-17

BITS

18-26

BITS

27-35

BITS

0-8

BITS

9-17

BITS

18-26

BITS

27-35

27B

- D

35B

18B

- D

26B

- D

17B

- D

RWS

WORD # n+1

WORD # n

WORD # n+1

WORD # n

WORD # n+1

WORD # n

543611-39

RQS

REQ

Figure 37. Port B Single-Byte FIFO #1 Read Access for

36-to-9 Funneling

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

TIMING DIAGRAMS (cont'd)

R/W

BITS

0-8

BITS

9-17

BITS

18-26

BITS

27-35

WORD # n

WORD # n+1

NOTES:
1. A

is held HIGH for FIFO access.

2. OE

is held HIGH.

3. WS

and WS

both are held LOW for single-byte access.

4. Data-setup time t

and data-hold time t

, before and after

the rising edge of CK

, shown for the first write cycle, apply

similarly for all subsequent write cycles.

BITS

0-8

BITS

9-17

- D

RWS

543611-40

RQS

REQ

Figure 38. Port B Single-Byte FIFO #2 Write Access for

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

543611-41

RQS

ACK

(CK )

(R/W )

(REQ )

(ACK )

(AF

)

R/W

REQ

ACK

RWS

Indicates where a write would take place, if ACK were tied to EN.

NOTES:
1. For a FIFO access to occur, REQ and EN must be held HIGH for the required setup and hold times.
2. ACK can be tied directly to EN to directly gate FIFO accesses.

3. REQ must be maintained HIGH with R/W stable throughout entire clock cycle for ACK to be generated.
4. When the REQ/ACK handshake is not used, ACK can be ignored,
and REQ may be tied HIGH or used as a second enable.
5. Parameters without parentheses apply to Port A. Parameters with parentheses apply to Port B.

Starting at the third cycle after entering the
'almost-full' region, acknowledge
occurs on every third cycle to prevent overrun
of the full condition.

Outside the 'almost-full' region,
acknowledge is continuous
for a continuous request.

Figure 39. Write Request/Acknowledge Handshake

TIMING DIAGRAMS (cont'd)

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

TIMING DIAGRAMS (cont'd)

RQS

ACK

(CK )

(R/W )

(REQ )

(ACK )

(AE

)

R/W

REQ

ACK

RWS

Starting at the third cycle after entering the
'almost-empty' region, acknowledge
occurs on every third cycle to prevent underrun
of the empty condition.

Outside the 'almost-empty' region,
acknowledge is continuous
for a continuous request.

Indicates where a read would take place, if ACK were tied to EN.

NOTES:
1. For a FIFO access to occur, REQ and EN must be held HIGH for the required setup and hold times.
2. ACK can be tied directly to EN to directly gate FIFO accesses.

543611-42

Figure 40. Read Request/Acknowledge Handshake

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

RWS

RQS

WSS

WSH

WSS

WSH

R/W

REQ

- D

35B

- D

35B

(WHEN DATA

WORDS ARE

INCOMING)

(SYNCHRONOUS

LATCHING)

(ASYNCHRONOUS,

WHEN DATA WORDS

ARE INCOMING)

(WHEN DATA

WORDS ARE

OUTGOING)

(ASYNCHRONOUS,

WHEN DATA WORDS

ARE OUTGOING)

543611-50

NOTE: During retransmit, WS

and WS

must be stable throughout entire clock cycle.

Figure 41. Changing Port B

Word-Width Selection During Operation

TIMING DIAGRAMS (cont'd)

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

RWS

RQS

WSS

WSH

WSS

WSH

R/W

REQ

- D

35B

- D

35B

(WHEN DATA WORDS

ARE INCOMING)

(SYNCHRONOUS

LATCHING)

(ASYNCHRONOUS,

WHEN DATA WORDS

ARE INCOMING)

(WHEN DATA

WORDS ARE

OUTGOING)

(ASYNCHRONOUS,

WHEN DATA WORDS

ARE OUTGOING)

543611-51

NOTE: During parity mode changes (odd or even), T

may have additional delay from the rising edge of the clock.

Figure 42. Parity Generation

TIMING DIAGRAMS (cont'd)

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

PACKAGE DIAGRAMS

132PQFP

DIMENSIONS IN MM [INCHES]

MAXIMUM LIMIT

MINIMUM LIMIT

132PQFP (PQFP132-P-S950)

28.02 [1.103]
27.86 [1.097]

0.635
[0.025] TYP
NON-ACCUM

4.57 [0.180]
4.06 [0.160]

0.51 [0.020]
MIN.

24.21 [0.953]
24.05 [0.947]

28.02 [1.103]
27.86 [1.097]

27.69 [1.090]
27.18 [1.070]

SECTION

0.10 [0.004]

0.51 [0.020] MIN.

0.15 [0.006]

- 8

CHAMFER

TOP VIEW

24.21 [0.953]
24.05 [0.947]

0.25 [0.010] TYP.

132-pin PQFP

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

DIMENSIONS IN MM [INCHES]

MAXIMUM LIMIT

MINIMUM LIMIT

144TQFP (TQFP-144-P-2020)

0.50 [0.020]

TYP.

0.20 [0.008]
0.09 [0.004]

20.0 [0.787]

BASIC

144TQFP

1.45 [0.057]
1.35 [0.053]

DETAIL

20.0

[0.787]
BASIC

1.60 [0.063]

REF. MAX

0.15 [0.006]
0.05 [0.002]

22.0

[0.866]
BASIC

0.27 [0.010]
0.17 [0.007]

22.0 [0.866]

BASIC

0.75 [0.030]
0.47 [0.019]

1.00

[0.039]

REF.

144-pin TQFP

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

ORDERING INFORMATION

15
20
25
30
35

Cycle Times (ns)

M 144-pin, Thin Quad Flat Package (TQFP144-P-2020)
P 132-pin, Plastic Quad Flat Package (PQFP132-P-S950)

LH543611/21

Device Type

Package

- ##

Speed

512 x 36 x 2/1K x 36 x 2 Bidirectional FIFO

Example: LH543611M-15 (512 x 36 x 2 Bidirectional FIFO, 15 ns, 144-pin, Thin Quad Flat Package)

543611-43

NOTE:

For PQFP-to-PGA conversion for through-hole board designs, SHARP recommends QFP-to-PGA adaptors from ISI (Interconnect Systems Inc.)
ISI makes three models that can map the LH543611/21 132-pin PQFP to a 13x13 PGA (100 mil); mode #A 13225-1® map to a SHARP spe-
cific 120-pin PGA. For more information, contact SHARP or ISI directly at P.O. Box 1089, Simi Valley, CA 93062, Tel: (805) 581-5626.

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

LH543611/21

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