LH5P860
CMOS 512K (64K
8) Pseudo-Static RAM
FEATURES
65,536
8 bit organization
Access time: 80 ns (MAX.)
Cycle time: 140 ns (MIN.)
Single +5 V power supply
Pin compatible with 1M standard SRAM
Power consumption (MAX.):
Operating: 440 mW
Self refresh (TTL level): 5.5 mW
Self refresh (CMOS level): 2.75 mW
TTL compatible I/O
512 refresh cycles/8 ms (MAX.)
Available for auto-refresh and self-refresh
modes
Packages:
32-pin, 600-mil DIP
32-pin, 525-mil SOP
DESCRIPTION
The LH5P860 is a 512K-bit Pseudo-Static RAM or-
ganized as 65,536
8 bits. It is fabricated using sili-
con-gate CMOS process technology. With its built-in
oscillator, it is easy to refresh memories without an
external clock.
PIN CONNECTIONS
5P860-1
TOP VIEW
5
6
7
8
11
12
A
0
A
3
26
25
24
23
22
21
18
A
5
A
4
9
10
A
1
A
2
20
19
A
6
A
9
A
11
A
10
13
14
15
28
27
I/O
0
A
13
16
17
I/O
2
OE
CE
1
A
7
GND
I/O
4
I/O
3
I/O
5
A
8
32-PIN DIP
32-PIN SOP
3
4
A
12
30
29
CE
2
A
14
R/W
1
2
NC
32
31
V
CC
RFSH
A
15
I/O
1
I/O
6
I/O
7
Figure 1. Pin Connections for DIP and
SOP Packages
1
I/O
1
CLOCK
GENERATOR
CE
1
R/W
A
12
A
13
A
14
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
11
A
10
A
2
A
1
A
0
COLUMN
ADDRESS
BUFFER
ROW
ADDRESS
BUFFER
REFRESH
ADDRESS
COUNTER
DATA
IN
BUFFER
DATA
OUT
BUFFER
I/O
SELECTOR
COLUMN
DECODER
SENSE
AMPS
ROW
DECODER
EXT/INT
ADDRESS
MUX
REFRESH
CONTROLLER
REFRESH
TIMER
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
V
BB
GENERATOR
GND
V
CC
5P860-2
I/O
0
RFSH
OE
12
11
10
9
8
7
6
5
27
26
23
25
4
28
3
22
24
29
16
32
13
14
15
17
18
19
20
21
30
CE
2
MEMORY
ARRAY
512 K
A
15
31
A
9
- A
15
A
0
- A
8
1
Figure 2. LH5P860 Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
A
0
- A
15
Address input
R/W
Read/Write input
OE
Output Enable input
RFSH
Refresh input
CE
1
, CE
2
Chip Enable input
SIGNAL
PIN NAME
I/O
0
- I/O
7
Data input/output
V
CC
Power Supply
GND
Ground
NC
No Connection
LH5P860
CMOS 512K (64K
8) Pseudo-Static RAM
2
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
NOTE
Applied voltage on all pins
V
T
1.0 to +7.0
V
1
Output short circuit current
I
O
50
mA
Power dissipation
P
D
600
mW
Operating temperature
Topr
0 to +70
C
Storage temperature
Tstg
65 to +150
C
NOTE:
1.
The maximum applicable voltage on any pin with respect to GND.
RECOMMENDED OPERATING CONDITIONS (T
A
= 0 to +70
C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
V
CC
4.5
5.0
5.5
V
GND
0
0
0
V
Input voltage
V
IH
2.4
V
CC
+ 0.3
V
V
IL
1.0
0.8
V
CAPACITANCE (T
A
= 0 to +70
C, f = 1 MHz, V
CC
= 5.0 V
10%)
PARAMETER
CONDITIONS
SYMBOL
MIN.
MAX.
UNIT
Input capacitance
A
0
A
15
C
IN1
8
pF
R/W, OE, RFSH
C
IN2
5
pF
CE
1
, CE
2
C
IN3
5
pF
Input/Output capacitance
I/O
0
I/O
7
C
OUT1
10
pF
DC CHARACTERISTICS (T
A
= 0 to +70
C, V
CC
= 5.0 V
10%)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Average supply current in
normal operation
I
CC1
80
mA
1, 2
Supply current in
standby mode
I
CC2
TTL input
1.0
mA
1, 3
CMOS input
0.5
1, 4
Average supply current in
self refresh cycle
I
CC3
TTL input
1.0
mA
1, 5
CMOS input
0.5
1, 6
Input leakage current
I
LI
0 V
V
IN
6.5 V,
0 V except on test pins
10
10
A
I/O leakage current
I
LO
0 V
V
OUT
V
CC
+ 0.3 V,
Outputs in high-impedance
state
10
10
A
Output HIGH voltage
V
OH
I
OUT
= 1.0 mA
2.4
V
Output LOW voltage
V
OL
I
OUT
= 4.0 mA
0.4
V
NOTES:
1.
Specified values are with outputs open.
2.
I
CC1
depends on the cycle time.
3.
CE
1
= V
IH
, RFSH = V
IH
.
4.
CE
1
= V
CC
0.2 V, RFSH = V
CC
0.2 V.
5.
CE
1
= V
IH
, RFSH = V
IL
.
6.
CE
1
= V
CC
0.2 V, RFSH = 0.2 V.
CMOS 512K (64K
8) Pseudo-Static RAM
LH5P860
3
AC CHARACTERISTICS
1, 2, 3
(T
A
= 0 to +70
C, V
CC
= 5.0 V
10%)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Random read, write cycle time
t
RC
140
ns
Read modify write cycle time
t
RMW
205
ns
CE pulse width
t
CE
80
10,000
ns
CE precharge time
t
P
50
ns
Address setup time
t
AS
0
ns
4
Address hold time
t
AH
20
ns
4
Read command setup time
t
RCS
0
ns
Read command hold time
t
RCH
0
ns
CE access time
t
CEA
80
ns
5
OE access time
t
OEA
30
ns
5
Output enable time from CE
t
CLZ
20
ns
Output enable time from OE
t
OLZ
0
ns
Output enable time from R/W
t
WLZ
0
ns
Output disable time from CE
t
CHZ
25
ns
Output disable time from OE
t
OHZ
25
ns
Output diable time from R/W
t
WHZ
25
ns
OE setup time
t
OES
10
ns
OE hold time
t
OEH
10
ns
Write command pulse width
t
WP
30
ns
Write command setup time
t
WCS
30
ns
Write command hold time
t
WCH
50
ns
Data setup time from R/W
t
DSW
30
ns
6
Data setup time from CE
t
DSC
30
ns
6
Data hold time from R/W
t
DHW
0
ns
6
Data hold time from CE
t
DHC
0
ns
6
Transition time (rise and fall)
t
T
3
35
ns
Refresh time interval
t
REF
8
ms
Refresh command hold time
t
RHC
15
ns
Auto refresh cycle time
t
FC
130
ns
Refresh delay time from CE
t
RFD
50
ns
Refresh pulse width (Auto refresh)
t
FAP
30
8,000
ns
Refresh precharge time (Auto refresh)
t
FP
30
ns
Refresh pulse width (Self refresh)
t
FAS
8,000
ns
CE delay time from refresh precharge (Self refresh)
t
FRS
160
ns
NOTES:
1.
In order to initialize the circuit, an initialize pause of 100
s with
CE
1
= V
IH
, RFSH = V
IH
(or CE
2
= V
IL
, RFSH = V
IH
) is required
after power-up, followed by at least 8 dummy cycles.
2.
AC characteristics are measured at t
T
= 5 ns.
3.
AC characteristics are measured at the following condition (see
figure at right):
4.
Address is latched at the negative edge of CE
1
or at the positive
edge of CE
2
.
5.
Measured with a load equivalent to 2TTL + 100 pF.
6.
Data is latched at the positive edge of R/W, at the positive edge
of CE
1
, or at the negative edge of CE
2
.
2.4 V
0.8 V
2.6 V
0.6 V
2.2 V
0.8 V
OUTPUT
INPUT
5P860-12
Figure 3. AC Characteristics
LH5P860
CMOS 512K (64K
8) Pseudo-Static RAM
4
VALID-DATA
OUTPUT
5P860-3
V
IH
V
IL
CE
1
V
IH
V
IL
CE
2
t
P
t
RC
t
CE
t
AS
ADDRESS
INPUT
t
AH
V
IH
V
IL
A
0
- A
15
V
IH
V
IL
OE
V
IH
V
IL
R/W
t
RCS
t
RCH
t
OEA
t
CEA
t
OLZ
t
CLZ
t
OHZ
t
CHZ
V
IH
V
IL
RFSH
V
OH
V
OL
I/O
0
- I/O
7
t
RFD
t
FP
t
RHC
t
FRS
NOTE: Operation is possible using only CE
2
(CE
1
) by fixing CE
1
to LOW (CE
2
to HIGH).
Figure 4. Read Cycle
CMOS 512K (64K
8) Pseudo-Static RAM
LH5P860
5
DATA INPUT
5P860-4
V
IH
V
IL
CE
1
V
IH
V
IL
CE
2
t
P
t
RC
t
CE
t
AS
ADDRESS
INPUT
t
AH
V
IH
V
IL
A
0
- A
15
V
IH
V
IL
OE
t
OES
t
OEH
V
IH
V
IL
RFSH
V
OH
V
OL
I/O
0
- I/O
7
t
RFD
t
FP
t
RHC
t
FRS
V
IH
V
IL
R/W
t
WCS
t
WCH
t
WP
t
DSW
t
DSC
t
DHW
t
DHC
NOTE: Operation is possible using only CE
2
(CE
1
) by fixing CE
1
to LOW (CE
2
to HIGH).
Figure 5. Write Cycle 1 (OE = Fix `H')
LH5P860
CMOS 512K (64K
8) Pseudo-Static RAM
6
DATA INPUT
5P860-5
V
IH
V
IL
CE
1
V
IH
V
IL
CE
2
t
P
t
RC
t
CE
t
AS
ADDRESS
INPUT
t
AH
V
IH
V
IL
A
0
- A
15
V
IH
V
IL
V
IH
V
IL
RFSH
t
RFD
t
FP
t
RHC
t
FRS
V
IH
V
IL
OE
t
WCS
t
WCH
t
WP
t
DSW
t
DSC
t
DHW
t
DHC
t
OHZ
V
IH
V
IL
I/O
0
- I/O
7
t
CLZ
t
WHZ
t
OLZ
t
WLZ
t
CHZ
D
IN
D
OUT
V
OH
V
OL
R/W
NOTE: Operation is possible using only CE
2
(CE
1
) by fixing CE
1
to LOW (CE
2
to HIGH).
Figure 6. Write Cycle 2 (OE Clock)
CMOS 512K (64K
8) Pseudo-Static RAM
LH5P860
7
DATA INPUT
5P860-6
V
IH
V
IL
CE
1
V
IH
V
IL
CE
2
t
P
t
RC
t
CE
t
AS
ADDRESS
INPUT
t
AH
V
IH
V
IL
A
0
- A
15
V
IH
V
IL
V
IH
V
IL
RFSH
t
RFD
t
FP
t
RHC
t
FRS
V
IH
V
IL
OE
t
WCS
t
WCH
t
WP
t
DSW
t
DSC
t
DHW
t
DHC
V
IH
V
IL
I/O
0
- I/O
7
t
CLZ
t
WHZ
t
WLZ
t
CHZ
D
IN
D
OUT
V
OH
V
OL
R/W
NOTE: Operation is possible using only CE
2
(CE
1
) by fixing CE
1
to LOW (CE
2
to HIGH).
t
FD
Figure 7. Write Cycle 3 (OE = Fix `L')
LH5P860
CMOS 512K (64K
8) Pseudo-Static RAM
8
DATA
OUTPUT
5P860-7
V
IH
V
IL
CE
1
V
IH
V
IL
CE
2
t
P
t
RMW
t
AS
ADDRESS
INPUT
t
AH
V
IH
V
IL
A
0
- A
15
V
IH
V
IL
OE
V
IH
V
IL
R/W
t
CHZ
V
IH
V
IL
RFSH
t
RFD
t
FP
t
RHC
t
FRS
t
WCS
t
RCS
t
WP
DATA
INPUT
t
OEA
t
CEA
t
DSW
t
DSC
t
DHW
t
DHC
t
OLZ
t
CLZ
t
WHZ
t
OHZ
t
WLZ
V
IH
V
IL
I/O
0
- I/O
7
D
IN
D
OUT
V
OH
V
OL
NOTE: Operation is possible using only CE
2
(CE
1
) by fixing CE
1
to LOW (CE
2
to HIGH).
Figure 8. Read-Modify-Write Cycle
CMOS 512K (64K
8) Pseudo-Static RAM
LH5P860
9
5P860-8
V
IH
V
IL
CE
1
V
IH
V
IL
CE
2
t
P
t
RC
t
AS
ADDRESS
INPUT
t
AH
V
IH
V
IL
A
0
- A
8
V
IH
V
IL
OE
V
IH
V
IL
RFSH
V
OH
V
OL
I/O
0
- I/O
7
t
RFD
t
FP
t
RHC
t
FRS
t
OES
t
CE
t
OEH
V
IH
V
IL
R/W
t
RCS
t
RCH
OPEN
NOTES:
1. Operation is possible using only CE
2
(CE
1
) by fixing CE
1
to LOW (CE
2
to HIGH).
2. A
9
- A
16
= Don't Care.
Figure 9. CE Only Refresh Cycle
LH5P860
CMOS 512K (64K
8) Pseudo-Static RAM
10
5P860-10
V
IH
V
IL
CE
1
V
IH
V
IL
CE
1
t
RFD
t
FP
t
FAS
t
FRS
t
RHC
OR
V
IH
V
IL
CE
2
V
IH
V
IL
RFSH
V
IH
V
IL
CE
2
V
OH
V
OL
I/O
0
- I/O
7
NOTE: OE, R/W, A
0
-
A
16
= Don't care
OPEN
Figure 10. Self Refresh Cycle
V
IH
V
IL
CE
1
V
IH
V
IL
CE
1
t
FC
t
RFD
t
FP
t
FAP
t
FP
t
FAP
t
FP
t
RHC
t
FC
OR
V
IH
V
IL
CE
2
V
IH
V
IL
RFSH
V
IH
V
IL
CE
2
V
OH
V
OL
I/O
0
- I/O
7
NOTE: OE, R/W, A
0
-
A
16
= Don't care
5P860-9
OPEN
Figure 11. Auto Refresh Cycle
CMOS 512K (64K
8) Pseudo-Static RAM
LH5P860
11
PACKAGE DIAGRAMS
13.45 [0.530]
12.95 [0.510]
0.51 [0.020] MIN.
5.20 [0.205]
5.00 [0.197]
3.50 [0.138]
3.00 [0.118]
2.54 [0.100]
TYP.
0.60 [0.024]
0.40 [0.016]
0.30 [0.012]
0.20 [0.008]
DETAIL
DIMENSIONS IN MM [INCHES]
41.30 [1.626]
40.70 [1.602]
0
TO 15
MAXIMUM LIMIT
MINIMUM LIMIT
4.50 [0.177]
4.00 [0.157]
15.24 [0.600]
TYP.
32DIP (DIP032-P-0600)
1
16
17
32
32DIP
32-pin, 600-mil DIP
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
32SOP (SOP032-P-0525)
14.50 [0.571]
13.70 [0.539]
11.50 [0.453]
11.10 [0.437]
12.50 [0.492]
20.80 [0.819]
20.40 [0.803]
0.15 [0.006]
1.275 [0.050]
0.20 [0.008]
0.00 [0.000]
1.275 [0.050]
2.90 [0.114]
2.50 [0.098]
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
32
17
16
1
1.40 [0.055]
1.40 [0.055]
32SOP
32-pin, 525-mil SOP
LH5P860
CMOS 512K (64K
8) Pseudo-Static RAM
12
80 Access Time (ns)
LH5P860
Device Type
X
Package
- ##
Speed
5P860-11
CMOS 512K (64K x 8) Pseudo-Static RAM
Example: LH5P860N-80 (CMOS 512K (64K x 8) Pseudo-Static RAM, 80 ns, 32-pin, 525-mil SOP)
D 32-pin, 600-mil DIP (DIP032-P-0600)
N 32-pin, 525-mil SOP (SOP032-P-0525)
ORDERING INFORMATION
CMOS 512K (64K
8) Pseudo-Static RAM
LH5P860
13
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