Integrated Circuits Group
LH28F640BNHG-PTSL70
Flash Memory
64M (4M 16)
(Model No.:
LHF64N14)
Spec No.:
FM02Y002
Issue Date:
November 5, 2002
P
RELIMINARY
P
RODUCT
S
PECIFICATIONS
LHF64N14
Handle this document carefully for it contains material protected by international copyright law. Any reproduction,
full or in part, of this material is prohibited without the express written permission of the company.
When using the products covered herein, please observe the conditions written herein and the precautions outlined in
the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly
adhere to these conditions and precautions.
(1) The products covered herein are designed and manufactured for the following application areas. When using the
products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure
to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph
(3).
Office electronics
Instrumentation and measuring equipment
Machine tools
Audiovisual equipment
Home appliance
Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment which demands high
reliability, should first contact a sales representative of the company and then accept responsibility for
incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring
reliability and safety of the equipment and the overall system.
Control and safety devices for airplanes, trains, automobiles, and other transportation equipment
Mainframe computers
Traffic control systems
Gas leak detectors and automatic cutoff devices
Rescue and security equipment
Other safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands extremely high performance
in terms of functionality, reliability, or accuracy.
Aerospace equipment
Communications equipment for trunk lines
Control equipment for the nuclear power industry
Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales
representative of the company.
Please direct all queries regarding the products covered herein to a sales representative of the company.
Rev. 0.11
sharp
LHF64N14 1
PAGE
0.75mm pitch 56-Ball CSP Pinout ............................. 3
Pin Descriptions.......................................................... 4
Simultaneous Operation Modes
Allowed with Four Planes .................................. 6
Memory Map .............................................................. 7
Identifier Codes and OTP Address
for Read Operation ............................................. 8
Identifier Codes and OTP Address for
Read Operation on Partition Configuration........ 8
OTP Block Address Map for OTP Program............... 9
Bus Operation ........................................................... 10
Command Definitions ............................................... 11
Functions of Block Lock and Block Lock-Down..... 13
Block Locking State Transitions upon
Command Write................................................ 13
Block Locking State Transitions upon
WP# Transition................................................. 14
Status Register Definition......................................... 15
Extended Status Register Definition ........................ 16
Read Configuration Register Definition................... 17
PAGE
Frequency Configuration Settings ............................ 18
Frequency Configuration .......................................... 18
Output Configuration ................................................ 19
Read Sequence and Burst Length ............................. 19
Partition Configuration Register Definition.............. 20
Partition Configuration ............................................. 20
1 Electrical Specifications......................................... 21
1.1 Absolute Maximum Ratings ........................... 21
1.2 Operating Conditions ...................................... 21
1.2.1 Capacitance .............................................. 22
1.2.2 AC Input/Output Test Conditions ............ 22
1.2.3 DC Characteristics ................................... 23
1.2.4 AC Characteristics
- Read-Only Operations......................... 25
1.2.5 AC Characteristics
- Write Operations ................................. 33
1.2.6 Reset Operations ...................................... 35
1.2.7 Block Erase, Advanced Factory
Program, (Page Buffer) Program
and OTP Program Performance............. 36
CONTENTS
Rev. 0.11
sharp
LHF64N14 2
LH28F640BNHG-PTSL70
64Mbit (4Mbit
16)
Synchronous Dual Work Flash MEMORY
64M density with 16Bit I/O Interface
High Performance Reads
70/20ns 8-Word Page Mode
66MHz Synchronous Burst Mode
Configurative 4-Plane Dual Work
Flexible Partitioning
Read operations during Block Erase or (Page Buffer)
Program
Status Register for Each Partition
Low Power Operation
1.7V Read and Write Operations
V
CCQ
for Input/Output Power Supply Isolation
Automatic Power Savings Mode Reduces I
CCR
in Static Mode
Enhanced Code + Data Storage
5
s Typical Erase/Program Suspends
OTP (One Time Program) Block
4-Word Factory-Programmed Area
4-Word User-Programmable Area
High Performance Program with Page Buffer
16-Word Page Buffer
5
s/Word (Typ.) at 12V V
PP
Operating Temperature -40
C to +85C
Advanced Factory Programming Mode
3.5
s/Word (Typ.)
Flexible Blocking Architecture
Eight 4K-word Parameter Blocks
One-hundred and twenty-seven 32K-word
Main Blocks
Top Parameter Location
Enhanced Data Protection Features
Individual Block Lock and Block Lock-Down with
Zero-Latency
All blocks are locked at power-up or device reset.
Absolute Protection with V
PP
V
PPLK
Block Erase, Advanced Factory Program,
(Page Buffer) Word Program Lockout during
Power Transitions
Automated Erase/Program Algorithms
1.8V Low-Power 22
s/Word (Typ.)
Programming
12V No Glue Logic 9
s/Word (Typ.)
Production Programming and 0.5s Erase (Typ.)
Cross-Compatible Command Support
Basic Command Set
Common Flash Interface (CFI)
Extended Cycling Capability
Minimum 100,000 Block Erase Cycles
0.75mm pitch 56-Ball CSP
ETOX
TM*
Flash Technology
Not designed or rated as radiation hardened
CMOS Process (P-type silicon substrate)
The product, which is 4-Plane Synchronous Dual Work (Simultaneous Read while Erase/Program) Flash memory, is a low
power, high density, low cost, nonvolatile read/write storage solution for a wide range of applications. The product can
operate at V
CC
=1.7V-1.95V and V
PP
=0.9V-1.95V or 11.7V-12.3V. Its low voltage operation capability greatly extends
battery life for portable applications.
The product provides high performance asynchronous page mode and synchronous burst mode. It allows code execution
directly from Flash, thus eliminating time consuming wait states. Furthermore, its newly configurative partitioning
architecture allows flexible dual work operation.
The memory array block architecture utilizes Enhanced Data Protection features and provides separate Parameter and Main
Blocks that provide maximum flexibility for safe nonvolatile code and data storage.
Fast program capability is provided through the use of high speed Page Buffer Program.
Special OTP (One Time Program) block provides an area to store permanent code such as an unique number.
* ETOX is a trademark of Intel Corporation.
Rev. 0.11
sharp
LHF64N14 3
A
11
A
12
A
9
A
8
GND
A
20
V
CC
CLK
RST#
V
PP
A
18
A
17
A
5
A
6
A
4
H
G
F
E
D
C
B
A
A
3
A
13
A
15
A
14
A
10
A
21
WAIT
ADV#
A
16
DQ
12
WE#
A
19
WP#
NC
A
7
A
2
A
1
V
CCQ
GND
DQ
14
DQ
15
DQ
6
DQ
13
DQ
4
DQ
11
DQ
10
DQ
2
DQ
1
DQ
9
DQ
0
CE#
A
0
OE#
DQ
7
1
2
3
4
5
6
7
GND
DQ
5
V
CC
DQ
3
V
CCQ
DQ
8
GND
0.75mm pitch
56-BALL CSP
PINOUT
11mm x 8mm
TOP VIEW
Figure 1. 0.75mm pitch 56-Ball CSP Pinout
Rev. 0.11
sharp
LHF64N14 4
Table 1. Pin Descriptions
Symbol
Type
Name and Function
A
0
-A
21
INPUT
ADDRESS INPUTS: Inputs for addresses. 64M: A
0
-A
21
DQ
0
-DQ
15
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User
Interface) write cycles, outputs data during memory array, status register, query code,
identifier code and read/partition configuration register code reads. Data pins float to
high-impedance (High Z) when the chip or outputs are deselected. Data is internally
latched during an erase or program cycle.
CE#
INPUT
CHIP ENABLE: Activates the device's control logic, input buffers, decoders and sense
amplifiers. CE#-high (V
IH
) deselects the device and reduces power consumption to
standby levels.
CLK
INPUT
CLOCK: Synchronizes the memory to the system bus operating frequency in
synchronous burst mode. The first rising (or falling if RCR.6 is "0") edge latches the
address when ADV# is V
IL
or upon a rising ADV# edge. This is used only for
synchronous burst mode.
ADV#
INPUT
ADDRESS VALID: Addresses are input to the memory when ADV# is low (V
IL
).
Addresses are latched on ADV#'s rising edge during read and write operations.
RST#
INPUT
RESET: When low (V
IL
), RST# resets internal automation and inhibits write operations
which provides data protection. RST#-high (V
IH
) enables normal operation. After
power-up or reset mode, the device is automatically set to asynchronous read array
mode. RST# must be low during power-up/down.
OE#
INPUT
OUTPUT ENABLE: Gates the device's outputs during a read cycle.
WE#
INPUT
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of CE# or WE# (whichever goes high first).
WP#
INPUT
WRITE PROTECT: When WP# is V
IL
, locked-down blocks cannot be unlocked. Erase
or program operation can be executed to the blocks which are not locked and not locked-
down. When WP# is V
IH
, lock-down is disabled.
WAIT
OUTPUT
WAIT: Indicates data valid in synchronous burst modes. The read configuration register
bit 10 (RCR.10, WT) determines its polarity. With CE# at V
IL
, WAIT's active output is
V
OL
or V
OH
. WAIT is High-Z if CE# is V
IH
. WAIT is not gated by OE#. WAIT is used
only for synchronous burst mode.
V
PP
INPUT
MONITORING POWER SUPPLY VOLTAGE: V
PP
is not used for power supply pin.
With V
PP
V
PPLK
, block erase, advanced factory program, (page buffer) program or
OTP program cannot be executed and should not be attempted.
Applying 12V0.3V to V
PP
provides fast erasing or fast programming mode. In this
mode, V
PP
is power supply pin. Applying 12V0.3V to V
PP
during erase/program can
only be done for a maximum of 1,000 cycles on each block. V
PP
may be connected to
12V0.3V for a total of 80 hours maximum. Use of this pin at 12V beyond these limits
may reduce block cycling capability or cause permanent damage.
Rev. 0.11
sharp
LHF64N14 5
V
CC
SUPPLY
DEVICE POWER SUPPLY (1.7V-1.95V): With V
CC
V
LKO
, all write attempts to the
flash memory are inhibited. Device operations at invalid V
CC
voltage (see DC
Characteristics) produce spurious results and should not be attempted.
V
CCQ
SUPPLY
INPUT/OUTPUT POWER SUPPLY (1.7V-1.95V): Power supply for all input/output
pins.
GND
SUPPLY
GROUND: Do not float any ground pins.
NC
NO CONNECT: Lead is not internally connected; it may be driven or floated.
Table 1. Pin Descriptions
Symbol
Type
Name and Function
Rev. 0.11
(Continued)
sharp
LHF64N14 6
NOTES:
1. "X" denotes the operation available.
2. Configurative Partition Dual Work Restrictions:
Status register reflects partition state, not WSM (Write State Machine) state - this allows a status register for each
partition. Only one partition can be erased or programmed at a time - no command queuing.
Commands must be written to an address within the block targeted by that command.
It is not possible to do burst reads that cross partition boundaries.
Table 2. Simultaneous Operation Modes Allowed with Four Planes
(1, 2)
IF ONE
PARTITION IS:
THEN THE MODES ALLOWED IN THE OTHER PARTITION IS:
Read
Array
Read
ID/OTP
Read
Status
Read
Query
Word
Program
Page
Buffer
Program
OTP
Program
Block
Erase
Advanced
Factory
Program
Program
Suspend
Block
Erase
Suspend
Read Array
X
X
X
X
X
X
X
X
X
Read ID/OTP
X
X
X
X
X
X
X
X
X
Read Status
X
X
X
X
X
X
X
X
X
X
X
Read Query
X
X
X
X
X
X
X
X
X
Word Program
X
X
X
X
X
Page Buffer
Program
X
X
X
X
X
OTP Program
X
Block Erase
X
X
X
X
Advanced
Factory
Program
X
Program
Suspend
X
X
X
X
X
Block Erase
Suspend
X
X
X
X
X
X
X
Rev. 0.11
sharp
LHF64N14 7
127
128
129
130
131
132
133
4K-WORD
3FF000H - 3FFFFFH
4K-WORD
3FE000H - 3FEFFFH
4K-WORD
3FD000H - 3FDFFFH
4K-WORD
3FC000H - 3FCFFFH
4K-WORD
3FB000H - 3FBFFFH
4K-WORD
3FA000H - 3FAFFFH
4K-WORD
PLANE3 (PARAMETER PLANE)
3F9000H - 3F9FFFH
3F8000H - 3F8FFFH
PLANE2 (UNIFORM PLANE)
0
1
2
3
4
5
12
13
14
15
32K-WORD
078000H - 07FFFFH
32K-WORD
070000H - 077FFFH
32K-WORD
068000H - 06FFFFH
32K-WORD
060000H - 067FFFH
32K-WORD
058000H - 05FFFFH
32K-WORD
050000H - 057FFFH
32K-WORD
PLANE0 (UNIFORM PLANE)
048000H - 04FFFFH
32K-WORD
040000H - 047FFFH
32K-WORD
038000H - 03FFFFH
32K-WORD
030000H - 037FFFH
32K-WORD
028000H - 02FFFFH
32K-WORD
020000H - 027FFFH
32K-WORD
018000H - 01FFFFH
32K-WORD
010000H - 017FFFH
32K-WORD
008000H - 00FFFFH
32K-WORD
000000H - 007FFFH
0F8000H - 0FFFFFH
0F0000H - 0F7FFFH
0E8000H - 0EFFFFH
0E0000H - 0E7FFFH
0D8000H - 0DFFFFH
0D0000H - 0D7FFFH
PLANE1 (UNIFORM PLANE)
0C8000H - 0CFFFFH
0C0000H - 0C7FFFH
0B8000H - 0BFFFFH
0B0000H - 0B7FFFH
0A8000H - 0AFFFFH
0A0000H - 0A7FFFH
098000H - 09FFFFH
090000H - 097FFFH
088000H - 08FFFFH
080000H - 087FFFH
BLOCK NUMBER ADDRESS RANGE
BLOCK NUMBER ADDRESS RANGE
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
16
18
19
20
21
22
23
17
24
25
6
8
9
10
11
7
26
28
29
30
31
27
62
63
32
33
34
35
42
43
44
45
32K-WORD
178000H - 17FFFFH
32K-WORD
170000H - 177FFFH
32K-WORD
168000H - 16FFFFH
32K-WORD
160000H - 167FFFH
32K-WORD
158000H - 15FFFFH
32K-WORD
150000H - 157FFFH
32K-WORD
148000H - 14FFFFH
32K-WORD
140000H - 147FFFH
32K-WORD
138000H - 13FFFFH
32K-WORD
130000H - 137FFFH
32K-WORD
128000H - 12FFFFH
32K-WORD
120000H - 127FFFH
32K-WORD
118000H - 11FFFFH
32K-WORD
110000H - 117FFFH
32K-WORD
108000H - 10FFFFH
32K-WORD
100000H - 107FFFH
1F8000H - 1FFFFFH
1F0000H - 1F7FFFH
1E8000H - 1EFFFFH
1E0000H - 1E7FFFH
1D8000H - 1DFFFFH
1D0000H - 1D7FFFH
1C8000H - 1CFFFFH
1C0000H - 1C7FFFH
1B8000H - 1BFFFFH
1B0000H - 1B7FFFH
1A8000H - 1AFFFFH
1A0000H - 1A7FFFH
198000H - 19FFFFH
190000H - 197FFFH
188000H - 18FFFFH
180000H - 187FFFH
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
46
48
49
50
51
52
53
47
54
55
36
38
39
40
41
37
56
58
59
60
61
57
92
93
94
95
64
65
72
73
74
75
32K-WORD
278000H - 27FFFFH
32K-WORD
270000H - 277FFFH
32K-WORD
268000H - 26FFFFH
32K-WORD
260000H - 267FFFH
32K-WORD
258000H - 25FFFFH
32K-WORD
250000H - 257FFFH
32K-WORD
248000H - 24FFFFH
32K-WORD
240000H - 247FFFH
32K-WORD
238000H - 23FFFFH
32K-WORD
230000H - 237FFFH
32K-WORD
228000H - 22FFFFH
32K-WORD
220000H - 227FFFH
32K-WORD
218000H - 21FFFFH
32K-WORD
210000H - 217FFFH
32K-WORD
208000H - 20FFFFH
32K-WORD
200000H - 207FFFH
2F8000H - 2FFFFFH
2F0000H - 2F7FFFH
2E8000H - 2EFFFFH
2E0000H - 2E7FFFH
2D8000H - 2DFFFFH
2D0000H - 2D7FFFH
2C8000H - 2CFFFFH
2C0000H - 2C7FFFH
2B8000H - 2BFFFFH
2B0000H - 2B7FFFH
2A8000H - 2AFFFFH
2A0000H - 2A7FFFH
298000H - 29FFFFH
290000H - 297FFFH
288000H - 28FFFFH
280000H - 287FFFH
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
76
78
79
80
81
82
83
77
84
85
66
68
69
70
71
67
86
88
89
90
91
87
122
123
124
102
103
104
105
32K-WORD
378000H - 37FFFFH
32K-WORD
370000H - 377FFFH
32K-WORD
368000H - 36FFFFH
32K-WORD
360000H - 367FFFH
32K-WORD
358000H - 35FFFFH
32K-WORD
350000H - 357FFFH
32K-WORD
348000H - 34FFFFH
32K-WORD
340000H - 347FFFH
32K-WORD
338000H - 33FFFFH
32K-WORD
330000H - 337FFFH
32K-WORD
328000H - 32FFFFH
32K-WORD
320000H - 327FFFH
32K-WORD
318000H - 31FFFFH
32K-WORD
310000H - 317FFFH
32K-WORD
308000H - 30FFFFH
32K-WORD
300000H - 307FFFH
3F0000H - 3F7FFFH
3E8000H - 3EFFFFH
3E0000H - 3E7FFFH
3D8000H - 3DFFFFH
3D0000H - 3D7FFFH
3C8000H - 3CFFFFH
3C0000H - 3C7FFFH
3B8000H - 3BFFFFH
3B0000H - 3B7FFFH
3A8000H - 3AFFFFH
3A0000H - 3A7FFFH
398000H - 39FFFFH
390000H - 397FFFH
388000H - 38FFFFH
380000H - 387FFFH
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
106
108
109
110
111
112
113
107
114
115
96
98
99
100
101
97
116
118
119
120
121
117
125
126
134
4K-WORD
Figure 2. Memory Map (Top Parameter)
Rev. 0.11
sharp
LHF64N14 8
NOTES:
1. The address A
21
-A
16
are shown in below table for reading the manufacturer code, device code,
device configuration code and OTP data.
2. Top parameter device has its parameter blocks in the plane3 (The highest address).
3. Block Address = The beginning location of a block address within the partition to which
the Read Identifier Codes/OTP command (90H) has been written.
DQ
15
-DQ
2
are reserved for future implementation.
4. RCRC=Read Configuration Register Code.
5. PCRC=Partition Configuration Register Code.
6. OTP-LK=OTP Block Lock configuration.
7. OTP=OTP Block data.
NOTES:
1. The address to read the identifier codes or OTP data is dependent on the partition which is selected
when writing the Read Identifier Codes/OTP command (90H).
2. Refer to Table 15 for the partition configuration register.
Table 3. Identifier Codes and OTP Address for Read Operation
Code
Address
[A
15
-A
0
]
Data
[DQ
15
-DQ
0
]
Notes
Manufacturer Code
Manufacturer Code
0000H
00B0H
1
Device Code
Top Parameter Device Code
0001H
00BAH
1, 2
Block Lock Configuration
Code
Block is Unlocked
Block
Address
+ 2
DQ
0
= 0
3
Block is Locked
DQ
0
= 1
3
Block is not Locked-Down
DQ
1
= 0
3
Block is Locked-Down
DQ
1
= 1
3
Device Configuration Code
Read Configuration Register
0005H
RCRC
1, 4
Partition Configuration Register
0006H
PCRC
1, 5
OTP
OTP Lock
0080H
OTP-LK
1, 6
OTP 0081-0088H
OTP
1,
7
Table 4. Identifier Codes and OTP Address for Read Operation on Partition Configuration
(1)
(64M-bit device)
Partition Configuration Register
(2)
Address (64M-bit device)
PCR.10
PCR.9
PCR.8
[A
21
-A
16
]
0
0
0
00H
0
0
1
00H or 10H
0
1
0
00H or 20H
1
0
0
00H or 30H
0
1
1
00H or 10H or 20H
1
1
0
00H or 20H or 30H
1
0
1
00H or 10H or 30H
1
1
1
00H or 10H or 20H or 30H
Rev. 0.11
sharp
LHF64N14 9
Customer Programmable Area Lock Bit (DQ
1
)
Factory Programmed Area Lock Bit (DQ
0
)
Customer Programmable Area
Factory Programmed Area
Reserved for Future Implementation
000080H
000081H
000084H
000085H
000088H
[A
21
-A
0
]
(DQ
15
-DQ
2)
Figure 3. OTP Block Address Map for OTP Program
(The area outside 80H~88H cannot be used.)
Rev. 0.11
sharp
LHF64N14 10
NOTES:
1. Refer to DC Characteristics. When V
PP
V
PPLK
, memory contents can be read, but cannot be altered.
2. X can be V
IL
or V
IH
for control pins and addresses, and V
PPLK
or V
PPH1/2
for V
PP
. See DC Characteristics for V
PPLK
and V
PPH1/2
voltages.
3. RST# at GND0.2V ensures the lowest power consumption.
4. Command writes involving block erase, (page buffer) program or OTP program are reliably executed when
V
PP
=V
PPH1/2
and V
CC
=1.7V-1.95V.
Command writes involving advanced factory program are reliably executed when V
PP
=V
PPH2
and V
CC
=1.7V-1.95V.
5. Refer to Table 6 for valid D
IN
during a write operation.
6. Never hold OE# low and WE# low at the same timing.
7. Refer to Appendix of LH28F640BN series for more information about query code.
8. WAIT indicates data valid in synchronous burst modes. WAIT is used only for synchronous burst mode.
Table 5. Bus Operation
(1, 2)
Mode
Notes RST#
CE#
OE#
WE#
ADV#
WP#
Address
V
PP
DQ
0-15
WAIT
Read Arra;y
6
V
IH
V
IL
V
IL
V
IH
V
IL
X
X
X
D
OUT
See
NOTE 8
Output Disable
V
IH
V
IL
V
IH
V
IH
X
X
X
X
High Z
V
IL
or V
IH
Standby
V
IH
V
IH
X
X
X
X
X
X
High Z
High Z
Reset
3
V
IL
X
X
X
X
X
X
X
High Z
High Z
Read Identifier
Codes/OTP
6
V
IH
V
IL
V
IL
V
IH
V
IL
X
See
Table 3 and
Table 4
X
See
Table 3 and
Table 4
V
IL
or V
IH
Read Query
6,7
V
IH
V
IL
V
IL
V
IH
V
IL
X
See
Appendix
X
See
Appendix
V
IL
or V
IH
Write
4,5,6
V
IH
V
IL
V
IH
V
IL
V
IL
X
X
X
D
IN
V
IL
or V
IH
Rev. 0.11
sharp
LHF64N14 11
NOTES:
1. Bus operations are defined in Table 5.
2. All addresses which are written at the first bus cycle should be the same as the addresses which are written at the second
bus cycle.
X=Any valid address within the device.
PA=Address within the selected partition.
IA=Identifier codes address (See Table 3 and Table 4).
QA=Query codes address. Refer to Appendix of LH28F640BN series for details.
BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit.
WA=Address of memory location for the Program command or the first address for the Page Buffer Program command.
WA0=First address for the Advanced Factory Program command.
OA=Address of OTP block to be read or programmed (See Figure 3).
RCRC=Read configuration register code presented on the addresses A
0
-A
15
.
PCRC=Partition configuration register code presented on the address A
0
-A
15
.
3. ID=Data read from identifier codes. (See Table 3 and Table 4).
QD=Data read from query database. Refer to Appendix of LH28F640BN series for details.
SRD=Data read from status register. See Table 10 and Table 11 for a description of the status register bits.
WD=Data to be programmed at location WA. Data is latched on the rising edge of WE# or CE# (whichever
goes high first) during command write cycles.
OD=Data within OTP block. Data is latched on the rising edge of WE# or CE# (whichever goes high first)
during command write cycles.
N-1=N is the number of the words to be loaded into a page buffer.
4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock
configuration code, read configuration register code, partition configuration register code and the data within OTP block
(See Table 3 and Table 4).
The Read Query command is available for reading CFI (Common Flash Interface) information.
Table 6. Command Definitions
(11)
Command
Bus
Cycles
Req'd
Notes
First Bus Cycle
Second Bus Cycle
Oper
(1)
Addr
(2)
Data
Oper
(1)
Addr
(2)
Data
(3)
Read Array
1
Write
PA
FFH
Read Identifier Codes/OTP
2
4
Write
PA
90H
Read
IA or OA
ID or OD
Read Query
2
4
Write
PA
98H
Read
QA
QD
Read Status Register
2
Write
PA
70H
Read
PA
SRD
Clear Status Register
1
Write
PA
50H
Block Erase
2
5
Write
BA
20H
Write
BA
D0H
Advanced Factory Program
2
5,9
Write
WA0
30H
Write
WA0
D0H
Program
2
5,6
Write
WA
40H or
10H
Write
WA
WD
Page Buffer Program
4
5,7
Write
WA
E8H
Write
WA
N-1
Block Erase and (Page Buffer)
Program Suspend
1
8,9
Write
PA
B0H
Block Erase and (Page Buffer)
Program Resume
1
8,9
Write
PA
D0H
Set Block Lock Bit
2
Write
BA
60H
Write
BA
01H
Clear Block Lock Bit
2
10
Write
BA
60H
Write
BA
D0H
Set Block Lock-down Bit
2
Write
BA
60H
Write
BA
2FH
OTP Program
2
9
Write
OA
C0H
Write
OA
OD
Set Read Configuration Register
2
Write
RCRC
60H
Write
RCRC
03H
Set Partition Configuration Register
2
Write
PCRC
60H
Write
PCRC
04H
Rev. 0.11
sharp
LHF64N14 12
5. Block erase, advanced factory program or (page buffer) program cannot be executed when the selected block is locked.
Unlocked block can be erased or programmed when RST# is V
IH
.
6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.
7. Following the third bus cycle, input the program sequential address and write data of "N" times. Finally, input the any
valid address within the target block to be programmed and the confirm command (D0H). Refer to Appendix of
LH28F640BN series for details.
8. If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the
suspended program operation should be resumed first, and then the suspended erase operation should be resumed next.
9. Advanced factory program and OTP program operations can not be suspended. The OTP Program command can not be
accepted while the block erase operation is being suspended.
10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when WP# is V
IL
. When
WP# is V
IH
, lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration.
11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be
used.
Rev. 0.11
sharp
LHF64N14 13
NOTES:
1. DQ
0
=1: a block is locked; DQ
0
=0: a block is unlocked.
DQ
1
=1: a block is locked-down; DQ
1
=0: a block is not locked-down.
2. Erase and program are general terms, respectively, to express: block erase, advanced factory
program and (page buffer) program operations.
3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is,
[001] (WP#=0) or [101] (WP#=1), regardless of the states before power-off or reset operation.
4. When WP# is driven to V
IL
in [110] state, the state changes to [011] and the blocks are
automatically locked.
5. OTP (One Time Program) block has the lock function which is different from those described
above.
NOTES:
1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit
command and "Set Lock-down" means Set Block Lock-Down Bit command.
2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ
0
=0), the
corresponding block is locked-down and automatically locked at the same time.
3. "No Change" means that the state remains unchanged after the command written.
4. In this state transitions table, assumes that WP# is not changed and fixed V
IL
or V
IH
.
Table 7. Functions of Block Lock
(5)
and Block Lock-Down
Current State
Erase/Program Allowed
(2)
State
WP#
DQ
1
(1)
DQ
0
(1)
State Name
[000]
0
0
0
Unlocked
Yes
[001]
(3)
0
0
1
Locked
No
[011]
0
1
1
Locked-down
No
[100]
1
0
0
Unlocked
Yes
[101]
(3)
1
0
1
Locked
No
[110]
(4)
1
1
0
Lock-down Disable
Yes
[111]
1
1
1
Lock-down Disable
No
Table 8. Block Locking State Transitions upon Command Write
(4)
Current State
Result after Lock Command Written (Next State)
State
WP#
DQ
1
DQ
0
Set Lock
(1)
Clear Lock
(1)
Set Lock-down
(1)
[000]
0
0
0
[001]
No Change
[011]
(2)
[001]
0
0
1
No Change
(3)
[000]
[011]
[011]
0
1
1
No Change
No Change
No Change
[100]
1
0
0
[101]
No Change
[111]
(2)
[101]
1
0
1
No Change
[100]
[111]
[110]
1
1
0
[111]
No Change
[111]
(2)
[111]
1
1
1
No Change
[110]
No Change
Rev. 0.11
sharp
LHF64N14 14
NOTES:
1. "WP#=0
1" means that WP# is driven to V
IH
and "WP#=1
0" means that WP# is driven to
V
IL
.
2. State transition from the current state [011] to the next state depends on the previous state.
3. When WP# is driven to V
IL
in [110] state, the state changes to [011] and the blocks are
automatically locked.
4. In this state transitions table, assumes that lock configuration commands are not written in
previous, current and next state.
Table 9. Block Locking State Transitions upon WP# Transition
(4)
Previous State
Current State
Result after WP# Transition (Next State)
State
WP#
DQ
1
DQ
0
WP#=0
1
(1)
WP#=1
0
(1)
-
[000]
0
0
0
[100]
-
-
[001]
0
0
1
[101]
-
[110]
(2)
[011]
0
1
1
[110]
-
Other than [110]
(2)
[111]
-
-
[100]
1
0
0
-
[000]
-
[101]
1
0
1
-
[001]
-
[110]
1
1
0
-
[011]
(3)
-
[111]
1
1
1
-
[011]
Rev. 0.11
sharp
LHF64N14 15
Table 10. Status Register Definition
R
R
R
R
R
R
R
R
15
14
13
12
11
10
9
8
WSMS
BESS
BES
PBPAFPOPS
VPPS
PBPSS
DPS
PPES
7
6
5
4
3
2
1
0
SR.15 - SR.8 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = BLOCK ERASE STATUS (BES)
1 = Error in Block Erase
0 = Successful Block Erase
SR.4 = (PAGE BUFFER) PROGRAM,
ADVANCED FACTORY PROGRAM AND
OTP PROGRAM STATUS (PBPAFPOPS)
1 = Error in (Page Buffer) Program,
Advanced Factory Program or OTP Program
0 = Successful (Page Buffer) Program,
Advanced Factory Program or OTP Program
SR.3 = V
PP
STATUS (VPPS)
1 = V
PP
LOW Detect, Operation Abort
0 = V
PP
OK
SR.2 = (PAGE BUFFER) PROGRAM SUSPEND
STATUS (PBPSS)
1 = (Page Buffer) Program Suspended
0 = (Page Buffer) Program in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Erase or Program Attempted on a
Locked Block, Operation Abort
0 = Unlocked
SR.0 = PARTITION PROGRAM AND ERASE STATUS
(PPES)
1 = Another Partition is busy.
AFP: Program or Verify busy.
0 = Depending on status of SR.7.
The addressed partition is busy or no partition is
busy.
AFP: Program or Verify done, AFP ready.
NOTES:
Status Register indicates the status of the partition, not WSM (Write
State Machine). Even if the SR.7 is "1", the WSM may be occupied
by the other partition when the device is set to 2, 3 or 4 partitions
configuration.
Check SR.7 to determine block erase, advanced factory program,
(page buffer) program or OTP program completion. SR.6 - SR.1 are
invalid while SR.7="0".
If both SR.5 and SR.4 are "1"s after a block erase, advanced factory
program, (page buffer) program, set/clear block lock bit, set block
lock-down bit, set read configuration register, set partition
configuration register attempt, an improper command sequence was
entered.
SR.3 does not provide a continuous indication of V
PP
level. The
WSM interrogates and indicates the V
PP
level only after Block
Erase, Advanced Factory Program, (Page Buffer) Program or OTP
Program command sequences. SR.3 is not guaranteed to report
accurate feedback when V
PP
V
PPH1
, V
PPH2
or V
PPLK
.
SR.1 does not provide a continuous indication of block lock bit. The
WSM interrogates the block lock bit only after Block Erase,
Advanced Factory Program, (Page Buffer) Program or OTP
Program command sequences. It informs the system, depending on
the attempted operation, if the block lock bit is set. Reading the
block lock configuration codes after writing the Read Identifier
Codes/OTP command indicates block lock bit status.
SR.15 - SR.8 are reserved for future use and should be masked out
when polling the status register.
If SR.7="0" and SR.0="0", the addressed partition is busy and other
partition is not busy. In AFP Mode, it indicates that the device is
finished programming or verifying data or is ready for data.
If SR.7="0" and SR.0="1", another partition is busy (the addressed
partition is not busy). In AFP Mode, it indicates that the device is
programming or verifying data.
If SR.7="1" and SR.0="0", no partition is busy. In AFP Mode, it
indicates that the device has exited AFP mode.
SR.7="1" and SR.0="1" will not occur.
Rev. 0.11
sharp
LHF64N14 16
Table 11. Extended Status Register Definition
R
R
R
R
R
R
R
R
15
14
13
12
11
10
9
8
SMS
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
XSR.15-8 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
XSR.7 = STATE MACHINE STATUS (SMS)
1 = Page Buffer Program available
0 = Page Buffer Program not available
XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
NOTES:
After issue a Page Buffer Program command (E8H),
XSR.7="1" indicates that the entered command is accepted.
If XSR.7 is "0", the command is not accepted and a next Page
Buffer Program command (E8H) should be issued again to
check if page buffer is available or not.
XSR.15-8 and XSR.6-0 are reserved for future use and
should be masked out when polling the extended status
register.
Rev. 0.11
sharp
LHF64N14 17
Table 12. Read Configuration Register Definition
RM
R
FC2
FC1
FC0
WT
DOC
WC
15
14
13
12
11
10
9
8
BS
CC
R
R
BW
BL2
BL1
BL0
7
6
5
4
3
2
1
0
RCR.15 = READ MODE (RM)
0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default)
RCR.14 = RESERVED FOR FUTURE ENHANCEMENTS
(R)
RCR.13-11 = FREQUENCY CONFIGURATION (FC2-0)
000 = Code 0 reserved for future use
001 = Code 1 reserved for future use
010 = Code 2
011 = Code 3
100 = Code 4
101 = Code 5
110 = Code 6 reserved for future use
111 = Code 7 reserved for future use (Default)
RCR.10 = WAIT SIGNAL POLARITY (WT)
0 = WAIT signal is active low
1 = WAIT signal is active high (Default)
RCR.9 = DATA OUTPUT CONFIGURATION (DOC)
0 = Hold Data for One Clock
1 = Hold Data for Two Clocks (Default)
RCR.8 = WAIT CONFIGURATION (WC)
0 = WAIT Asserted During Delay
1 = WAIT Asserted One Data Cycle Before Delay
(Default)
RCR.7 = BURST SEQUENCE (BS)
0 = Intel Burst Order
1 = Linear Burst Order (Default)
RCR.6 = CLOCK CONFIGURATION (CC)
0 = Burst Starts and Data Output on Falling Clock Edge
1 = Burst Starts and Data Output on Rising Clock Edge
(Default)
RCR.5-4 = RESERVED FOR FUTURE ENHANCEMENTS
(R)
RCR.3 = BURST WRAP (BW)
0 = Wrap Burst Reads within Burst Length set
by RCR.2-0
1 = No Wrap Burst Reads within Burst Length set
by RCR.2-0 (Default).
RCR.2-0 = BURST LENGTH (BL2-0)
001 = 4 Word Burst
010 = 8 Word Burst
011 = Reserved for future use
111 = Continuous (Linear) Burst (Default)
NOTES:
Read configuration register affects the read operations from
main and parameter blocks. Read operations for status
register, query code, identifier codes, OTP block and device
configuration codes support single read cycles.
RCR.14, RCR.5 and RCR.4 bits are reserved for future use
and should be masked out when checking the read
configuration register.
Refer to Frequency Configuration in Table 13 and Figure 4
for information about the frequency configuration RCR.13-
11.
Undocumented combinations of bits RCR.13-11 are reserved
for future implementations and should not be used.
Data is not ready when WAIT is active.
Refer to Figure 5 for information about Data Output
configuration RCR.9.
Refer to Table 14 for information about Burst Wrap
configuration RCR.3.
In the asynchronous page mode, the burst length always
equals 8 words.
All the bits in the read configuration register are set to "1"
after power-up or device reset.
When the bit RCR.15 is set to "1", other bits are invalid.
Rev. 0.11
sharp
LHF64N14 18
CLK (C)
ADV# (V)
A
20-0
(A)
DQ
15-0
(D/Q)
Code 2
Code 3
Code 4
VALID
ADDRESS
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
Code 5
VALID
OUTPUT
VALID
OUTPUT
DQ
15-0
(D/Q)
DQ
15-0
(D/Q)
DQ
15-0
(D/Q)
A
21-0
(A)
Table 13. Frequency Configuration Settings
Read Configuration Register
Frequency
Configuration Code
Input Clock Frequency
(V
CC
=1.7V-1.95V)
RCR.13
RCR.12
RCR.11
70ns
0
1
0
2
40MHz
0
1
1
3
52MHz
1
0
0
4
66MHz
1
0
1
5
TBD
Figure 4. Frequency Configuration
Rev. 0.11
sharp
LHF64N14 19
CLK (C)
1 CLK
DATA HOLD
DQ
15-0
(D/Q)
VALID
OUTPUT
VALID
OUTPUT
2 CLK
DATA HOLD
DQ
15-0
(D/Q)
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
NOTE:
1. The burst wrap bit (RCR.3) determines whether 4- or 8-word burst-accesses wrap within the burst-length boundary or
whether they cross word-length boundaries to perform linear accesses.
Table 14. Read Sequence and Burst Length
Starting
Address
[Decimal]
Burst
Wrap
(1)
(RCR.3=)
Burst Addressing Sequence [Decimal]
4-Word Burst Length
(RCR.2-0=001)
8-Word Burst Length
(RCR.2-0=010)
Cotinuous Burst
(RCR.2-0=111)
Linear
Intel
Linear
Intel
Linear
0
0
0-1-2-3
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6...
1
0
1-2-3-0
1-0-3-2
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
1-2-3-4-5-6-7...
2
0
2-3-0-1
2-3-0-1
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
2-3-4-5-6-7-8...
3
0
3-0-1-2
3-2-1-0
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
3-4-5-6-7-8-9...
4
0
4-5-6-7
4-5-6-7
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
4-5-6-7-8-9-10...
5
0
5-6-7-4
5-4-7-6
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
5-6-7-8-9-10-11...
6
0
6-7-4-5
6-7-4-5
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
6-7-8-9-10-11-12...
7
0
7-4-5-6
7-6-5-4
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
7-8-9-10-11-12-13...
...
...
...
...
...
...
...
14
0
14-15-12-13 14-15-12-13
14-15-8-9-
10-11-12-13
14-15-12-13-
10-11-8-9
14-15-16-17-18-19-20...
15
0
15-12-13-14 15-14-13-12
15-8-9-10-
11-12-13-14
15-14-13-12-
11-10-9-8
15-16-17-18-19-20-21...
...
...
...
...
...
...
...
0
1
0-1-2-3
NA
0-1-2-3-4-5-6-7
NA
0-1-2-3-4-5-6...
1
1
1-2-3-4
NA
1-2-3-4-5-6-7-8
NA
1-2-3-4-5-6-7...
2
1
2-3-4-5
NA
2-3-4-5-6-7-8-9
NA
2-3-4-5-6-7-8...
3
1
3-4-5-6
NA
3-4-5-6-7-8-9-10
NA
3-4-5-6-7-8-9...
4
1
4-5-6-7
NA
4-5-6-7-8-9-10-11
NA
4-5-6-7-8-9-10...
5
1
5-6-7-8
NA
5-6-7-8-9-10-11-12
NA
5-6-7-8-9-10-11...
6
1
6-7-8-9
NA
6-7-8-9-
10-11-12-13
NA
6-7-8-9-10-11-12...
7
1
7-8-9-10
NA
7-8-9-10-
11-12-13-14
NA
7-8-9-10-11-12-13...
...
...
...
...
...
...
...
14
1
14-15-16-17
NA
14-15-16-17-
18-19-20-21
NA
14-15-16-17-18-19-20...
15
1
15-16-17-18
NA
15-16-17-18-
19-20-21-22
NA
15-16-17-18-19-20-21...
Figure 5. Data Output Configuration
Rev. 0.11
sharp
LHF64N14 20
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION1
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PARTITION1
PARTITION1
PARTITION0
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION1
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PLANE1
PLANE0
PLANE2
PLANE3
PARTITION0
PARTITION1
PARTITION1
PARTITION0
PARTITION2
PARTITION3
PARTITION2
PARTITION2
PARTITION1
PARTITION2
0
0
0
0
0
1
0
1
0
1
0
0
0
1
1
1
1
0
1
0
1
1
1
1
PC2 PC1PC0
PARTITIONING FOR DUAL WORK
PARTITIONING FOR DUAL WORK
PC2 PC1PC0
Table 15. Partition Configuration Register Definition
R
R
R
R
R
PC2
PC1
PC0
15
14
13
12
11
10
9
8
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
PCR.15-11 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
PCR.10-8 = PARTITION CONFIGURATION (PC2-0)
000 = No partitioning. Dual Work is not allowed.
001 = Plane1-3 are merged into one partition.
(default in a bottom parameter device)
010 = Plane 0-1 and Plane2-3 are merged into one
partition respectively.
100 = Plane 0-2 are merged into one partition.
(default in a top parameter device)
011 = Plane 2-3 are merged into one partition. There are
three partitions in this configuration. Dual work
operation is available between any two partitions.
110 = Plane 0-1 are merged into one partition. There are
three partitions in this configuration. Dual work
operation is available between any two partitions.
101 = Plane 1-2 are merged into one partition. There are
three partitions in this configuration. Dual work
operation is available between any two partitions.
111 = There are four partitions in this configuration.
Each plane corresponds to each partition respec-
tively. Dual work operation is available between any
two partitions.
PCR.7-0 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
NOTES:
After power-up or device reset, PCR10-8 (PC2-0) is set to
"001" in a bottom parameter device and "100" in a top
parameter device.
See Figure 6 for the detail on partition configuration.
PCR.15-11 and PCR.7-0 are reserved for future use and
should be masked out when checking the partition
configuration register.
Figure 6. Partition Configuration
Rev. 0.11
sharp
LHF64N14 21
1 Electrical Specifications
1.1 Absolute Maximum Ratings
*
Operating Temperature
During Read, Erase and Program ...-40
C to +85C
(1)
Storage Temperature
During under Bias............................... -40
C to +85C
During non Bias................................ -65
C to +125C
Voltage On Any Pin
(except V
CC
and V
PP
).............. -0.5V to V
CC
+0.5V
(2)
V
CC
and V
CCQ
Supply Voltage ........ -0.2V to +2.45V
(2)
V
PP
Supply Voltage .................... -0.2V to +12.6V
(2, 3, 4)
Output Short Circuit Current ........................... 100mA
(5)
*WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent
damage. These are stress ratings only. Operation
beyond the "Operating Conditions" is not
recommended and extended exposure beyond the
"Operating Conditions" may affect device
reliability.
NOTES:
1. Operating temperature is for extended temperature
product defined by this specification.
2. All specified voltages are with respect to GND.
Minimum DC voltage is -0.5V on input/output pins and
-0.2V on V
CC
and V
PP
pins. During transitions, this
level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input/output pins is
V
CC
+0.5V which, during transitions, may overshoot to
V
CC
+2.0V for periods <20ns.
3. Maximum DC voltage on V
PP
may overshoot to
+13.0V for periods <20ns.
4. V
PP
erase/program voltage is normally 1.7V-1.95V.
Applying 11.7V-12.3V to V
PP
during erase/program
can be done for a maximum of 1,000 cycles on the
main blocks and 1,000 cycles on the parameter blocks.
V
PP
may be connected to 11.7V-12.3V for a total of 80
hours maximum.
5. Output shorted for no more than one second. No more
than one output shorted at a time.
1.2 Operating Conditions
NOTES:
1. See DC Characteristics tables for voltage range-specific specification.
2. Applying V
PP
=11.7V-12.3V during a erase or program can be done for a maximum of 1,000 cycles on the main blocks
and 1,000 cycles on the parameter blocks. A permanent connection to V
PP
=11.7V-12.3V is not allowed and can cause
damage to the device.
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
Operating Temperature
T
A
-40
+25
+85
C
V
CC
Supply Voltage
V
CC
1.7
1.8
1.95
V
1
I/O Supply Voltage
V
CCQ
1.7
1.8
1.95
V
1
V
PP
Voltage when Used as a Logic Control
V
PPH1
0.90
1.8
1.95
V
1
V
PP
Supply Voltage
V
PPH2
11.7
12
12.3
V
1, 2
Main Block Erase Cycling: V
PP
=V
PPH1
100,000
Cycles
Parameter Block Erase Cycling: V
PP
=V
PPH1
100,000
Cycles
Main Block Erase Cycling: V
PP
=V
PPH2
, 80 hrs.
1,000
Cycles
Parameter Block Erase Cycling: V
PP
=V
PPH2
, 80 hrs.
1,000
Cycles
Maximum V
PP
hours at V
PPH2
80
Hours
Rev. 0.11
sharp
LHF64N14 22
TEST POINTS
V
CCQ
/2
V
CCQ
/2
INPUT
V
CCQ
0.0
OUTPUT
AC test inputs are driven at V
CCQ
(min) for a Logic "1" and 0.0V for a Logic "0".
Input timing begins, and output timing ends at V
CCQ
/2. Input rise and fall times (10% to 90%) < 5ns.
Worst case speed conditions are when V
CC
=V
CC
(min).
DEVICE
UNDER
TEST
RL=3.3k
CL
V
CCQ
(min)/2
OUT
CL Includes Jig
Capacitances.
1N914
Figure 7. Transient Input/Output Reference Waveform for V
CC
=1.7V-1.95V
Figure 8. Transient Equivalent Testing Load Circuit
Table 16. Configuration Capacitance Loading Value
Test Configuration
C
L
(pF)
V
CC
=1.7V-1.95V
50
1.2.2 AC Input/Output Conditions
1.2.1 Capacitance
(1)
(T
A
=
+25C, f=1MHz)
NOTE:
1. Sampled, not 100% tested.
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Input Capacitance
C
IN
V
IN
=0.0V
6
8
pF
CE# Input Capacitance
C
CE
V
IN
=0.0V
10
12
pF
Output Capacitance
C
OUT
V
OUT
=0.0V
10
12
pF
Rev. 0.11
sharp
LHF64N14 23
1.2.3 DC Characteristics
V
CC
=1.7V-1.95V
Symbol
Parameter
Notes
Min.
Typ.
Max.
Unit
Test Conditions
I
LI
Input Load Current
1
-1.0
+1.0
A
V
CC
=V
CC
Max.,
V
CCQ
=V
CCQ
Max.,
V
IN
/V
OUT
=V
CCQ
or
GND
I
LO
Output Leakage Current
1
-1.0
+1.0
A
I
CCS
V
CC
Standby Current
1
4
20
A
V
CC
=V
CC
Max.,
CE#=RST#=
V
CCQ
0.2V,
WP#, ADV#=
V
CCQ
or GND
I
CCAS
V
CC
Automatic Power Savings Current
1,5
4
20
A
V
CC
=V
CC
Max.,
CE#=GND0.2V,
WP#, ADV#=
V
CCQ
or GND
I
CCD
V
CC
Reset Power-Down Current
1
4
20
A
RST#=GND0.2V
I
CCR
Average V
CC
Read
Current
Normal Mode
1,7
15
25
mA
V
CC
=V
CC
Max.,
CE#=V
IL
,
OE#=V
IH
,
f=5MHz
Average V
CC
Read
Current
Page Mode
8 Word Read
1,7
5
10
mA
Average V
CC
Read
Current
Synchronous
CLK=52MHz
Burst Length=4
1,3,8
15
20
mA
V
CC
=V
CC
Max.,
CE#=V
IL
,
OE#=V
IH
,
f=52MHz
Burst Length=8
1,3,8
15
20
mA
Burst Length=
Continuous
1,3,8
25
30
mA
Average V
CC
Read
Current
Synchronous
CLK=66MHz
Burst Length=4
1,3,8
20
25
mA
V
CC
=V
CC
Max.,
CE#=V
IL
,
OE#=V
IH
,
f=66MHz
Burst Length=8
1,3,8
20
25
mA
Burst Length=
Continuous
1,3,8
32
38
mA
I
CCW
V
CC
(Page Buffer) Program,
Advanced Factory Program Current
1,6,8
20
60
mA
V
PP
=V
PPH1
1,6,8
10
20
mA
V
PP
=V
PPH2
I
CCE
V
CC
Block Erase Current
1,6,8
10
30
mA
V
PP
=V
PPH1
1,6,8
4
10
mA
V
PP
=V
PPH2
I
CCWS
I
CCES
V
CC
(Page Buffer) Program or
Block Erase Suspend Current
1,2,8
10
200
A
CE#=V
IH
I
PPS
I
PPR
V
PP
Standby or Read Current
1,7,8
2
5
A
V
PP
V
CC
I
PPW
V
PP
(Page Buffer) Program,
Advanced Factory Program Current
1,6,7,8
2
5
A
V
PP
=V
PPH1
1,6,7,8
10
30
mA
V
PP
=V
PPH2
I
PPE
V
PP
Block Erase Current
1,6,7,8
2
5
A
V
PP
=V
PPH1
1,6,7,8
5
15
mA
V
PP
=V
PPH2
Rev. 0.11
sharp
LHF64N14 24
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values are the reference values at V
CC
=1.8V and T
A
=+25
C
unless V
CC
is specified.
2. I
CCWS
and I
CCES
are specified with the device de-selected. If read or (page buffer) program is executed while in block
erase suspend mode, the device's current draw is the sum of I
CCES
and I
CCR
or I
CCW
. If read is executed while in (page
buffer) program suspend mode, the device's current draw is the sum of I
CCWS
and I
CCR
.
3. The burst wrap bit (RCR.3) determines whether 4- or 8-word burst-accesses wrap within the burst-length boundary or
whether they cross word-length boundaries to perform linear accesses.
4. Block erase, advanced factory program, (page buffer) program and OTP program are inhibited when V
PP
V
PPLK
, and not
guaranteed in the range between V
PPLK
(max.) and V
PPH1
(min.), between V
PPH1
(max.) and V
PPH2
(min.) and above
V
PPH2
(max.).
5. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle
completion. Standard address access timings (t
AVQV
) provide new data when addresses are changed.
6. Sampled, not 100% tested.
7. V
PP
is not used for power supply pin. With V
PP
V
PPLK
, block erase, advanced factory program, (page buffer) program
and OTP program cannot be executed and should not be attempted.
Applying 12V0.3V to V
PP
provides fast erasing or fast programming mode. In this mode, V
PP
is power supply pin and
supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths
and layout considerations given to the V
CC
power bus.
Applying 12V0.3V to V
PP
during erase/program can only be done for a maximum of 1,000 cycles on each block. V
PP
may be connected to 12V0.3V for a total of 80 hours maximum.
8. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane.
I
PPWS
V
PP
(Page Buffer) Program
Suspend Current
1,7,8
2
5
A
V
PP
=V
PPH1
1,7,8
10
200
A
V
PP
=V
PPH2
I
PPES
V
PP
Block Erase Suspend Current
1,7,8
2
5
A
V
PP
=V
PPH1
1,7,8
10
200
A
V
PP
=V
PPH2
V
IL
Input Low Voltage
6
-0.4
0.4
V
V
IH
Input High Voltage
6
V
CCQ
-0.4
V
CCQ
+ 0.4
V
V
OL
Output Low Voltage
6
0.1
V
V
CC
=V
CC
Min.,
V
CCQ
=V
CCQ
Min.,
I
OL
=100
A
V
OH
Output High Voltage
6
V
CCQ
-0.1
V
V
CC
=V
CC
Min.,
V
CCQ
=V
CCQ
Min.,
I
OH
=-100 A
V
PPLK
V
PP
Lockout during Normal
Operations
4,6,7
0.4
V
V
PPH1
V
PP
during Block Erase, (Page Buffer)
Program or OTP Program Operations
7
0.9
1.8
1.95
V
V
PPH2
V
PP
during Block Erase, Advanced
Factory Program, (Page Buffer)
Program or OTP Program Operations
7
11.7
12
12.3
V
V
LKO
V
CC
Lockout Voltage
1.0
V
V
CC
=1.7V-1.95V
Symbol
Parameter
Notes
Min.
Typ.
Max.
Unit
Test Conditions
DC Characteristics (Continued)
Rev. 0.11
sharp
LHF64N14 25
1.2.4 AC Characteristics - Read-Only Operations
(1)
NOTES:
1. See AC input/output reference waveform for timing measurements and maximum allowable input slew rate.
2. Sampled, not 100% tested.
3. Applies only to subsequent synchronous reads.
4. OE# may be delayed up to t
ELQV
t
GLQV
after the falling edge of CE# without impact to t
ELQV
.
V
CC
=1.7V-1.95V, T
A
=-40
C to +85C
Symbol
Parameter
Notes
Min.
Max.
Unit
t
CLK
CLK Period
15
ns
t
CH
(t
CL
)
CLK High (Low) Time
5
ns
t
CHCL
(t
CLCH
) CLK Fall (Rise) Time
2.5
ns
t
AVCH
Address Setup to CLK
9
ns
t
VLCH
ADV# Setup to CLK
10
ns
t
ELCH
CE# Setup to CLK
9
ns
t
CHQV
CLK to Output Delay
14
ns
t
CHQX
Output Hold from CLK
3
ns
t
CHAX
Address Hold from CLK
10
ns
t
CHTV
CLK to WAIT Valid
14
ns
t
ELTV
CE# Low to WAIT Valid
14
ns
t
EHTZ
CE# High to WAIT High Z
20
ns
t
EHEL
CE# High between Subsequent Synchronous Reads
3
15
ns
t
AVVH
Address Setup to ADV#
10
ns
t
ELVH
CE# Setup to ADV#
10
ns
t
AVAV
Read Cycle Time
70
ns
t
AVQV
Address to Output Delay
70
ns
t
ELQV
CE# to Output Delay
4
70
ns
t
VLQV
ADV# to Output Delay
70
ns
t
VLVH
ADV# Pulse Width Low
10
ns
t
VHVL
ADV# Pulse Width High
10
ns
t
VHAX
Address Hold from ADV#
9
ns
t
APA
Page Address Access Time
20
ns
t
GLQV
OE# to Output Delay
4
20
ns
t
PHQV
RST# High to Output Delay
150
ns
t
EHQZ
, t
GHQZ
CE# or OE# to Output in High Z, Whichever Occurs First
2
15
ns
t
ELQX
CE# to Output in Low Z
2
0
ns
t
GLQX
OE# to Output in Low Z
2
0
ns
t
OH
Output Hold from First Occurring Address, CE# or OE# change
2
0
ns
Rev. 0.11
sharp
LHF64N14 26
CLK (C)
t
CLK
t
CL
t
CHCL
t
CLCH
t
CH
t
AVQV
t
AVVH
t
VLVH
t
VHVL
t
EHQZ
t
GHQZ
t
VHAX
t
VLQV
t
ELQV
t
PHQV
t
ELVH
t
GLQV
t
OH
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
V
IH
V
IL
(P)
(D/Q)
(T)
(W)
(G)
(E)
(V)
(A)
A
20-0
DQ
15-0
ADV#
CE#
OE#
WAIT
WE#
RST#
VALID
ADDRESS
VALID
OUTPUT
High Z
t
ELQX
t
GLQX
High Z
NOTE 1
High Z
t
AVAV
NOTE:
1. WAIT shown active low.
A
21-0
(A)
Figure 9. AC Waveform for CLK Input
Figure 10. AC Waveform for Single Asynchronous Read Operations
from Status Register, Identifier Codes, OTP Block or Query Code
Rev. 0.11
sharp
LHF64N14 27
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
t
AVQV
t
VLVH
t
VHVL
t
VLQV
t
ELQV
t
ELVH
t
VHAX
t
EHQZ
t
GHQZ
t
OH
t
APA
t
PHQV
High Z
t
AVVH
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
(P)
(D/Q)
(W)
(G)
(E)
(V)
(A)
A
20-3
V
IH
V
IL
(A)
A
2-0
DQ
15-0
ADV#
CE#
OE#
WE#
(T)
WAIT
RST#
VALID
ADDRESS
t
GLQV
t
ELQX
t
GLQX
V
OH
V
OL
High Z
NOTE 1
High Z
t
AVAV
NOTE:
1. WAIT shown active low.
A
21-3
(A)
Figure 11. AC Waveform for Asynchronous 4-Word Page Mode
Read Operations from Main Blocks or Parameter Blocks
Rev. 0.11
sharp
LHF64N14 28
Figure 12. AC Waveform for Asynchronous 8-Word Page Mode
Read Operations from Main Blocks or Parameter Blocks
VALID
ADDRESS
t
AVQV
t
VLVH
t
VHVL
t
VLQV
t
ELQV
t
ELVH
t
VHAX
t
EHQZ
t
GHQZ
t
OH
t
APA
t
PHQV
t
AVVH
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
(P)
(D/Q)
(W)
(G)
(E)
(V)
(A)
A
20-3
(A)
A
2-0
DQ
15-0
ADV#
CE#
OE#
WE#
(T)
WAIT
RST#
t
GLQV
t
ELQX
t
GLQX
V
OH
V
OL
High Z
NOTE 1
High Z
t
AVAV
V
IH
V
IL
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
High Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
NOTE:
1. WAIT shown active low.
A
21-3
(A)
Rev. 0.11
sharp
LHF64N14 29
V
IH
V
IL
VALID
OUTPUT
VALID
ADDRESS
t
AVVH
t
AVCH
t
CHAX
t
VHAX
t
AVQV
t
VLVH
t
VLCH
t
VLQV
t
CHQV
t
GHQZ
t
EHQZ
t
ELVH
t
ELCH
t
ELQV
t
OH
t
CHQX
t
VHVL
High Z
NOTE 1
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
(D/Q)
(W)
(G)
(E)
(V)
(A)
A
20-0
V
IH
V
IL
(C)
CLK
DQ
15-0
ADV#
CE#
OE#
WE#
t
GLQV
t
ELQX
t
GLQX
NOTE:
1. Depending upon the frequency configuration code in the read configuration register, insert clock cycles:
Frequency Configuration Code 2, insert two clock cycles
Frequency Configuration Code 3, insert three clock cycles
Frequency Configuration Code 4, insert four clock cycles
Frequency Configuration Code 5, insert five clock cycles
2. WAIT (shown active low) configuration allows assertion one CLK cycle before or during an output delay.
V
OH
V
OL
(T)
WAIT
High Z
NOTE 2
High Z
t
ELTV
t
CHTV
t
EHTZ
Figure 13. AC Waveform for Single Synchronous Read Operations
from Status Register, Identifier Codes, OTP Block or Query Code
A
21-0
(A)
Rev. 0.11
sharp
LHF64N14 30
V
IH
V
IL
VALID
ADDRESS
t
AVVH
t
AVCH
t
CHAX
t
VHAX
t
AVQV
t
VLVH
t
VLCH
t
VLQV
t
GHQZ
t
EHQZ
t
ELVH
t
ELCH
t
ELQV
t
OH
t
CHQX
t
CHQV
t
VHVL
High Z
NOTE 1
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
(D/Q)
(W)
(G)
(E)
(V)
(A)
A
20-0
V
IH
V
IL
(C)
CLK
DQ
15-0
ADV#
CE#
OE#
WE#
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
t
ELQX
t
GLQX
NOTE:
1. Depending upon the frequency configuration code in the read configuration register, insert clock cycles:
Frequency Configuration Code 2, insert two clock cycles
Frequency Configuration Code 3, insert three clock cycles
Frequency Configuration Code 4, insert four clock cycles
Frequency Configuration Code 5, insert five clock cycles
2. WAIT (shown active low) configuration allows assertion one CLK cycle before or during an output delay.
t
GLQV
V
OH
V
OL
(T)
WAIT
High Z
NOTE 2
High Z
t
ELTV
t
CHTV
t
EHTZ
Figure 14. AC Waveform for Synchronous Burst Mode Read Operations
from Main Blocks or Parameter Blocks (4 Word Burst: RCR.2-0=001)
A
21-0
(A)
Rev. 0.11
sharp
LHF64N14 31
V
IH
V
IL
VALID
ADDRESS
t
AVVH
t
AVCH
t
CHAX
t
VH AX
t
AVQV
t
VLVH
t
VLCH
t
VLQV
t
ELVH
t
ELCH
t
ELQV
t
VHVL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
(W)
(G)
(E)
(V)
(A)
A
20-0
V
IH
V
IL
(C)
CLK
ADV#
CE#
OE#
WE#
NOTE:
1. WAIT (shown active low) configuration allows assertion one CLK cycle before or during an output delay.
V
OH
V
OL
(D/Q)
DQ
15-0
High Z
V
OH
V
OL
(D/Q)
DQ
15-0
High Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
V
OH
V
OL
(D/Q)
DQ
15-0
High Z
V
OH
V
OL
(T)
WAIT
High Z
NOTE 1
t
ELTV
V
OH
V
OL
(T)
WAIT
High Z
NOTE 1
t
ELTV
t
CHTV
V
OH
V
OL
(T)
WAIT
High Z
NOTE 1
t
ELTV
t
CHTV
t
CHTV
INVALID
OUTPUT
INVALID
OUTPUT
INVALID
OUTPUT
INVALID
OUTPUT
INVALID
OUTPUT
INVALID
OUTPUT
t
CHTV
t
CHTV
t
CHQV
t
CHQX
t
ELQX
t
GLQX
t
GL QV
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
INVALID
OUTPUT
INVALID
OUTPUT
t
CHQV
t
CHQX
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
t
CHQV
t
CHQX
4 Word Burst: RCR.2-0 = 001
8 Word Burst: RCR.2-0 = 010
Continuous Burst: RCR.2-0 = 111
Figure 15. AC Waveform for Synchronous Burst Mode Read Operations
from Main Blocks or Parameter Blocks (Frequency Configuration: RCR.13-11=010)
A
21-0
(A)
Rev. 0.11
sharp
LHF64N14 32
VALID
OUTPUT
INVALID
OUTPUT
NOTE 2
NOTE 1
VALID
OUTPUT
VALID
OUTPUT
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
(D/Q)
(W)
(G)
(E)
(V)
(A)
A
20-0
V
IH
V
IL
(C)
CLK
DQ
15-0
ADV#
CE#
OE#
WE#
V
OH
V
OL
(T)
WAIT
t
CHTV
t
CHQX
t
CHQV
t
CHQX
NOTES:
1. This delay occurs only in continuous burst mode or 4-, 8-word burst with no-wrap mode.
2. WAIT (shown active low) configuration allows assertion one CLK cycle before or during an output delay.
Figure 16. AC Waveform for an Output Delay when Continuous Burst Read
with Data Output Configurations Set to One Clock
A
21-0
(A)
Rev. 0.11
sharp
LHF64N14 33
1.2.5 AC Characteristics - Write Operations
(1), (2)
NOTES:
1. The timing characteristics for reading the status register during block erase, advanced factory program, (page buffer)
program and OTP program operations are the same as during read-only operations. Refer to AC Characteristics for read-
only operations.
2. A write operation can be initiated and terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Write pulse width (t
WP
) is defined from the falling edge of CE# or WE# (whichever goes low last) to the rising edge of
CE# or WE# (whichever goes high first). Hence, t
WP
=t
WLWH
=t
ELEH
=t
WLEH
=t
ELWH
.
5. Write pulse width high (t
WPH
) is defined from the rising edge of CE# or WE# (whichever goes high first) to the falling
edge of CE# or WE# (whichever goes low last). Hence, t
WPH
=t
WHWL
=t
EHEL
=t
WHEL
=t
EHWL
.
6. V
PP
should be held at V
PP
=V
PPH1/2
until determination of block erase, (page buffer) program or OTP program success
(SR.1/3/4/5=0) and held at V
PP
=V
PPH2
until determination of advanced factory program success (SR.0/1/3/4=0).
7. t
WHR0
(t
EHR0
) after the Read Query or Read Identifier Codes/OTP command=t
AVQV
+100ns.
8. Refer to Table 6 for valid address and data for block erase, advanced factory program, (page buffer) program, OTP
program or lock bit configuration.
V
CC
=1.7V-1.95V, T
A
=-40
C to +85C
Symbol
Parameter
Notes
Min.
Max.
Unit
t
AVAV
Write Cycle Time
70
ns
t
PHWL
(t
PHEL
)
RST# High Recovery to WE# (CE#) Going Low
3
150
ns
t
ELWL
(t
WLEL
)
CE# (WE#) Setup to WE# (CE#) Going Low
0
ns
t
WLWH
(t
ELEH
)
WE# (CE#) Pulse Width
4
45
ns
t
VLVH
ADV# Pulse Width
10
ns
t
DVWH
(t
DVEH
)
Data Setup to WE# (CE#) Going High
8
45
ns
t
AVWH
(t
AVEH
)
Address Setup to WE# (CE#) Going High
8
45
ns
t
VLWH
(t
VLEH
)
ADV# Setup to WE# (CE#) Going High
45
ns
t
AVVH
Address Setup to ADV# Going High
10
ns
t
WHEH
(t
EHWH
)
CE# (WE#) Hold from WE# (CE#) High
0
ns
t
WHDX
(t
EHDX
)
Data Hold from WE# (CE#) High
0
ns
t
WHAX
(t
EHAX
)
Address Hold from WE# (CE#) High
0
ns
t
VHAX
Address Hold from ADV# High
9
ns
t
WHWL
(t
EHEL
)
WE# (CE#) Pulse Width High
5
25
ns
t
SHWH
(t
SHEH
)
WP# High Setup to WE# (CE#) Going High
3
0
ns
t
VVWH
(t
VVEH
)
V
PP
Setup to WE# (CE#) Going High
3
200
ns
t
WHGL
(t
EHGL
)
Write Recovery before Read
30
ns
t
QVSL
WP# High Hold from Valid SRD
3, 6
0
ns
t
QVVL
V
PP
Hold from Valid SRD
3, 6
0
ns
t
WHR0
(t
EHR0
)
WE# (CE#) High to SR.7 Going "0"
3, 7
t
AVQV
+
19
ns
Rev. 0.11
sharp
LHF64N14 34
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
DATA IN
DATA IN
VALID
SRD
t
AVVH
t
VHVL
t
VLVH
t
VHAX
t
AVWH
(t
AVEH
)
t
VLWH
(t
VLEH
)
t
WHAX
(t
EHAX
)
t
ELWL
(t
WLEL
)
t
PHWL
(t
PHEL
)
t
WLWH
t
WHWL
(t
EHEL
)
t
WHDX
(t
EHDX
)
t
DVWH
(t
DVEH
)
t
SHWH
(t
SHEH
)
t
VVWH
(t
VVEH
)
t
WHQV1,2,3
(t
EHQV1,2,3
)
t
QVSL
t
QVVL
t
WHEH
(t
EHWH
)
t
WHGL
(t
EHGL
)
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
(D/Q)
(W)
(G)
(E)
(V)
(A)
NOTE 1
NOTE 2
NOTE 3
NOTES 5, 6
NOTE 4
NOTE 6
NOTE 5
A
20-0
DQ
15-0
(V)
V
PP
V
IH
V
PPH1,2
V
PPLK
V
IL
V
IL
(P)
RST#
ADV#
CE#
OE#
WE#
V
IH
V
IL
(S)
WP#
NOTES:
1. V
CC
power-up and standby.
2. Write each first cycle command.
3. Write each second cycle command or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. For read operation, OE#, CE# and ADV# must be driven active, and WE# de-asserted.
(t
ELEH
)
"1"
"0"
(R)
SR.7
t
WHR0
(t
EHR0
)
t
AVAV
NOTES 5, 6
Figure 17. AC Waveform for Write Operations
A
21-0
(A)
Rev. 0.11
sharp
LHF64N14 35
ABORT
COMPLETE
t
PLPH
t
PLPH
t
2VPH
t
PLRH
t
PHQV
t
PHQV
(A) Reset during Read Array Mode
(B) Reset during Erase or Program Mode
(C) RST# rising timing
RST#
RST#
V
IL
V
IH
V
IL
V
IH
V
CC
GND
V
CC
(min)
RST#
V
IL
V
IH
SR.7="1"
V
OH
V
OL
(D/Q)
DQ
15-0
VALID
OUTPUT
High Z
(P)
(P)
(P)
V
OH
V
OL
(D/Q)
DQ
15-0
VALID
OUTPUT
High Z
V
OH
V
OL
(D/Q)
DQ
15-0
VALID
OUTPUT
High Z
t
PHQV
t
VHQV
NOTES:
1. A reset time, t
PHQV
, is required from the later of SR.7 going "1" or RST# going high until outputs are valid. Refer to AC
Characteristics - Read-Only Operations for t
PHQV
.
2. t
PLPH
is <100ns the device may still reset but this is not guaranteed.
3. Sampled, not 100% tested.
4. If RST# asserted while a block erase, advanced factory program, (page buffer) program or OTP program operation is not
executing, the reset will complete within 100ns.
5. When the device power-up, holding RST# low minimum 100ns is required after V
CC
has been in predefined range and
also has been in stable there.
Reset AC Specifications (V
CC
=1.7V-1.95V, T
A
=-40
C to +85C)
Symbol
Parameter
Notes
Min.
Max.
Unit
t
PLPH
RST# Low to Reset during Read
(RST# should be low during power-up.)
1, 2, 3
100
ns
t
PLRH
RST# Low to Reset during Erase or Program
1, 3, 4
20
s
t
2VPH
V
CC
1.7V to RST# High
1, 3, 5
100
ns
t
VHQV
V
CC
1.7V to Output Delay
3
1
ms
Figure 18. AC Waveform for Reset Operations
1.2.6 Reset Operations
Rev. 0.11
sharp
LHF64N14 36
1.2.7 Block Erase, Advanced Factory Program, (Page Buffer) Program and OTP Program
Performance
(3)
NOTES:
1. Typical values measured at V
CC
=1.8V, V
PP
=1.8V or 12V, and T
A
=+25
C. Assumes corresponding lock bits
are not set. Subject to change based on device characterization.
2. Excludes external system-level overhead.
3. Sampled, but not 100% tested.
4. A latency time is required from writing suspend command (WE# or CE# going high) until SR.7 going "1".
5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter
than t
ERES
and its sequence is repeated, the block erase operation may not be finished.
6. AFP mode is allowed only when T
A
=+20
C to +30C.
7. In AFP mode, eight 4K-word parameter blocks are programmed at a time. Specification shown above is the program time
per each 4K-word parameter block.
V
CC
=1.7V-1.95V, T
A
=-40
C to +85C
Symbol
Parameter
Notes
PBP (Page
Buffer) is
Used, AFP
(Advanced
Factory
Program) is
Used or not
V
PP
=V
PPH1
(In System)
V
PP
=V
PPH2
(In Manufacturing)
Unit
Min.
Typ.
(1)
Max.
(2)
Min.
Typ.
(1)
Max.
(2)
t
WPB
4K-Word Parameter Block
Program Time
2
-
0.09
0.23
0.04
0.07
s
2
PBP
0.05
0.2
0.02
0.06
s
2, 6, 7
AFP
-
-
0.015
-
s
t
WMB
32K-Word Main Block
Program Time
2
-
0.72
1.8
0.31
0.6
s
2
PBP
0.34
1.4
0.17
0.5
s
2, 6
AFP
-
-
0.12
-
s
t
WHQV1
/
t
EHQV1
Word Program Time
2
-
22
150
9
130
s
2
PBP
10
100
5
90
s
2, 6
AFP
-
-
3.5
16
s
t
WHOV1
/
t
EHOV1
OTP Program Time
2
-
72
800
27
185
s
t
WHQV2
/
t
EHQV2
4K-Word Parameter Block
Erase Time
2
-
0.3
2.5
0.2
2.5
s
t
WHQV3
/
t
EHQV3
32K-Word Main Block
Erase Time
2
-
0.6
4
0.5
4
s
t
WHRH1
/
t
EHRH1
(Page Buffer) Program Suspend
Latency Time to Read
4
-
5
10
5
10
s
t
WHRH2
/
t
EHRH2
Block Erase Suspend
Latency Time to Read
4
-
5
20
5
20
s
t
ERES
Latency Time from Block Erase
Resume Command to Block
Erase Suspend Command
5
-
500
500
s
t
ARES
Latency Time for AFP Set-Up
2, 6
AFP
-
-
-
5
s
Latency for AFP Verify
Transition
2, 6
AFP
-
-
2.7
5.6
s
Latency for AFP Verify
2, 6
AFP
-
-
1.7
130
s
Rev. 0.11
sharp
Rev. 1.10
i
A-1 RECOMMENDED OPERATING CONDITIONS
A-1.1 At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
Figure A-1. AC Timing at Device Power-Up
For the AC specifications t
VR
, t
R
, t
F
in the figure, refer to the next page. See the "ELECTRICAL SPECIFICATIONS"
described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in
the next page.
t
2VPH
GND
V
CC
(min)
RST#
V
IL
V
IH
(P)
t
PHQV
V
PP
*1
GND
V
CCWH1/2
(V)
CE#
V
IL
V
IH
(E)
WE#
V
IL
V
IH
(W)
OE#
V
IL
V
IH
(G)
WP#
V
IL
V
IH
(S)
V
OH
V
OL
(D/Q)
DATA
High Z
Valid
Output
t
VR
t
F
t
ELQV
t
F
t
GLQV
(A)
ADDRESS
Valid
(RP#)
(V
CCW
)
t
R
or
t
F
Address
V
IL
V
IH
t
AVQV
t
R
or
t
F
t
R
t
R
*1 To prevent the unwanted writes, system designers should consider the design, which applies V
PP
(V
CCW
)
to 0V during read operations and V
PPH1/2
(V
CCWH1/2
) during write or erase operations.
(V
PPH1/2
)
See the application note AP-007-SW-E for details.
V
CC
V
CCQ
ADV#
V
IL
V
IH
(V)
t
F
t
VLQV
t
R
sharp
Rev. 1.10
ii
A-1.1.1 Rise and Fall Time
NOTES:
1. Sampled, not 100% tested.
2. This specification is applied for not only the device power-up but also the normal operations.
Symbol
Parameter
Notes
Min.
Max.
Unit
t
VR
V
CC
Rise Time
1
0.5
30000
s/V
t
R
Input Signal Rise Time
1, 2
1
s/V
t
F
Input Signal Fall Time
1, 2
1
s/V
sharp
Rev. 1.10
iii
A-1.2 Glitch Noises
Do not input the glitch noises which are below V
IH
(Min.) or above V
IL
(Max.) on address, data, reset, and control signals,
as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).
Figure A-2. Waveform for Glitch Noises
See the "DC CHARACTERISTICS" described in specifications for V
IH
(Min.) and V
IL
(Max.).
(a) Acceptable Glitch Noises
Input Signal
V
IH
(Min.)
Input Signal
V
IH
(Min.)
Input Signal
V
IL
(Max.)
Input Signal
V
IL
(Max.)
(b)
NOT
Acceptable Glitch Noises
sharp
Rev. 1.10
iv
A-2 RELATED DOCUMENT INFORMATION
(1)
NOTE:
1. International customers should contact their local SHARP or distribution sales office.
Document No.
Document Name
AP-001-SD-E
Flash Memory Family Software Drivers
AP-006-PT-E
Data Protection Method of SHARP Flash Memory
AP-007-SW-E
RP#, V
PP
Electric Potential Switching Circuit
sharp
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited
Warranty for SHARP's product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied.
ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND
FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible,
for any incidental or consequential economic or property damage.
NORTH AMERICA
EUROPE
JAPAN
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5700 NW Pacific Rim Blvd.
Camas, WA 98607, U.S.A.
Phone: (1) 360-834-2500
Fax: (1) 360-834-8903
Fast Info: (1) 800-833-9437
www.sharpsma.com
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Division of Sharp Electronics (Europe) GmbH
Sonninstrasse 3
20097 Hamburg, Germany
Phone: (49) 40-2376-2286
Fax: (49) 40-2376-2232
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Electronic Components & Devices
22-22 Nagaike-cho, Abeno-Ku
Osaka 545-8522, Japan
Phone: (81) 6-6621-1221
Fax: (81) 6117-725300/6117-725301
www.sharp-world.com
TAIWAN
SINGAPORE
KOREA
SHARP Electronic Components
(Taiwan) Corporation
8F-A, No. 16, Sec. 4, Nanking E. Rd.
Taipei, Taiwan, Republic of China
Phone: (886) 2-2577-7341
Fax: (886) 2-2577-7326/2-2577-7328
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438A, Alexandra Road, #05-01/02
Alexandra Technopark,
Singapore 119967
Phone: (65) 271-3566
Fax: (65) 271-3855
SHARP Electronic Components
(Korea) Corporation
RM 501 Geosung B/D, 541
Dohwa-dong, Mapo-ku
Seoul 121-701, Korea
Phone: (82) 2-711-5813 ~ 8
Fax: (82) 2-711-5819
CHINA
HONG KONG
SHARP Microelectronics of China
(Shanghai) Co., Ltd.
28 Xin Jin Qiao Road King Tower 16F
Pudong Shanghai, 201206 P.R. China
Phone: (86) 21-5854-7710/21-5834-6056
Fax: (86) 21-5854-4340/21-5834-6057
Head Office:
No. 360, Bashen Road,
Xin Development Bldg. 22
Waigaoqiao Free Trade Zone Shanghai
200131 P.R. China
Email: smc@china.global.sharp.co.jp
SHARP-ROXY (Hong Kong) Ltd.
3rd Business Division,
17/F, Admiralty Centre, Tower 1
18 Harcourt Road, Hong Kong
Phone: (852) 28229311
Fax: (852) 28660779
www.sharp.com.hk
Shenzhen Representative Office:
Room 13B1, Tower C,
Electronics Science & Technology Building
Shen Nan Zhong Road
Shenzhen, P.R. China
Phone: (86) 755-3273731
Fax: (86) 755-3273735
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