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1
DESCRIPTION
The LZ2423H is a 1/4-type (4.5 mm) solid-state
image sensor that consists of PN photo-diodes
and CCDs (charge-coupled devices). With
approximately 320 000 pixels (542 horizontal x 582
vertical), the sensor provides a stable high-resolution
color image.
FEATURES
Number of effective pixels : 512 (H) x 582 (V)
Number of optical black pixels
Horizontal : 2 front and 28 rear
Pixel pitch : 7.2 m (H) x 4.7 m (V)
Mg, G, Cy, and Ye complementary color filters
Low fixed-pattern noise and lag
No burn-in and no image distortion
Blooming suppression structure
Built-in output amplifier
Built-in overflow drain voltage circuit and reset
gate voltage circuit
Horizontal shift register clock and reset gate clock
voltage : 3.3 V (TYP.)
Variable electronic shutter (1/50 to 1/10 000 s)
Compatible with PAL standard
Package :
14-pin half-pitch WDIP [Plastic]
(WDIP014-P-0400A)
Row space : 10.16 mm
PIN CONNECTIONS
PRECAUTIONS
The exit pupil position of lens should be more
than 25 mm from the top surface of the CCD.
Refer to "PRECAUTIONS FOR CCD AREA
SENSORS" for details.
LZ2423H
1/4-type Color CCD Area Sensor
with 320 k Pixels
LZ2423H
1
OD
2
RS
3
NC
1
4
OS
5
NC
2
6
H2
7
H1
14
13
12
11
10
9
8
GND
V4
V3
V2
V1
PW
OFD
14-PIN HALF-PITCH WDIP
TOP VIEW
(WDIP014-P-0400A)
LZ2423H
2
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
(T
A
= +25 C)
SYMBOL
PIN NAME
OD
Output transistor drain
OS
Output signals
RS
Reset transistor clock
V1
,
V2
,
V3
,
V4
Vertical shift register clock
H1
,
H2
Horizontal shift register clock
PW
P-well
GND
Ground
NC
1
, NC
2
No connection
PARAMETER
SYMBOL
RATING
UNIT
Output transistor drain voltage
V
OD
0 to +18
V
Reset gate clock voltage
V
RS
Internal output
V
Vertical shift register clock voltage
V
V
10.5 to +17.5
V
Horizontal shift register clock voltage
V
H
0.3 to +12
V
Voltage difference between P-well and vertical clock
V
PW
-V
V
28 to 0
V
Storage temperature
T
STG
40 to +85
C
Ambient operating temperature
T
OPR
20 to +70
C
2
NOTE
NOTES :
1. Do not connect to DC voltage directly. When OFD is connected to GND, connect V
OD
to GND. Overflow drain clock is
applied below 26 Vp-p.
2. Do not connect to DC voltage directly. When
RS
is connected to GND, connect V
OD
to GND. Reset gate clock is
applied below 8 Vp-p.
3. When clock width is below 10 s, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be
below 27 V.
Overflow drain
OFD
1
V
Internal output
V
OFD
Overflow drain voltage
3
V
0 to +15
V
V
-V
V
Voltage difference between vertical clocks
3
LZ2423H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Ambient operating temperature
T
OPR
25.0
C
Output transistor drain voltage
V
OD
14.55
15.0
15.45
V
NOTES :
Connect NC
1
and NC
2
to GND directly or through a capacitor larger than 0.047 F.
1. Use the circuit parameter indicated in "SYSTEM CONFIGURATION EXAMPLE", and do not connect to DC voltage directly.
2. V
PW
is set below V
VL
that is low level of vertical shift register clock, or is used with the same power supply that is connected
to V
L
of V driver IC.
* To apply power, first connect GND and then turn on V
OD
. After turning on V
OD
, turn on PW first and then turn on other powers
and pulses. Do not connect the device to or disconnect it from the plug socket while power is being applied.
1
V
23.5
21.5
V
OFD
Overflow drain clock
P-well voltage
V
PW
9.0
V
VL
V
2
Ground
GND
0.0
V
V
7.5
8.0
8.5
V
V1L
, V
V2L
V
V3L
, V
V4L
Vertical shift
register clock
LOW level
INTERMEDIATE level
HIGH level
V
V1I
, V
V2I
V
V3I
, V
V4I
V
V1H
, V
V3H
14.55
0.0
15.0
15.45
V
V
LOW level
Horizontal shift
register clock
V
H1L
, V
H2L
0.05
0.0
0.05
V
HIGH level
V
H1H
, V
H2H
3.0
3.3
5.25
V
1
V
5.25
3.3
3.3
V
RS
Reset gate clock
p-p level
Reset gate clock frequency
f
RS
9.66
MHz
Horizontal shift register clock frequency
f
H1
, f
H2
9.66
MHz
Vertical shift register clock frequency
f
V1
, f
V2
f
V3
, f
V4
15.63
kHz
p-p level
LZ2423H
4
CHARACTERISTICS
(Drive method : Field accumulation)
(T
A
= +25 C, Operating conditions : The typical values specified in "RECOMMENDED OPERATING CONDITIONS".
Color temperature of light source : 3 200 K, IR cut-off filter (CM-500, 1 mmt) is used.)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Standard output voltage
V
O
150
mV
2
Photo response non-uniformity
PRNU
15
%
3
Saturation output voltage
V
SAT
650
mV
4
Dark output voltage
V
DARK
0.5
3.0
mV
1, 5
Dark signal non-uniformity
DSNU
0.5
2.0
mV
1, 6
Sensitivity
R
380
500
mV
7
Smear ratio
SMR
90
80
dB
8
Image lag
AI
1.0
%
9
Blooming suppression ratio
ABL
1 000
10
Output transistor drain current
I
OD
4.0
8.0
mA
Output impedance
R
O
350
$
Vector breakup
7.0
, %
11
Line crawling
3.0
%
12
Luminance flicker
2.0
%
13
NOTES :
Within the recommended operating conditions of V
OD
,
V
OFD
of the internal output satisfies with ABL larger than
1 000 times exposure of the standard exposure conditions,
and V
SAT
larger than 650 mV.
1. T
A
= +60 C
2. The average output voltage under uniform illumination.
The standard exposure conditions are defined as when
Vo is 150 mV.
3. The image area is divided into 10 x 10 segments under
the standard exposure conditions. Each segment's
voltage is the average output voltage of all pixels within
the segment. PRNU is defined by (Vmax Vmin)/Vo,
where Vmax and Vmin are the maximum and minimum
values of each segment's voltage respectively.
4. The image area is divided into 10 x 10 segments. Each
segment's voltage is the average output voltage of all
pixels within the segment. V
SAT
is the minimum
segment's voltage under 10 times exposure of the
standard exposure conditions.
5. The average output voltage under non-exposure
conditions.
6. The image area is divided into 10 x 10 segments under
non-exposure conditions. DSNU is defined by (Vdmax
Vdmin), where Vdmax and Vdmin are the maximum and
minimum values of each segment's voltage respectively.
7. The average output voltage when a 1 000 lux light
source with a 90% reflector is imaged by a lens of F4,
f50 mm.
8. The sensor is exposed only in the central area of V/10
square with a lens at F4, where V is the vertical image
size. SMR is defined by the ratio of the output voltage
detected during the vertical blanking period to the
maximum output voltage in the V/10 square.
9. The sensor is exposed at the exposure level
corresponding to the standard conditions. AI is defined
by the ratio of the output voltage measured at the 1st
field during the non-exposure period to the standard
output voltage.
10. The sensor is exposed only in the central area of V/10
square, where V is the vertical image size. ABL is
defined by the ratio of the exposure at the standard
conditions to the exposure at a point where blooming is
observed.
11. Observed with a vector scope when the color bar chart
is imaged under the standard exposure conditions.
12. The difference between the average output voltage of the
(Mg + Ye), (G + Cy) line and that of the (Mg + Cy), (G +
Ye) line under the standard exposure conditions.
13. The difference between the average output voltage of
the odd field and that of the even field under the
standard exposure conditions.
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