Semiconductor Group
1
The HYB 314171BJ/BJL is a 4 MBit dynamic RAM organized as 262 144 words by 16-bit. The
HYB 314171BJ/BJL utilizes CMOS silicon gate process as well as advanced circuit techniques to
provide wide operation margins, both internally and for the system user. Multiplexed address inputs
permit the HYB 314171BJ/BJL to be packed in a standard plastic 400mil wide P-SOJ-40-1 package.
This package size provides high system bit densities and is compatible with commonly used
automatic testing and insertion equipment. System oriented features include Self Refresh (L-
Version), single + 3.3 V (
0.3 V) power supply, direct interfacing with high performance logic
device families.
3.3V 256 K x 16-Bit Dynamic RAM
3.3V Low Power 256 K x 16-Bit
Dynamic RAM with Self Refresh
Preliminary Information
262 144 words by 16-bit organization
0 to 70
C operating temperature
Fast access and cycle time
RAS access time:
50 ns (-50 version)
60 ns (-60 version)
70 ns (-70 version)
CAS access time:
15ns (-50,-60 version)
20 ns (-70 version)
Cycle time:
95 ns (-50 version)
110 ns (-60 version)
130 ns (-70 version)
Fast page mode cycle time
35 ns (-50 version)
40 ns (-60 version)
45 ns (-70 version)
Single + 3.3 V (
0.3 V) supply with a built-
in VBB generator
Low Power dissipation
max. 450 mW active (-50 version)
max. 378 mW active (-60 version)
max. 306 mW active (-70 version)
Standby power dissipation
7.2 mW standby (TTL)
3.6 mW max. standby (CMOS)
0.72 mW max. standby (CMOS) for
Low Power Version
Output unlatched at cycle end allows two-
dimensional chip selection
Read, write, read-modify write, CAS-
before-RAS refresh, RAS-only refresh,
hidden-refresh and fast page mode
capability
2 CAS / 1 WE control
Self Refresh (L-Version)
All inputs and outputs TTL-compatible
512 refresh cycles / 16 ms
512 refresh cycles / 128 ms
Low Power Version only
Plastic Packages:
P-SOJ-40-1 400mil width
7.96
HYB 314171BJ-50/-60/-70
HYB 314171BJL-50/-60/-70
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
2
Ordering Information
Truth Table
Pin Names
Type
Ordering Code
Package
Description
HYB 314171BJ-50
on request
P-SOJ-40-1
3.3V 50ns 256 K x 16 DRAM
HYB 314171BJ-60
on request
P-SOJ-40-1
3.3V 60 ns 256 K x 16 DRAM
HYB 314171BJ-70
on request
P-SOJ-40-1
3.3V 70 ns 256 K x 16 DRAM
HYB 314171BJL-50
on request
P-SOJ-40-1
3.3V 50 ns 256 K x 16 DRAM
HYB 314171BJL-60
on request
P-SOJ-40-1
3.3V 60 ns 256 K x 16 DRAM
HYB 314171BJL-70
on request
P-SOJ-40-1
3.3V 70 ns 256 K x 16 DRAM
RAS
LCAS
UCAS
WE
OE
I/O1-I/O8
I/O9-I/O16
Operation
H
L
L
L
L
L
L
L
L
H
H
L
H
L
L
H
L
L
H
H
H
L
L
H
L
L
L
H
H
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
H
High-Z
High-Z
Dout
High-Z
Dout
Din
Don't care
Din
High-Z
High-Z
High-Z
High-Z
Dout
Dout
Don't care
Din
Din
High-Z
Standby
Refresh
Lower byte read
Upper byte read
Word read
Lower byte write
Upper byte write
Word write
A0-A8
Address Inputs
RAS
Row Address Strobe
UCAS, LCAS
Column Address Strobe
WE
Read/Write Input
OE
Output Enable
I/O1 I/O16
Data Input/Output
V
CC
Power Supply (+ 3.3 V)
V
SS
Ground (0 V)
N.C.
No Connection
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
3
Pin Configuration
(top view)
P-SOJ-40-1
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
4
Block Diagram
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
5
Absolute Maximum Ratings
Operating temperature range ........................................................................................ 0 to + 70
C
Storage temperature range..................................................................................... 55 to + 150
C
Input/output voltage .................................................................................... 1 to (
V
CC
+ 0.5, 4.6) V
Power supply voltage.................................................................................................. 1 to + 4.6 V
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under
"
Absolute Maximum Ratings
"
may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
T
A
= 0 to 70
C;
V
SS
= 0 V;
V
CC
= 3.3 V
0.3 V,
t
T
= 5 ns
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
Input high voltage
V
I
H
2.0
V
CC
+ 0.5
V
1
Input low voltage
V
I
L
1.0
0.8
V
1
LVTTL Output high voltage (
I
OUT
= 2.0 mA)
V
OH
2.4
V
1
LVTTL Output low voltage (
I
OUT
= 2 mA)
V
OL
0.4
V
1
LVCMOS Output high voltage (
I
OUT
= 100
A)
V
OH
2.4
V
1
LVCMOS Output low voltage (
I
OUT
= 100
A)
V
OL
0.4
V
1
Input leakage current, any input
(0 V <
V
I
N
<
V
CC
+ 0.3 V, all other inputs = 0 V)
I
I
(L)
10
10
A
1
Output leakage current
(DO is disabled, 0 V <
V
OUT
<
V
CC
+ 0.3 V )
I
O(L)
10
10
A
1
Average
V
CC
supply current:
-50 version
-60 version
-70 version
I
CC1
125
105
85
mA
2, 3, 4
Standby
V
CC
supply current
(RAS = LCAS = UCAS = WE =
V
I
H
)
I
CC2
2
mA
Average
V
CC
supply current during
RAS-only refresh cycles:
-50 version
-60 version
-70 version
I
CC3
125
105
85
mA
2, 4
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
6
DC Characteristics (cont'd)
Capacitance
T
A
= 0 to 70
C;
V
CC
= 3.3 V
0.3 V,
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
Average
V
CC
supply current during
fast page mode operation:
-50 version
-60 version
-70 version
I
CC4
70
65
60
mA
2, 3, 4
Standby
V
CC
supply current
(RAS = LCAS = UCAS = WE =
V
CC
0.2 V)
I
CC5
1
mA
1
Average
V
CC
supply current during
CAS-before-RAS refresh mode:
-50 version
-60 version
-70 version
I
CC6
125
105
85
mA
2, 4
Standby
V
CC
current (L-version)
(RAS = LCAS = UCAS = WE=
V
CC
0.2 V)
I
CC5
200
A
Self Refresh Current (L-version)
(RAS, LCAS, UCAS = 0.2 V
A0 A8 =
V
CC
0.2 V or 0.2 V)
I
CCS
250
A
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A8)
C
I
1
6
pF
Input capacitance (RAS, UCAS, LCAS, WE, OE)
C
I
2
7
pF
Output capacitance (l/O1 to l/O16)
C
I
O
7
pF
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
7
AC Characteristics
5)6)
T
A
= 0 to 70
C;
V
SS
= 0 V;
V
CC
= 3.3 V
0.3 V,
t
T
= 5 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
- 60
- 70
min.
max. min.
max. min.
max.
Common Parameters
Random read or write cycle time
t
RC
95
110
130
ns
RAS precharge time
t
RP
35
40
50
ns
RAS pulse width
t
RAS
50
10k
60
10k
70
10k
ns
CAS pulse width
t
CAS
15
10k
15
10k
20
10k
ns
Row address setup time
t
ASR
0
0
0
ns
Row address hold time
t
RAH
10
10
10
ns
Column address setup time
t
ASC
0
0
0
ns
Column address hold time
t
CAH
10
15
15
ns
RAS to CAS delay time
t
RCD
20
35
20
45
20
50
ns
RAS to column address delay
time
t
RAD
15
25
15
30
15
35
ns
RAS hold time
t
RSH
15
15
20
ns
CAS hold time
t
CSH
50
60
70
ns
CAS to RAS precharge time
t
CRP
5
5
5
ns
Transition time (rise and fall)
t
T
3
50
3
50
3
50
ns
7
Refresh period
t
REF
16
16
16
ms
Refresh period (L-version)
t
REF
128
128
128
ms
Read Cycle
Access time from RAS
t
RAC
50
60
70
ns
8, 9
Access time from CAS
t
CAC
15
15
20
ns
8, 9
Access time from column address
t
AA
25
30
35
ns
8,10
OE access time
t
OEA
15
15
20
ns
Column address to RAS lead time
t
RAL
25
30
35
ns
Read command setup time
t
RCS
0
0
0
ns
Read command hold time
t
RCH
0
0
0
ns
11
Read command hold time ref. to
RAS
t
RRH
0
0
0
ns
11
CAS to output inlow-Z
t
CLZ
0
0
0
ns
8
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
8
Output buffer turn-off delay from
CAS
t
OFF
0
15
0
20
0
20
ns
12
Output buffer turn-off delay from
OE
t
OEZ
0
15
0
20
0
20
ns
12
Data to OE low delay
t
DZO
0
0
0
ns
13
CAS high to datadelay
t
CDD
15
20
20
ns
14
OE high to data delay
t
ODD
15
-
20
20
ns
14
Write Cycle
Write command hold time
t
WCH
10
10
15
ns
Write command pulse width
t
WP
10
10
15
ns
Write command setup time
t
WCS
0
0
0
ns
15
Write command to RAS lead time
t
RWL
15
15
20
ns
Write command to CAS lead time
t
CWL
15
15
20
ns
Data setup time
t
DS
0
0
0
ns
16
Data hold time
t
DH
10
15
15
ns
16
Data to CAS lowdelay
t
DZC
0
0
0
ns
13
Read-modify-Write Cycle
Read-write cycle time
t
RWC
140
160
185
ns
RAS to WE delay time
t
RWD
75
90
100
ns
15
CAS to WE delay time
t
CWD
40
45
50
ns
15
Column address to WE delay
time
t
AWD
50
60
65
ns
15
OE command hold time
t
OEH
15
20
20
ns
Fast Page Mode Cycle
Fast page mode cycle time
t
PC
35
40
45
ns
CAS precharge time
t
CP
10
10
10
ns
Access time from CAS precharge
t
CPA
30
35
40
ns
7
RAS pulse width
t
RASP
50
200k
60
200k
70
200k
ns
RAS hold time from CAS
precharge
t
RHCP
30
35
40
ns
Parameter
Symbol
Limit Values
Unit
Note
-50
- 60
- 70
min.
max. min.
max. min.
max.
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
9
Fast Page Mode Read Modify Write Cycle
Fast page mode read/write cycle
time
t
PRWC
80
90
100
ns
CAS precharge to WE delay time
t
CPWD
55
60
65
ns
CAS before RAS refresh Cycle
CAS setup time
t
CSR
5
5
5
ns
CAS hold tim
t
CHR
10
10
10
ns
RAS to CAS precharge time
t
RPC
0
0
0
ns
Write to RAS precharge time
t
WRP
10
10
10
ns
Write to RAS hold time
t
WRH
10
10
10
ns
CAS-before RAS counter test cycle
CAS precharge time
t
CPT
25
30
40
ns
Self Refresh Cycle (L-Version only)
RAS pulse width
t
RASS
100
100
100
s
RAS precharge time
t
RPS
95
110
130
ns
CAS hold time Self Refresh
t
CHS
35
40
50
ns
Parameter
Symbol
Limit Values
Unit
Note
-50
- 60
- 70
min.
max. min.
max. min.
max.
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
10
Notes:
1) All voltages are referenced to
V
SS
.
2)
I
CC1
,
I
CC3
,
I
CC4
and
I
CC6
depend on cycle rate.
3)
I
CC1
and
I
CC4
depend on output loading. Specified values are obtained with the output open.
4) Address can be changed once or less while RAS =
V
il
. In case of
I
CC4
it can be changed once or less during
a page mode cycle
5) An initial pause of 200
s is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume
t
T
= 5 ns.
7)
V
I
H
(min.)
and
V
I
L (max.)
are reference levels for measuring timing of input signals. Transition times are also
measured between
V
I
H
and
V
I
L
.
8) Measured with a load equivalent to 100 pF and at Voh=2.0V (Ioh=-2mA), Vol=0.8V (Iol=2mA).
9) Operation within the
t
RCD (max.)
limit ensures that
t
RAC (max.)
can be met.
t
RCD (max.)
is specified as a reference point
only. If
t
RCD
is greater than the specified
t
RCD (max.)
limit, then access time is controlled by
t
CAC
.
10) Operation within the
t
RAD (max.
)
limit ensures that
t
RAC (max.)
can be met.
t
RAD (max.)
is specified as a reference point
only. If
t
RAD
is greater than the specified
t
RAD (max.)
limit, then access time is controlled by
t
AA
.
11) Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
12)
t
OFF (max.)
,
t
OEZ (max.)
define the time at which the output achieves the open-circuit conditions and are not
referenced to output voltage levels.
13) Either
t
DZC
or
t
DZO
must be satisfied.
43) Either
t
CDD
or
t
ODD
must be satisfied.
15)
t
WCS
,
t
RWD
,
t
CWD
and
t
AWD
are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If
t
WCS
>
t
WCS (min.)
, the cycle is an early write cycle and data out pin will remain
open-circuit (high impedance) through the entire cycle; if
t
RWD
>
t
RWD (min.)
,
t
CWD
>
t
CWD (min.)
and
t
AWD
>
t
AWD (min.)
,
the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above
sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.
16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-write cycles.
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
11
Read Cycle
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
12
Write Cycle (Early Write)
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
13
Write Cycle (OE Controlled Write)
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
14
Read-Write (Read-Modify-Write) Cycle
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
15
Fast Page Mode Read Cycle
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
16
Fast Page Mode Early Write Cycle
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
17
Fast Page Mode Read-Modify-Write Cycle
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
18
RAS-Only Refresh Cycle
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
19
CAS-Before-RAS Refresh Cycle
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
20
CAS before RAS Self Refresh Cycle
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
21
Hidden Refresh Cycle (Read)
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
22
Hidden Refresh Cycle (Early Write)
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
23
CAS/-Before-RAS Refresh Counter Test Cycle
HYB 314171BJ/BJL-50/-60/-70
3.3V 256 K x 16-DRAM
Semiconductor Group
24
Package Outline
Plastic Package, P-SOJ- 40-1 (SMD)
(Plastic Small Outline J-leaded Package)
GPJ09018
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book "Package Information".
Dimensions in mm
SMD = Surface Mounted Device
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