Semiconductor Group
1
The HYB 5(3)14265BJ(L) is the new generation dynamic RAM organized as 262 144 words by
16-bit. The HYB 5(3)14265BJ(L) utilizes the SIEMENS 16M-CMOS submicron silicon gate process
as well as advanced circuit techniques to provide wide operation margins, both internally and for the
system user. Multiplexed address inputs permit the HYB 5(3)14265BJ(L) to be packed in a
standard plastic 400mil wide P-SOJ-40-3 package. This package size provides high system bit
densities and is compatible with commonly used automatic testing and insertion equipment.
The HYB314265BJL parts have a very low power "sleep mode" supported by Self Refresh.
256K x 16-Bit EDO-Dynamic RAM
Preliminary Information
262 144 words by 16-bit organization
0 to 70
C operating temperature
EDO - Hyper Page Mode
Performance:
Low Power dissipation
- Active(max.):
120mA / 120mA / 105mA / 95 mA
- Standby : TTL Inputs (max.) 2.0 mA
- Standby: CMOS Inputs (max.) 1.0 mA
- Standby (L-version) 200
A
-400
-40
-45
-50
t
rc
69
69
79
89
ns
t
rac
40
40
45
50
ns
t
cac
10
10
12
13
ns
t
aa
20
20
22
25
ns
t
hpc
12,5
15
18
20
ns
t
hpc
80
66
55
50
MHz
Power Supply:
Read, write, read-modify-write, CAS -before
RAS refresh, RAS only refresh, hidden refresh
mode
Low Power Version (L) with Self Refresh
and 250
A self refresh current
2 CAS / 1 WE control
All inputs and outputs TTL-compatible
512 refresh cycles / 16 ms
512 refresh cycles / 128 ms (L-version)
Plastic Packages: P-SOJ-40-3 400 mil width
HYB 514265BJ-400
+5 V
5%
HYB 514265BJ-40
+5 V
10%
HYB 514265BJ-45
+5 V
10%
HYB 514265BJ-50
+5 V
10%
HYB 314265BJ(L)-45 +3.3 V
0.3 V
HYB 314265BJ(L)-50 +3.3 V
0.3 V
6.96
HYB 514265BJ-400/40/-45/-50
HYB 314265BJ(L)-45/-50
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
2
Ordering Information
Truth Table
Pin Names
Type
Ordering
Code
Package
Description
5 V versions:
HYB 514265BJ-400
Q67100-3033
P-SOJ-40-3
5 V 40 ns 256 K x 16 EDO-DRAM
HYB 514265BJ-40
Q67100-3039
P-SOJ-40-3
5 V 40 ns 256 K x 16 EDO-DRAM
HYB 514265BJ-45
Q67100-3035
P-SOJ-40-3
5 V 45 ns 256 K x 16 EDO-DRAM
HYB 514265BJ-50
Q67100-3036
P-SOJ-40-3
5 V 50 ns 256 K x 16 EDO-DRAM
3.3 V versions:
HYB 314265BJ-45
on request
P-SOJ-40-3
3.3 V 45 ns 256 K x 16 EDO- DRAM
HYB 314265BJ-50
on request
P-SOJ-40-3
3.3 V 50 ns 256 K x 16 EDO- DRAM
HYB 314265BJL-45
on request
P-SOJ-40-3
3.3 V Low Power 45 ns 256 K x 16 EDO- DRAM
HYB 314265BJL-50
on request
P-SOJ-40-3
3.3 V Low Power 50 ns 256 K x 16 EDO-DRAM
RAS
LCAS
UCAS
WE
OE
I/O1-I/O8
I/O9-I/O16
Operation
H
L
L
L
L
L
L
L
L
H
H
L
H
L
L
H
L
L
H
H
H
L
L
H
L
L
L
H
H
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
H
High-Z
High-Z
Dout
High-Z
Dout
Din
Don't care
Din
High-Z
High-Z
High-Z
High-Z
Dout
Dout
Don't care
Din
Din
High-Z
Standby
Refresh
Lower byte read
Upper byte read
Word read
Lower byte write
Upper byte write
Word write
A0-A8
Address Inputs
RAS
Row Address Strobe
UCAS, LCAS
Column Address Strobe
WE
Read/Write Input
OE
Output Enable
I/O1 I/O16
Data Input/Output
V
CC
Power Supply:
+ 5 V for HYB 514265,
+ 3.3 V for HYB 314265
V
SS
Ground (0 V)
N.C.
No Connection
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
3
Pin Configuration
(top view)
P-SOJ-40-3
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
4
Block Diagram
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
5
Absolute Maximum Ratings
Operating temperature range ........................................................................................ 0 to + 70
C
Storage temperature range..................................................................................... 55 to + 150
C
Input/output voltage for HYB 514265................................................ 0.5 to min. (
V
CC
+ 0.5, 7.0) V
Power supply voltage for HYB 514265 ........................................................................... 1 to + 7 V
Input/output voltage for HYB 314265................................................ 0.5 to min. (
V
CC
+ 0.5, 4.6) V
Power supply voltage for HYB 314265 ..................................................................... 0.5 to + 4.6 V
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under
"
Absolute Maximum Ratings
"
may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics for HYB514265
T
A
= 0 to 70
C;
V
SS
= 0 V;
V
CC
= 5 V
10 % (
5 % for -400 version) ,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
Input high voltage
V
I
H
2.4
V
CC
+ 0.5
V
1
Input low voltage
V
I
L
0.5
0.8
V
1
Output high voltage (
I
OUT
= 5.0 mA)
V
OH
2.4
V
1
Output low voltage (
I
OUT
= 4.2 mA)
V
OL
0.4
V
1
Input leakage current, any input
(0 V <
V
I
N
< 7 V, all other inputs = 0 V)
I
I
(L)
10
10
A
1
Output leakage current
(DO is disabled, 0 V <
V
OUT
<
V
CC
)
I
O(L)
10
10
A
1
Average
V
CC
supply current:
-400 version
-40 version
-45 version
-50 version
I
CC1
120
120
105
95
mA
2, 3, 4
Standby
V
CC
supply current
(RAS = LCAS = UCAS = WE =
V
IH
)
I
CC2
2
mA
Average
V
CC
supply current during RAS-only
refresh cycles:
-400 version
-40 version
-45 version
-50 version
I
CC3
120
120
105
95
mA
2, 4
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
6
DC Characteristics for 314265
T
A
= 0 to 70
C;
V
SS
= 0 V;
V
CC
= 3.3 V
0.3 V,
t
T
= 2 ns
Average
V
CC
supply current during
hyper page mode (EDO) operation: -400 version
-40 version
-45 version
-50 version
I
CC4
110
90
75
65
mA
2, 3, 4
Standby
V
CC
supply current
(RAS = LCAS = UCAS = WE =
V
CC
0.2 V)
I
CC5
1
mA
1
Standby
V
CC
supply current (L-version only)
(RAS = LCAS = UCAS = WE =
V
CC
0.2 V)
I
CC5
200
A
1
Average
V
CC
supply current during
CAS-before-RAS refresh mode:
-400 version
-40 version
-45 version
-50 version
I
CC6
120
120
105
95
mA
2, 4
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Input high voltage
V
I
H
2.0
V
CC
+ 0.5 V
1
Input low voltage
V
I
L
0.5
0.8
V
1
TTL Output high voltage (
I
OUT
= 2.0 mA)
V
OH
2.4
V
1
TTL Output low voltage (
I
OUT
= 2 mA)
V
OL
0.4
V
1
CMOS Output high voltage (
I
OUT
= 100
A)
V
OH
2.4
V
1
CMOS Output low voltage (
I
OUT
= 100
A)
V
OL
0.4
V
1
Input leakage current, any input
(0 V <
V
IN
<
V
CC
+ 0.3 V, all other inputs = 0 V)
I
I
(L)
10
10
A
1
Output leakage current
(DO is disabled, 0 V <
V
OUT
<
V
CC
+ 0.3 V)
I
O(L)
10
10
A
1
Average
V
CC
supply current:
-45 version
-50 version
I
CC1
105
95
mA
2, 3, 4
Standby
V
CC
supply current
(RAS = LCAS = UCAS = WE =
V
IH
)
I
CC2
2
mA
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
7
Capacitance
T
A
= 0 to 70
C;
f
= 1 MHz
Average
V
CC
supply current during
RAS-only refresh cycles:
-45 version
-50 version
I
CC3
105
95
mA
2, 4
Average
V
CC
supply current during hyper page
mode (EDO) operation:
-45 version
-50 version
I
CC4
75
65
mA
2, 3, 4
Standby
V
CC
supply current
(RAS = LCAS = UCAS = WE =
V
CC
0.2 V)
I
CC5
1
mA
1
Standby
V
CC
supply current (L-version only)
(RAS = LCAS = UCAS = WE =
V
CC
0.2 V)
I
CC5
200
A
1
Average
V
CC
supply current during CAS-
before-RAS refresh mode:
-45 version
-50 version
I
CC6
105
95
mA
2, 4
Self Refresh Current (L-version only)
CBR cycle with RAS >trasss(min), CAS held low;
WE =
V
CC
0.2 V,
Addresses and Din =
V
CC
0.2 V or 0.2 V
I
CC7
250
A
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A8)
C
I
1
5
pF
Input capacitance (RAS, UCAS, LCAS, WE, OE)
C
I
2
7
pF
Output capacitance (l/O1 to l/O16)
C
I
O
7
pF
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
8
AC Characteristics
5) 6)
T
A
= 0 to 70
C,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit Note
-400
-40
min.
max.
min.
max.
Common Parameters
Random read or write cycle time
t
RC
69
69
ns
RAS precharge time
t
RP
25
25
ns
RAS pulse width
t
RAS
40
10k
40
10k
ns
CAS pulse width
t
CAS
4.5
10k
6
10k
ns
CAS precharge time
t
CP
4
5
ns
Row address setup time
t
ASR
0
0
ns
Row address hold time
t
RAH
5
5
ns
Column address setup time
t
ASC
0
0
ns
Column address hold time
t
CAH
5
5
ns
RAS to CAS delaytime
t
RCD
9
30
9
30
ns
RAS to column address delay time
t
RAD
7
20
7
20
ns
RAS hold time
t
RSH
6
6
ns
CAS hold time
t
CSH
32
32
ns
CAS to RAS precharge time
t
CRP
5
5
ns
Transition time(rise and fall)
t
T
1
50
1
50
ns
7
Refresh period
t
REF
16
16
ms
Read Cycle
Access time from RAS
t
RAC
40
40
ns
8, 9
Access time from CAS
t
CAC
10
10
ns
8, 9
Access time from column address
t
AA
17
20
ns
8,10
OE access time
t
OEA
10
10
ns
Column address to RAS lead time
t
RAL
20
20
ns
Read command setup time
t
RCS
0
0
ns
Read command hold time
t
RCH
0
0
ns
11
Read command hold time ref. to RAS
t
RRH
0
0
ns
11
CAS to output inlow-Z
t
CLZ
0
0
ns
8
Output buffer turn-off delay from CAS
t
OFF
0
0
10
ns
12
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
9
Output buffer turn-off delay from OE
t
OEZ
0
10
0
10
ns
12
Data to OE low delay
t
DZO
0
0
ns
13
CAS high to data delay
t
CDD
8
8
ns
14
OE high to data delay
t
ODD
8
8
ns
14
Data to CAS low delay
t
DZC
0
0
ns
13
Write Cycle
Write command hold time
t
WCH
5
5
ns
Write command pulse width
t
WP
5
5
ns
Write command setup time
t
WCS
0
0
ns
15
Write command to RAS lead time
t
RWL
10
10
ns
Write command to CAS lead time
t
CWL
10
10
ns
Data setup time
t
DS
0
0
ns
16
Data hold time
t
DH
5
5
ns
16
Data to CAS low delay
t
DZC
0
0
ns
13
Read-modify-Write Cycle
Read-write cycle time
t
RWC
93
93
ns
RAS to WE delay time
t
RWD
52
52
ns
15
CAS to WE delay time
t
CWD
22
22
ns
15
Column address to WE delay time
t
AWD
32
32
ns
15
OE command hold time
t
OEH
5
5
ns
Hyper Page Mode (EDO) Cycle
Hyper page mode cycle time
t
HPC
12.5
15
ns
Access time from CAS precharge
t
CPA
17
21
ns
7
Output data hold time
t
COH
3
3
ns
RAS pulse width in hyper page mode
t
RAS
40
200k
40
200k
ns
RAS hold time from CAS precharge
t
RHCP
17
21
ns
Parameter
Symbol
Limit Values
Unit Note
-400
-40
min.
max.
min.
max.
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
10
Hyper Page Mode (EDO) Read-Modify-Write Cycle
Hyper page mode read/write cycle time
t
PRWC
55
55
ns
CAS precharge to WE delay time
t
CPWD
35
35
ns
CAS before RAS Refresh Cycle
CAS setup time
t
CSR
5
5
ns
CAS hold time
t
CHR
5
5
ns
RAS to CAS precharge time
t
RPC
5
5
ns
Write to RAS precharge time
t
WRP
10
10
ns
Write to RAS hold time
t
WRH
10
10
ns
CAS-before-RAS Counter Test Cycle
CAS precharge time
t
CPT
25
25
ns
Parameter
Symbol
Limit Values
Unit Note
-400
-40
min.
max.
min.
max.
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
11
AC Characteristics
5)6)
16E
T
A
= 0 to 70 C,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit Note
-45
-50
min.
max.
min.
max.
Common Parameters
Random read or write cycle time
t
RC
79
89
ns
RAS precharge time
t
RP
30
35
ns
RAS pulse width
t
RAS
45
10k
50
10k
ns
CAS pulse width
t
CAS
7
10k
8
10k
ns
CAS precharge time
t
CP
7
8
ns
Row address setup time
t
ASR
0
0
ns
Row address hold time
t
RAH
7
8
ns
Column address setup time
t
ASC
0
0
ns
Column address hold time
t
CAH
7
8
ns
RAS to CAS delay time
t
RCD
11
33
12
37
ns
RAS to column address delay
t
RAD
9
23
10
25
ns
RAS hold time
t
RSH
12
13
ns
CAS hold time
t
CSH
36
40
ns
CAS to RAS precharge time
t
CRP
5
5
ns
Transition time (rise and fall)
t
T
1
50
1
50
ns
7
Refresh period
t
REF
16
16
ms
Refresh period (L-version only)
t
REF
128
128
ms
Read Cycle
Access time from RAS
t
RAC
45
50
ns
8, 9
Access time from CAS
t
CAC
12
13
ns
8, 9
Access time from column address
t
AA
22
25
ns
8,10
OE access time
t
OEA
12
13
ns
Column address to RAS lead time
t
RAL
23
25
ns
Read command setup time
t
RCS
0
0
ns
Read command hold time
t
RCH
0
0
ns
11
Read command hold time referenced to RAS
t
RRH
0
0
ns
11
CAS to output in low-Z
t
CLZ
0
0
ns
8
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
12
Output buffer turn-off delay
t
OFF
0
12
0
13
ns
12
Output turn-off delay from OE
t
OEZ
0
12
0
13
ns
12
Data to CAS low delay
t
DZC
0
0
ns
13
Data to OE low delay
t
DZO
0
0
ns
13
CAS high to data delay
t
CDD
10
10
ns
14
OE high to data delay
t
ODD
10
10
ns
14
Write Cycle
Write command hold time
t
WCH
7
8
ns
Write command pulse width
t
WP
7
8
ns
Write command setup time
t
WCS
0
0
ns
15
Write command to RAS lead time
t
RWL
12
13
ns
Write command to CAS lead time
t
CWL
12
13
ns
Data setup time
t
DS
0
0
ns
16
Data hold time
t
DH
7
8
ns
16
Read-modify-Write Cycle
Read-write cycle time
t
RWC
107
118
ns
RAS to WE delay time
t
RWD
59
64
ns
15
CAS to WE delay time
t
CWD
26
27
ns
15
Column address to WE delay time
t
AWD
36
39
ns
15
OE command hold time
t
OEH
7
10
ns
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time
t
HPC
18
20
ns
Access time from CAS precharge
t
CPA
25
27
ns
7
Output data hold time
t
COH
5
5
ns
RAS pulse width in EDO mode
t
RAS
45
200k
50
200k
ns
CAS precharge to RAS Delay
t
RHPC
25
27
ns
AC Characteristics (cont'd)
5)6)
16E
T
A
= 0 to 70 C,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit Note
-45
-50
min.
max.
min.
max.
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
13
Notes:
1) All voltages are referenced to
V
SS
.
2)
I
CC1
,
I
CC3
,
I
CC4
and
I
CC6
depend on cycle rate.
3)
I
CC1
and
I
CC4
depend on output loading. Specified values are obtained with the output open.
4) Address can be changed once or less while RAS =
V
IL
. In case of
I
CC4
it can be changed once or less during
a hyper page mode (EDO) cycle
5) An initial pause of 200
s is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume
t
T
= 2 ns.
Hyper Page Mode (EDO) Read-modify-Write Cycle
Hyper page mode (EDO) read-write cycle time
t
PRWC
51
58
ns
CAS precharge to WE
t
CPWD
41
41
ns
CAS-before-RAS Refresh Cycle
CAS setup time
t
CSR
5
10
ns
CAS hold time
t
CHR
10
10
ns
RAS to CAS precharge time
t
RPC
5
5
ns
Write to RAS precharge time
t
WRP
10
10
ns
Write hold time referenced to RAS
t
WRH
10
10
ns
CAS-before-RAS Counter Test Cycle
CAS precharge time
t
CPT
30
35
ns
Self Refresh Cycle (L-version)
RAS pulse width
t
RASS
100k
100k
ns
17
RAS precharge
t
RPS
110
95
ns
17
CAS hold time
t
CHS
50
50
ns
17
AC Characteristics (cont'd)
5)6)
16E
T
A
= 0 to 70 C,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit Note
-45
-50
min.
max.
min.
max.
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
14
7)
V
I
H
(min.)
and
V
I
L (max.)
are reference levels for measuring timing of input signals. Transition times are also
measured between
V
I
H
and
V
I
L
.
8) Measured with the specified current load and 50 pF at
V
OL
= 0.8 V and
V
OH
= 2.0 V. Access time is determined
by the latter of
t
RAC
,
t
CAC
,
t
AA
,
t
CPA
,
t
OEA
.
t
CAC
is measured from tristate
.
9) Operation within the
t
RCD (max.)
limit ensures that
t
RAC (max.)
can be met.
t
RCD (max.)
is specified as a reference point
only. If
t
RCD
is greater than the specified
t
RCD (max.)
limit, then access time is controlled by
t
CAC
.
10) Operation within the
t
RAD (max.
)
limit ensures that
t
RAC (max.)
can be met.
t
RAD (max.)
is specified as a reference point
only. If
t
RAD
is greater than the specified
t
RAD (max.)
limit, then access time is controlled by
t
AA
.
11) Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
12)
t
OFF (max.)
,
t
OEZ (max.)
define the time at which the output achieves the open-circuit conditions and are not
referenced to output voltage levels.
t
OFF
is referenced from the rising edge of RAS or CAS, whichever occurs
last.
13) Either
t
DZC
or
t
DZO
must be satisfied.
14) Either
t
CDD
or
t
ODD
must be satisfied.
15)
t
WCS
,
t
RWD
,
t
CWD
and
t
AWD
are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If
t
WCS
>
t
WCS (min.)
, the cycle is an early write cycle and data out pin will remain
open-circuit (high impedance) through the entire cycle; if
t
RWD
>
t
RWD (min.)
,
t
CWD
>
t
CWD (min.)
and
t
AWD
>
t
AWD (min.)
,
the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above
sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.
16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-write cycles.
17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR
refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the
refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately
after exit from Self Refresh.
50 pF
I/O
Z=50 Ohm
+ 1.5 V
50 Ohm
fig.2
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
15
Read Cycle
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
16
Write Cycle (Early Write)
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
17
Write Cycle (OE Controlled Write)
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
18
Read-Write (Read-Modify-Write) Cycle
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
19
Hyper Page Mode (EDO) Read Cycle
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
20
Hyper Page Mode (EDO) Early Write Cycle
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
21
Hyper Page Mode (EDO) Late Write and Read-Modify-Write Cycles
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
22
RAS-Only Refresh Cycle
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
23
CAS-Before-RAS Refresh Cycle
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
24
CAS before RAS Self Refresh Cycle
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
25
Hidden Refresh Cycle (Read)
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
26
Hidden Refresh Cycle (Early Write)
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
27
CAS-Before-RAS Refresh Counter Test Cycle
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
28
Package Outlines
P-SOJ-40-3
(Small Outline J-Leaded Package)
GPJ09018
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book "Package Information".
Dimensions in mm
SMD = Surface Mounted Device
PDF 
ZIP