Semiconductor Group 1 6.97

8 388 608 words by 8-bit organization

0 to 70 °C operating temperature

Fast Page Mode operation

Performance:

Single + 3.3 V (

0.3V) power supply

Low power dissipation:
max. 396 mW active ( HYB 3164800AJ/AT(L) -40)
max. 324 mW active ( HYB 3164800AJ/AT(L) -50)
max. 270 mW active ( HYB 3164800AJ/AT(L) -60)
max. 558 mW active ( HYB 3165800AJ/AT(L) -40)
max. 468 mW active ( HYB 3165800AJ/AT(L) -50)
max. 378 mW active ( HYB 3165800AJ/AT(L) -60)
7.2 mW standby (LVTTL)
3.24 mW standby (LVCMOS)
720

W standby for L-versions

Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh and self refresh (L-version only)

8192 refresh cycles/128 ms , 13 R/ 10C addresses (HYB 3164800AJ/AT)
4096 refresh cycles/ 64 ms , 12 R/ 11C addresses (HYB 3165800AJ/AT)

256 msec refresh period for L-versions

Plastic Package: P-SOJ-32-1 400 mil HYB 3164(5)800AJ
P-TSOPII-32-1 400 mil HYB 3164(5)800AT(L)

-40

-50

-60

RAC

RAS access time

CAC

CAS access time

Access time from address

Read/write cycle time

110

Fast page mode cycle time

8M x 8-Bit Dynamic RAM

Advanced Information

HYB 3164800AJ/AT(L) -40/-50/-60
HYB 3165800AJ/AT(L) -40/-50/-60

( 4k & 8k Refresh)

Semiconductor Group

HYB3164(5)800AJ/AT(L)-40/-50/-60

8M x 8-DRAM

This device is a 64 MBit dynamic RAM organized 8 388 608 by 8 bits. The device is fabricated in an
advanced second generation 64Mbit 0,35

m CMOS silicon gate process technology. The circuit

and process design allow this device to achieve high performance and low power dissipation. This
DRAM operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or
LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)800AJ/AT to be packaged in a
400mil wide SOJ-32 or TSOP-32 plastic package. These packages provide high system bit
densities and are compatible with commonly used automatic testing and insertion equipment. The
HYB3164(5)800ATL parts (L-versions) have a very low power ,,sleep mode" supported by Self
Refresh

Ordering Information

Pin Names

Type

Ordering
Code

Package

Descriptions

HYB 3164800AJ-40

P-SOJ-32-1 400 mil

DRAM (access time 40 ns)

HYB 3164800AJ-50

P-SOJ-32-1 400 mil

DRAM (access time 50 ns)

HYB 3164800AJ-60

P-SOJ-32-1 400 mil

DRAM (access time 60 ns)

HYB 3164800AT-40

P-TSOPII-32-1 400 mil

DRAM (access time 40 ns)

HYB 3164800AT-50

P-TSOPII-32-1 400 mil

DRAM (access time 50 ns)

HYB 3164800AT-60

P-TSOPII-32-1 400 mil

DRAM (access time 60 ns)

HYB 3165800AJ-40

P-SOJ-32-1 400 mil

DRAM (access time 40 ns)

HYB 3165800AJ-50

P-SOJ-32-1 400 mil

DRAM (access time 50 ns)

HYB 3165800AJ-60

P-SOJ-32-1 400 mil

DRAM (access time 60 ns)

HYB 3165800AT-40

P-TSOPII-32-1 400 mil

DRAM (access time 40 ns)

HYB 3165800AT-50

P-TSOPII-32-1 400 mil

DRAM (access time 50 ns)

HYB 3165800AT-60

P-TSOPII-32-1 400 mil

DRAM (access time 60 ns)

HYB 3164(5)800ATL

P-TSOPII-32-1 400 mil

Low Power DRAMs

A0-A12

Address Inputs for 8k-refresh versions HYB 3164800AJ/AT(L)

A0-A11

Address Inputs for 4k-refresh versions HYB 3165800AJ/AT(L)

RAS

Row Address Strobe

Output Enable

I/O1-I/O8

Data Input/Output

CAS

Column Address Strobe

Read/Write Input

Vcc

Power Supply ( + 3.3V)

Vss

Ground

Semiconductor Group

HYB3164(5)800AJ/AT(L)-40/-50/-60

8M x 8-DRAM

TRUTH TABLE

FUNCTION

RAS

CAS

ROW

ADDR

COL

ADDR

I/O1-

I/O8

Standby

H - X

High Impedance

Read

ROW

COL

Data Out

Early-Write

ROW

COL

Data In

Delayed-Write

H - L

ROW

COL

Data In

Read-Modify-Write

H - L

L - H

ROW

COL

Data Out, Data In

Fast Page Mode Read

1st Cycle

H - L

ROW

COL

Data Out

2nd Cycle

H - L

n/a

COL

Data Out

Fast Page Mode Early
Write

1st Cycle

H - L

ROW

COL

Data In

2nd Cycle

H - L

n/a

COL

Data In

Fast Page Mode RMW

1st Cycle

H - L

L - H

ROW

COL

Data Out, Data In

2st Cycle

H - L

L - H

n/a

COL

Data Out, Data In

RAS only refresh

ROW

n/a

High Impedance

CAS-before-RAS refresh

H - L

n/a

High Impedance

Test Mode Entry

H - L

n/a

High Impedance

Hidden Refresh

READ

L-H-L

ROW

COL

Data Out

WRITE

L-H-L

ROW

COL

Data In

Semiconductor Group

HYB3164(5)800AJ/AT(L)-40/-50/-60

8M x 8-DRAM

Absolute Maximum Ratings

Operating temperature range..............................................................................................0 to 70 °C

Storage temperature range......................................................................................... 55 to 150 °C

Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V

Power supply voltage....................................................................................................-0.5V to 4.6 V

Power dissipation......................................................................................................................1.0 W

Data out current (short circuit)..................................................................................................50 mA

Note

Stresses above those listed under ,,Absolute Maximum Ratings" may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may effect device
reliability.

DC Characteristics

= 0 to 70 °C,

= 0 V,

= 3.3 V

0.3 V

Parameter

Symbol

Limit Values

Unit Note

min.

max.

Input high voltage

2.0

Vcc+0.3

Input low voltage

0.3

0.8

Output high voltage (LVTTL)
Output ,,H" level voltage (Iout = -2mA)

2.4

Output low voltage (LVTTL)
Output ,,L"level voltage (Iout = +2mA)

0.4

Output high voltage (LVCMOS)
Output ,,H" level voltage (Iout = -100uA)

Vcc-0.2 -

Ouput low voltage (LVCMOS)
Output ,,L" level voltage (Iout = +100uA)

0.2

Input leakage current,any input

(0 V < Vin < Vcc , all other pins = 0 V

I(L)

Output leakage current

(DO is disabled, 0 V < Vout < Vcc )

O(L)

Semiconductor Group

HYB3164(5)800AJ/AT(L)-40/-50/-60

8M x 8-DRAM

DC-Characteristics (cont'd)

= 0 to 70 °C,

= 0 V,

= 3.3 V

0.3 V

Parameter

Symbol refresh version Unit Note

4k 8k

Operating Current
-40 ns version
-50 ns version
-60 ns version

(RAS, CAS, address cycling: tRC = tRC min.)

CC1

155
130
105

110
90
75

mA
mA
mA

2) 3) 4)

Standby Current

(RAS=CAS= Vih)

CC2

RAS Only Refresh Current:

- -40 ns version
-50ns version
-60 ns version

(RAS cycling: CAS = VIH: tRC = tRC min.)

CC3

155
130
105

110
90
75

mA
mA
mA

2) 4)

Fast Page Mode Current:

-40 ns version
-50 ns version
-60 ns version

(RAS =

, CAS, address cycling: tPC=tPC min.)

CC4

70
60
50

mA
mA
mA

2) 3) 4)

Standby Current

(RAS=CAS= Vcc-0.2V)

CC5

900

Standby Current (L-Version)

(RAS=CAS= Vcc-0.2V)

CC5

200

CAS Before RAS Refresh Current

-40 ns version

-50 ns version
-60 ns version

(RAS, CAS cycling: tRC = tRC min.)

CC6

155
130
105

mA
mA
mA

2) 4)

Self Refresh Current (L-version only)

(CBR cycle with tRAS>TRASSmin, CAS held low,
WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)

CC7

400

Semiconductor Group

HYB3164(5)800AJ/AT(L)-40/-50/-60

8M x 8-DRAM

AC Characteristics (note: 6,7,8)

AC64-2F

= 0 to 70 °C,

= 3.3

0.3V

Parameter

Symbol

-40

-50

-60

Unit Note

min.

max. min.

max.

Common Parameters

Random read or write cycle time

110

RAS pulse width

RAS

100k

CAS pulse width

CAS

100k

RAS precharge time

CAS precharge time

Row address setup time

ASR

Row address hold time

RAH

Column address setup time

ASC

Column address hold time

CAH

RAS to CAS delay time

RCD

RAS to column address delay

RAD

RAS hold time

RSH

CAS hold time

CSH

CAS to RAS precharge time

CRP

Transition time (rise and fall)

Refresh period for 8k-refresh

REF

128

Refresh period for 4k-refresh

REF

Refresh period for L-versions

REF

256

Read Cycle

Access time from RAS

RAC

8, 9

Access time from CAS

CAC

8, 9

Access time from column address

8, 10

OE access time

OEA

Column address to RAS lead time

RAL

Read command setup time

RCS

Read command hold time

RCH

Read command hold time
referenced to RAS

RRH

CAS to output in low-Z

CLZ

Semiconductor Group

HYB3164(5)800AJ/AT(L)-40/-50/-60

8M x 8-DRAM

Output buffer turn-off delay

OFF

Output buffer turn-off delay from
OE

OEZ

Data to OE low delay

DZO

CAS high to data delay

CDD

OE high to data delay

ODD

Write Cycle

Write command hold time

WCH

Write command pulse width

Write command setup time

WCS

Write command to RAS lead time

R WL

Write command to CAS lead time

C WL

Data setup time

Data hold time

CAS delay time from Din

DZC

Read-Modify-Write Cycle

Read-write cycle time

R WC

105

126

150

RAS to WE delay time

R WD

CAS to WE delay time

C WD

Column address to WE delay time

A WD

OE command hold time

OEH

Fast Page Mode Cycle

Fast page mode cycle time

Access time from CAS precharge

CPA

RAS pulse width

RAS

200k

200k 60

200k

CAS precharge to RAS Delay

RHPC

AC Characteristics

(cont'd)

(note: 6,7,8)

AC64-2F

= 0 to 70 °C,

= 3.3

0.3V

Parameter

Symbol

-40

-50

-60

Unit Note

min.

max. min.

max.

Semiconductor Group

HYB3164(5)800AJ/AT(L)-40/-50/-60

8M x 8-DRAM

Fast Page Mode Read-Modify-Write Cycle

Fast page mode read-write cycle
time

PR WC

CAS precharge to WE

CP WD

CAS-before-RAS Refresh Cycle

CAS setup time

CSR

CAS hold time

CHR

RAS to CAS precharge time

RPC

Write to RAS precharge time

WRP

Write hold time referenced to RAS

WRH

Self Refresh Cycle (L-version only)

RAS pulse width

RASS

100k

RAS precharge time

RPS

110

CAS hold time

CHS

-50

Test Mode Cycle

Write command setup time

WTS

Write command hold time

WTH

Capacitance

= 0 to 70 °C,

= 3.3 V

0.3 V,

= 1 MHz

Parameter

Symbol

Limit Values

Unit

min.

max.

Input capacitance (A0 to A11,A12)

Input capacitance (RAS, CAS, WE, OE)

I/O capacitance (I/O1-I/O8)

AC Characteristics

(cont'd)

(note: 6,7,8)

AC64-2F

= 0 to 70 °C,

= 3.3

0.3V

Parameter

Symbol

-40

-50

-60

Unit Note

min.

max. min.

max.

Semiconductor Group

HYB3164(5)800AJ/AT(L)-40/-50/-60

8M x 8-DRAM

Notes:

1) All voltages are referenced to VSS.
Vih may overshoot to Vcc + 2.0 V for pulse widths of < 4ns with 3.3V. Vil may undershoot to -2.0V for pulse

width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.

2) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less

during a fast page mode cycle ( tpc).

5) An initial pause of 100

s is required after power-up followed by 8 RAS-only-refresh cycles, before proper

device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS
initialization cycles instead of 8 RAS cycles are required.

6) AC measurements assume tT = 5 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are

measured between VIH and VIL.

8) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a

reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.

10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a

reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.

11) Either tRCH or tRRH must be satisfied for a read cycle.
12) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are

not referenced to output voltage levels.

13) Either tDZC or tDZO must be satisfied.
14) Either tCDD or tODD must be satisfied.
15) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data

sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin
will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD
(min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition
of the I/O pins (at access time) is indeterminate.

16) These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in

Read-Modify-Write cycles.

17) When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM

operation:

If row addresses are being refresh in an evenly distributed manner over the refresh iterval using CBR refresh

cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh.

If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the

refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey
after exit from Self Refresh.

18) In a Test Mode Read Cycle, the value of trac, taa, tcac and tcpa are delayed by 5 ns from the specified value.

These parameters must be adjusted in Test Mode cycles by adding 5ns to the specified value. Associated
timings must be adjusted by 5 ns.

Semiconductor Group

HYB3164(5)800AJ/AT(L)-40/-50/-60

8M x 8-DRAM

Read Cycle

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

Row

Column

Row

AAAA

Valid Data Out

RAS

CAS

Address

I/O
(Inputs)

I/O
(Outputs)

VIL

RAS

CSH

RAD

CAS

RAH

CRP

RSH

RCD

RAL

ASR

CAH

ASC

ASR

RCH

RRH

RCS

OEA

CLZ

CAC

OEZ

ODD

CDD

OFF

DZC

DZO

RAC

Hi Z

AAAA

"H" or "L"

WL1

Semiconductor Group

HYB3164(5)800AJ/AT(L)-40/-50/-60

8M x 8-DRAM

Write Cycle (Early Write)

AAAA

RAS

CAS

Address

I/O
(Inputs)

I/O
(Outputs)

VIL

RAS

CSH

RAD

CAS

CRP

RSH

RCD

RAL

ASR

CAH

ASR

AAAA

AAA

AAAA

AAA

AAAA

AAA

CWL

RWL

ASC

WCH

Valid Data In

Hi Z

Column

AAAA

Row

RAH

WCS

AAAA

AAA

"H" or "L"

WL2

Semiconductor Group

HYB3164(5)800AJ/AT(L)-40/-50/-60

8M x 8-DRAM

Write Cycle (OE Controlled Write)

AAAA

AAA

AAAA

Valid Data

AAAA

RWL

OEH

ODD

CWL

AAAA

DZO

OEA

CLZ

OEZ

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

Row

DZC

AAAA

"H" or "L"

Hi-Z

Column

Row

ASC

RAD

RAL

CAH

RAH

RAS

CAS

Address

I/O
(Inputs)

I/O
(Outputs)

VIL

VOL

RAS

CSH

CAS

CRP

RSH

RCD

ASR

WL3

Semiconductor Group

HYB3164(5)800AJ/AT(L)-40/-50/-60

8M x 8-DRAM

Read-Write (Read-Modify-Write) Cycle

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

Row

CSH

CAS

CRP

RWC

AWD

ASR

RAS

RAH

CAH

I/O
(Outputs)

VIL

I/O
(Inputs)

VIL

ASR

Column

RCD

RSH

RAD

CWD

OEH

RWD

RWL

CWL

CLZ

RCS

OEA

DZC

DZO

ODD

CAC

OEZ

Valid

Data in

Data

Out

RAC

AAAA

"H" or "L"

ASC

RAS

CAS

Address

WL4

Semiconductor Group

HYB3164(5)800AJ/AT(L)-40/-50/-60

8M x 8-DRAM

Fast Page Mode Read Cycle

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

RASP

CAS

RCD

CSH

CAH

ASC

ASR

RAH

RAD

RCS

ASC

CAH

CAS

RSH

CRP

ASR

RCH

CPA

OEA

DZC

CDD

RRH

CPA

OEA

DZC

DZO

ODD

DZO

ODD

DZO

OFF

OEZ

OFF

OEZ

CAC

CLZ

OFF

RAC

CAC

Valid

Data Out

Valid

Column

Row

RAS

I/O
(Outputs)

I/O
(Inputs)

Address

CAS

VIL

AAAA

"H" or "L"

RHPC

RCH

VOL

Column

FPM1

Semiconductor Group

HYB3164(5)800AJ/AT(L)-40/-50/-60

8M x 8-DRAM

Fast Page Mode Early Write Cycle

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

RAS

RSH

CAS

CRP

RAL

CAH

ASR

CWL

RWL

CAH

ASC

CWL

WCS

WCH

RAD

CAS

RCD

CAH

RAH

ASR

ASC

Column

Row

Valid

Data In

Valid

Data In

Column

HI-Z

RAS

I/O
(Outputs)

I/O
(Inputs)

Address

CAS

VIL

AAAA

AAA

"H" or "L"

FPM2

Semiconductor Group

HYB3164(5)800AJ/AT(L)-40/-50/-60

8M x 8-DRAM

Fast Page Mode Read-Modify-Write Cycle

AAAA

OEA

ASR

ASC

ASR

ASC

CWL

CWD

OEH

OEZ

OEA

OEZ

OEH

OEA

OEH

V OL

ts)

(Ou

t
p

ts)

t
a

lumn

ess

l
u

lumn

AAAA

AAA

" o

r

"
L

OEZ

Semiconductor Group

HYB3164(5)800AJ/AT(L)-40/-50/-60

8M x 8-DRAM

RAS-Only Refresh Cycle

AAAA

CRP

RAH

RAS

ASR

RPC

VIL

Row

HI-Z

Address

RAS

CAS

I/O
(Outputs)

AAAA

"H" or "L"

WL9

Semiconductor Group

HYB3164(5)800AJ/AT(L)-40/-50/-60

8M x 8-DRAM

CAS-Before-RAS Refresh Cycle

AAAA

RAS

CRP

RPC

CHR

WRH

WRP

CSR

RPC

OFF

OEZ

CDD

ODD

VIL

HI-Z

AAAA

"H" or "L"

RAS

I/O
(Outputs)

I/O
(Inputs)

CAS

WL10

Semiconductor Group

HYB3164(5)800AJ/AT(L)-40/-50/-60

8M x 8-DRAM

Hidden Refresh Cycle (Read)

AAAA

AAA

RAS

I/O
(Outputs)

I/O
(Inputs)

Address

CAS

RAS

CRP

CHR

RAD

CAH

ASC

RAH

ASR

RCS

RRH

DZC

DZO

CAC

RAC

CLZ

OEZ

OFF

ODD

CDD

RCD

RSH

OEA

VIL

WRP

WRH

AAAA

AAA

"H" or "L"

Valid Data Out

Row

Column

Row

HI-Z

VOL

WL11

Semiconductor Group

HYB3164(5)800AJ/AT(L)-40/-50/-60

8M x 8-DRAM

Hidden Refresh Cycle (Early Write)

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

RAS

I/O

(Output)

I/O

(Input)

Address

CAS

VIL

AAAA

"H" or "L"

RAS

RCD

RSH

RAD

CAH

WCS

WCH

ASR

RAH

ASR

CRP

CHR

RAS

ASC

Row

Valid Data

HI-Z

Column

WRP

WRH

WL12

Semiconductor Group

HYB3164(5)800AJ/AT(L)-40/-50/-60

8M x 8-DRAM

Test Mode Entry Cycle

AAAA

AAA

AAAA

AAA

AAAA

RAS

RPC

CRP

CHR

WTH

RPC

CSR

WTS

CDD

OFF

OEZ

ODD

I/O
(Outputs)

I/O
(Inputs)

VIL

CAS

RAS

VIL

AAAA

"H" or "L"

HI-Z

Address

AAAA

AAA

AAAA

AAA

RAH

ASR

Row

WL15

HI-Z

Semiconductor Group

HYB3164(5)800AJ/AT(L)-40/-50/-60

8M x 8-DRAM

Self Refresh (,,Sleep Mode") L-version only

AAAA

AAA

AAAA

RPS

RASS

CRP

RPC

WRH

WRP

CSR

OFF

OEZ

CDD

ODD

VIL

HI-Z

AAAA

"H" or "L"

RAS

I/O

(Outputs)

I/O

(Inputs)

CAS

VOL

CHS

WL13

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HYB3164800AJ-50

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HYB3164800AJ-50