ChipFind - документация

Электронный компонент: HYB3164805J-50

Скачать:  PDF   ZIP
Semiconductor Group
149
8 388 608 words by 8-bit organization
0 to 70 C operating temperature
Fast access and cycle time
RAS access time:
50 ns (-50 version)
60 ns (-60 version)
Cycle time:
84 ns (-50 version)
104 ns (-60 version)
CAS access time:
13 ns ( -50 version)
15 ns ( -60 version)
Hyper page mode (EDO) cycle time
20 ns (-50 version)
25 ns (-60 version)
Single + 3.3 V (
0.3V) power supply
Low power dissipation
max. 396 active mW ( HYB 3164805J/T(L)-50)
max. 360 active mW ( HYB 3164805J/T(L)-60)
max. 504 active mW ( HYB 3165805J/T(L)-50)
max. 432 active mW ( HYB 3165805J/T(L)-60)
7.2 mW standby (TTL)
720 W standby (MOS)
14.4 mW Self Refresh (L-version only)
Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh and self refresh modes
Hyper page mode (EDO) capability
8192 refresh cycles/128 ms , 13 R/ 11C addresses (HYB 3164805J/T(L))
4096 refresh cycles/ 64 ms , 12 R/ 12C addresses (HYB 3165805J/T(L))
Plastic Package:
P-SOJ-34-1 500 mil HYB 3164(5)805J
P-TSOPII-34-1 500 mil HYB 3164(5)805T(L)
HYB 3164805J/T(L) -50/-60
HYB 3165805J/T(L) -50/-60
8M x 8-Bit Dynamic RAM
(4k & 8k Refresh, EDO-version)
Preliminary Information
Semiconductor Group
150
HYB3164(5)805J/T(L)-50/-60
8M x 8 EDO-DRAM
This HYB3164(5)805 is a 64 MBit dynamic RAM organized 8 388 608 x 8 bits. The device is
fabricated in SIEMENS/IBM most advanced first generation 64Mbit CMOS silicon gate process
technology. The circuit and process design allow this device to achieve high performance and low
power dissipation. The HYB3164(5)805 operates with a single 3.3 +/-0.3V power supply and
interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB
3164(5)805 to be packaged in a 500mil wide SOJ-34 or TSOP-34 plastic package. These packages
provide high system bit densities and are compatible with commonly used automatic testing and
insertion equipment.The HYB3164(5)805TL parts have a very low power ,,sleep mode" supported
by Self Refresh.
Ordering Information
Pin Names
Type
Ordering
Code
Package
Descriptions
HYB 3164805J-50
on request
P-SOJ-34-1 500 mil DRAM (access time 50 ns)
HYB 3164805J-60
on request
P-SOJ-34-1 500 mil DRAM (access time 60 ns)
HYB 3164805T-50
on request
P-TSOPII-34-1 500 mil DRAM (access time 50 ns)
HYB 3164805T-60
on request
P-TSOPII-34-1 500 mil DRAM (access time 60 ns)
HYB 3164805TL-50 on request
P-TSOPII-34-1 500 mil DRAM (access time 50 ns)
HYB 3164805TL-60 on request
P-TSOPII-34-1 500 mil DRAM (access time 60 ns)
HYB 3165805J-50
on request
P-SOJ-34-1 500 mil DRAM (access time 50 ns)
HYB 3165805J-60
on request
P-SOJ-34-1 500 mil DRAM (access time 60 ns)
HYB 3165805T-50
on request
P-TSOPII-34-1 500 mil DRAM (access time 50 ns)
HYB 3165805T-60
on request
P-TSOPII-34-1 500 mil DRAM (access time 60 ns)
HYB 3165805TL-50 on request
P-TSOPII-34-1 500 mil DRAM (access time 50 ns)
HYB 3165805TL-60 on request
P-TSOPII-34-1 500 mil DRAM (access time 60 ns)
A0-A12
Address Inputs for HYB 3164805J/T(L)
A0-A11
Address Inputs for HYB 3165805J/T(L)
RAS
Row Address Strobe
OE
Output Enable
I/O1-I/O8
Data Input/Output
CAS
Column Address Strobe
WRITE
Read/Write Input
Vcc
Power Supply ( + 3.3V)
Vss
Ground
Semiconductor Group
151
HYB3164(5)805J/T(L)-50/-60
8M x 8 EDO-DRAM
Pin Configuration
P-SOJ-34-1 (500 mil)
P-TSOPII-34-1 (500 mil)
Semiconductor Group
152
HYB3164(5)805J/T(L)-50/-60
8M x 8 EDO-DRAM
TRUTH TABLE
FUNCTION
RAS
CAS
WRITE
OE
ROW
ADDR
COL
ADDR
I/O1-
I/O4
Standby
H
H - X
X
X
X
X
High Impedance
Read
L
L
H
L
ROW
COL
Data Out
Early-Write
L
L
L
X
ROW
COL
Data In
Delayed-Write
L
L
H - L
H
ROW
COL
Data In
Read-Modify-Write
L
L
H - L
L - H
ROW
COL
Data Out, Data In
Hyper Page Mode Read
1st Cycle
L
H - L
H
L
ROW
COL
Data Out
2nd Cycle
L
H - L
H
L
n/a
COL
Data Out
Hyper Page Mode Write 1st Cycle
L
H - L
L
X
ROW
COL
Data In
2nd Cycle
L
H - L
L
X
n/a
COL
Data In
Hyper Page Mode RMW 1st Cycle
L
H - L
H - L
L - H
ROW
COL
Data Out, Data In
2st Cycle
L
H - L
H - L
L - H
n/a
COL
Data Out, Data In
RAS only refresh
L
H
X
X
ROW
n/a
High Impedance
CAS-before-RAS refresh
H - L
L
H
X
X
n/a
High Impedance
Test Mode Entry
H - L
L
L
X
X
n/a
High Impedance
Hidden Refresh
READ
L-H-L
L
H
L
ROW
COL
Data Out
WRITE
L-H-L
L
L
X
ROW
COL
Data In
Self Refresh
(L-version only)
H - L
L
H
X
X
X
High Impedance
Semiconductor Group
153
HYB3164(5)805J/T(L)-50/-60
8M x 8 EDO-DRAM
Block Diagram for HYB 3165805J/T(L)