Semiconductor Group
121
8 388 608 words by 8-bit organization
0 to 70 C operating temperature
Fast access and cycle time
RAS access time:
50 ns (-50 version)
60 ns (-60 version)
Cycle time:
90 ns (-50 version)
110 ns (-60 version)
CAS access time:
13 ns ( -50 version)
15 ns ( -60 version)
Fast page mode cycle time
35 ns (-50 version)
40 ns (-60 version)
Single + 3.3 V (
0.3V) power supply
Low power dissipation
max. 396 active mW ( HYB 3164800J/T-50)
max. 360 active mW ( HYB 3164800J/T-60)
max. 504 active mW ( HYB 3165800J/T-50)
max. 432 active mW ( HYB 3165800J/T-60)
7.2 mW standby (TTL)
720 W standby (MOS)
Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh and self refresh modes
Fast page mode capability
8192 refresh cycles/128 ms , 13 R/ 10C addresses (HYB 3164800J/T)
4096 refresh cycles/ 64 ms , 12 R/ 11C addresses (HYB 3165800J/T)
Plastic Package:
P-SOJ-34-1 500 mil HYB 3164(5)800J
P-TSOPII-34-1 500 mil HYB 3164(5)800T
8M x 8-Bit Dynamic RAM
Preliminary Information
HYB 3164800J/T -50/-60
HYB 3165800J/T -50/-60
(4k & 8k Refresh)
Semiconductor Group
122
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
This device is a 64 MBit dynamic RAM organized 8 388 608 by 8 bits. The device is fabricated in
SIEMENS/IBM's most advanced first generation 64Mbit CMOS silicon gate process technology.
The circuit and process design allow this device to achieve high performance and low power
dissipation. This DRAM operates with a single 3.3 +/-0.3V power supply and interfaces with either
LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)800J/T to be
packaged in a 500 mil wide SOJ-34 or TSOP-34 plastic package. These packages provide high
system bit densities and are compatible with commonly used automatic testing and insertion
equipment.
Ordering Information
Pin Names
Type
Ordering
Code
Package
Descriptions
HYB 3164800J-50
on request
P-SOJ-34-1 500 mil DRAM (access time 50 ns)
HYB 3164800J-60
on request
P-SOJ-34-1 500 mil DRAM (access time 60 ns)
HYB 3164800T-50
on request
P-TSOPII-34-1 500 mil DRAM (access time 50 ns)
HYB 3164800T-60
on request
P-TSOPII-34-1 500 mil DRAM (access time 60 ns)
HYB 3165800J-50
on request
P-SOJ-34-1 500 mil DRAM (access time 50 ns)
HYB 3165800J-60
on request
P-SOJ-34-1 500 mil DRAM (access time 60 ns)
HYB 3165800T-50
on request
P-TSOPII-34-1 500 mil DRAM (access time 50 ns)
HYB 3165800T-60
on request
P-TSOPII-34-1 500 mil DRAM (access time 60 ns)
A0-A12
Address Inputs for HYB 3164800J/T
A0-A11
Address Inputs for HYB 3165800J/T
RAS
Row Address Strobe
OE
Output Enable
I/O1-I/O8
Data Input/Output
CAS
Column Address Strobe
WRITE
Read/Write Input
Vcc
Power Supply ( + 3.3V)
Vss
Ground
Semiconductor Group
123
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Pin Configuration
P-SOJ-34-1 (500 mil)
P-TSOPII-34-1 (500 mil)
Semiconductor Group
124
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
TRUTH TABLE
FUNCTION
RAS
CAS
WRITE
OE
ROW
ADDR
COL
ADDR
I/O1-
I/O8
Standby
H
H - X
X
X
X
X
High Impedance
Read
L
L
H
L
ROW
COL
Data Out
Early-Write
L
L
L
X
ROW
COL
Data In
Delayed-Write
L
L
H - L
H
ROW
COL
Data In
Read-Modify-Write
L
L
H - L
L - H
ROW
COL
Data Out, Data In
Fast Page Mode Read
1st Cycle
L
H - L
H
L
ROW
COL
Data Out
2nd Cycle
L
H - L
H
L
n/a
COL
Data Out
Fast Page Mode Early
Write
1st Cycle
L
H - L
L
X
ROW
COL
Data In
2nd Cycle
L
H - L
L
X
n/a
COL
Data In
Fast Page Mode RMW
1st Cycle
L
H - L
H - L
L - H
ROW
COL
Data Out, Data In
2st Cycle
L
H - L
H - L
L - H
n/a
COL
Data Out, Data In
RAS only refresh
L
H
X
X
ROW
n/a
High Impedance
CAS-before-RAS refresh
H - L
L
H
X
X
n/a
High Impedance
Test Mode Entry
H - L
L
L
X
X
n/a
High Impedance
Hidden Refresh
READ
L-H-L
L
H
L
ROW
COL
Data Out
WRITE
L-H-L
L
L
X
ROW
COL
Data In
Semiconductor Group
125
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Block Diagram for HYB 3165800J/T
Semiconductor Group
126
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Block Diagram for HYB 3164800J/T
Semiconductor Group
127
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Absolute Maximum Ratings
Operating temperature range..............................................................................................0 to 70 C
Storage temperature range......................................................................................... 55 to 150 C
Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V
Power supply voltage....................................................................................................-0.5V to 4.6 V
Power dissipation......................................................................................................................1.0 W
Data out current (short circuit)..................................................................................................50 mA
Note
Stresses above those listed under ,,Absolute Maximum Ratings" may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may effect device
reliability.
DC Characteristics
T
A
= 0 to 70 C,
V
SS
= 0 V,
V
CC
= 3.3 V
0.3 V, (values in brackets for HYB 3165800J/T)
Parameter
Symbol
Limit Values
Unit Note
min.
max.
Input high voltage
V
IH
2.0
Vcc+0.3
V
1)
Input low voltage
V
IL
0.3
0.8
V
1)
Output high voltage (LVTTL)
Output ,,H" level voltage (Iout = -2mA)
V
OH
2.4
V
Output low voltage (LVTTL)
Output ,,L"level voltage (Iout = +2mA)
V
OL
0.4
V
Output high voltage (LVCMOS)
Output ,,H" level voltage (Iout = -100uA)
V
OH
Vcc-0.2 -
V
Ouput low voltage (LVCMOS)
Output ,,L" level voltage (Iout = +100uA)
V
OL
-
0.2
V
Input leakage current,any input
(0 V < Vin < Vcc , all other pins = 0 V
I
I(L)
2
2
A
Output leakage current
(DO is disabled, 0 V < Vout < Vcc )
I
O(L)
2
2
A
Average Vcc supply current:
-50 ns version
-60 ns version
(RAS, CAS, address cycling: tRC = tRC min.)
I
CC1
110 (140)
100 (120)
mA
mA
2) 3) 4)
Standby Vcc supply current
(RAS=CAS= Vih)
I
CC2
2
mA
Semiconductor Group
128
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Average Vcc supply current, during RAS-only
refresh cycles:
-50 ns version
-60 ns version
(RAS cycling: CAS = VIH: tRC = tRC min.)
I
CC3
110 (140)
100 (120)
mA
mA
2) 4)
Average Vcc supply current,
during fast page mode:
-50 ns version
-60 ns version
(RAS =
V
IL
, CAS, address cycling: tPC=tPC min.)
I
CC4
85 (85)
75 (75)
mA
mA
2) 3) 4)
Standby Vcc supply current
(RAS=CAS= Vcc-0.2V)
I
CC5
200
A
Average Vcc supply current, during CAS-before-
RAS refresh mode:
-50 ns version
-60 ns version
(RAS, CAS cycling: tRC = tRC min.)
I
CC6
110 (140)
100 (120)
mA
mA
2) 4)
Self Refresh Current
Average Power Supply Current during Self Refresh.
(CBR cycle with tRAS>TRASSmin, CAS held low,
WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
I
CC7
400
A
Capacitance
T
A
= 0 to 70 C,
V
CC
= 3.3 V
0.3 V,
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A11,A12)
C
I1
5
pF
Input capacitance (RAS, CAS, WRITE, OE)
C
I2
7
pF
I/O capacitance (I/O1-I/O8)
C
IO
7
pF
DC Characteristics
(cont'd)
T
A
= 0 to 70 C,
V
SS
= 0 V,
V
CC
= 3.3 V
0.3 V, (values in brackets for HYB 3165800J/T)
Parameter
Symbol
Limit Values
Unit Note
min.
max.
Semiconductor Group
129
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
AC Characteristics (note: 6,7,8)
T
A
= 0 to 70 C,
V
CC
= 3.3
0.3V
Parameter
Symbol
HYB
3164(5)800
J/T-50
HYB
3164(5)800
J/T-60
Unit
Note
min.
max.
min.
max.
common parameters
Random read or write cycle time
t
RC
90
110
ns
RAS precharge time
t
RP
30
40
ns
RAS pulse width
t
RAS
50
100k
60
100k
ns
CAS pulse width
t
CAS
13
100k
15
100k
ns
Row address setup time
t
ASR
0
0
ns
Row address hold time
t
RAH
8
10
ns
Column address setup time
t
ASC
0
0
ns
Column address hold time
t
CAH
10
10
ns
RAS to CAS delay time
t
RCD
18
37
20
45
RAS to column address delay time
t
RAD
13
25
15
30
ns
RAS hold time
t
RSH
13
15
ns
CAS hold time
t
CSH
50
60
ns
CAS to RAS precharge time
t
CRP
5
5
ns
Transition time (rise and fall)
t
T
3
30
3
30
ns
7
Refresh period for HYB3164800
t
REF
128
128
ms
Refresh period for HYB3165800
t
REF
64
64
ms
Read Cycle
Access time from RAS
t
RAC
50
60
ns
8, 9
Access time from CAS
t
CAC
13
15
ns
8, 9
Access time from column address
t
AA
25
30
ns
8, 10
OE access time
t
OEA
13
15
ns
8
Column address to RAS lead time
t
RAL
25
30
ns
Read command setup time
t
RCS
0
0
ns
Read command hold time
t
RCH
0
0
ns
11
Read command hold time referenced
to RAS
t
RRH
0
0
ns
11
Semiconductor Group
130
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
CAS to output in low-Z
t
CLZ
0
0
ns
8
Output buffer turn-off delay
t
OFF
13
15
ns
12
Output buffer turn-off delay from OE
t
OEZ
13
15
ns
12
Data to OE low delay
t
DZO
0
0
ns
13
CAS high to data delay
t
CDD
13
15
ns
14
OE high to data delay
t
ODD
13
15
ns
14
Write Cycle
Write command hold time
t
WCH
8
10
ns
Write command pulse width
t
WP
8
10
ns
Write command setup time
t
WCS
0
0
ns
15
Write command to RAS lead time
t
RWL
13
15
ns
Write command to CAS lead time
t
CWL
13
15
ns
Data setup time
t
DS
0
0
ns
16
Data hold time
t
DH
10
10
ns
16
CAS delay time from Din
t
DZC
0
0
ns
13
Read-Modify-Write Cycle
Read-write cycle time
t
RWC
126
150
ns
RAS to WE delay time
t
RWD
68
80
ns
15
CAS to WE delay time
t
CWD
31
35
ns
15
Column address to WE delay time
t
AWD
43
50
ns
15
OE command hold time
t
OEH
13
15
ns
Fast Page Mode Cycle
Fast page mode cycle time
t
PC
35
40
ns
CAS precharge time
t
CP
10
10
ns
Access time from CAS precharge
t
CPA
30
35
ns
8
RAS pulse width
t
RAS
50
200k
60
200k
ns
AC Characteristics
(cont'd)
(note: 6,7,8)
T
A
= 0 to 70 C,
V
CC
= 3.3
0.3V
Parameter
Symbol
HYB
3164(5)800
J/T-50
HYB
3164(5)800
J/T-60
Unit
Note
min.
max.
min.
max.
Semiconductor Group
131
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
CAS precharge to RAS Delay
t
RHCP
30
35
ns
Fast Page Mode Read-Modify-Write
Cycle
Fast page mode read-write cycle time
t
PRWC
71
80
ns
CAS precharge to WE
t
CPWD
48
55
ns
CAS-before-RAS refresh cycle
CAS setup time
t
CSR
5
5
ns
CAS hold time
t
CHR
10
10
ns
RAS to CAS precharge time
t
RPC
5
5
ns
Write to RAS precharge time
t
WRP
10
10
ns
Write hold time referenced to RAS
t
WRH
10
10
ns
CAS-before-RAS counter test cycle
CAS precharge time
t
CPT
25
30
ns
Test mode cycle
Write command setup time
t
WTS
10
10
ns
Write command hold time
t
WTH
10
10
ns
Self Refresh Cycle
RAS pulse width
t
RASS
100k
100k
ns
17
RAS precharge time
t
RPS
90
110
17
CAS hold time
t
CHS
-50
-50
ns
17
AC Characteristics
(cont'd)
(note: 6,7,8)
T
A
= 0 to 70 C,
V
CC
= 3.3
0.3V
Parameter
Symbol
HYB
3164(5)800
J/T-50
HYB
3164(5)800
J/T-60
Unit
Note
min.
max.
min.
max.
Semiconductor Group
132
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less
during a fast page mode cycle ( tpc).
5) An initial pause of 100 s is required after power-up followed by 8 RAS-only-refresh cycles, before proper
device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS
initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 5 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are
measured between VIH and VIL.
8) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
11) Either tRCH or tRRH must be satisfied for a read cycle.
12) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are
not referenced to output voltage levels.
13) Either tDZC or tDZO must be satisfied.
14) Either tCDD or tODD must be satisfied.
15) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin
will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD
(min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition
of the I/O pins (at access time) is indeterminate.
16) These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in
Read-Modify-Write cycles.
17) When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refresh in an evenly distributed manner over the refresh iterval using CBR refresh
cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh.
If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the
refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey
after exit from Self Refresh
Semiconductor Group
133
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Read Cycle
Row
Address
Column
Address
Row
Address
Valid Data Out
RAS
CAS
Address
WRITE
OE
I/O1-I/O4
(Inputs)
I/O1-I/O8
(Outpus)
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
t
RAS
t
RC
t
CSH
t
RAD
t
CAS
t
RP
t
RAH
t
CRP
t
RSH
t
RCD
t
RAL
t
ASR
t
CAH
t
ASC
t
ASR
t
RCH
t
RRH
t
RCS
t
AA
t
OEA
t
CLZ
t
CAC
t
OEZ
t
ODD
t
CDD
t
OFF
t
DZC
t
DZO
t
RAC
Hi Z
Hi Z
"H" or "L"
8
Semiconductor Group
134
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Write Cycle (Early Write)
RAS
CAS
Address
WRITE
OE
I/O1-I/O8
(Inputs
I/O1-I/O8
(Outputs)
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
.
t
RAS
t
RC
t
CSH
t
RAD
t
CAS
t
RP
t
CRP
t
RSH
t
RCD
t
RAL
t
ASR
t
CAH
t
ASR
t
CWL
t
RWL
t
WP
t
ASC
t
WCH
Valid Data In
t
DS
t
DH
Hi Z
Column
Address
Address
Row
Row
Address
t
RAH
t
WCS
"H" or "L"
Semiconductor Group
135
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Write Cycle (OE Controlled Write)
Valid Data
t
RWL
t
WP
t
OEH
t
ODD
t
CWL
t
DZO
t
OEA
t
CLZ
t
DS
t
OEZ
t
DH
t
RC
V
IH
V
IL
Row
Address
t
DZC
"H" or "L"
Hi-Z
Hi-Z
Column
Address
Address
Row
t
ASC
t
RAD
t
RAL
t
CAH
t
RAH
RAS
CAS
Address
WRITE
OE
I/O1-I/O8
(Inputs)
I/O1-I/O8
(Outputs)
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
.
t
RAS
t
CSH
t
CAS
t
RP
t
CRP
t
RSH
t
RCD
t
ASR
t
ASR
Semiconductor Group
136
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Read-Write (Read-Modify-Write) Cycle
Row
Address
Row
Address
t
CSH
t
CAS
t
CRP
t
RWC
t
AWD
t
ASR
t
RP
t
RAS
t
RAH
t
CAH
I/O1-I/O8
(Outputs)
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
I/O1-I/O8
(Inputs)
OE
WRITE
V
IH
V
IL
t
ASR
Column
Address
t
RCD
t
DH
t
RSH
t
RAD
t
CWD
t
OEH
t
RWD
t
RWL
t
CWL
t
CLZ
t
WP
t
RCS
t
AA
t
OEA
t
DS
t
DZC
t
DZO
t
ODD
t
CAC
t
OEZ
Valid
Data in
Data
Out
t
RAC
"H" or "L"
t
ASC
V
IH
V
IL
V
IH
V
IL
RAS
CAS
Address
V
IH
V
IL
Semiconductor Group
137
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Fast Page Mode Read-Modify-Write Cycle
t
CAH
t
CP
t
DZC
t
DZO
t
RAC
t
CAC
t
CLZ
t
RCS
t
AA
t
OEA
t
RCD
t
RAD
t
RAH
t
ASR
t
ASC
t
CAS
t
CAS
t
PRWC
t
CWD
t
CAH
t
ASC
t
CAS
t
RSH
t
RP
t
CRP
t
ASR
t
CAH
t
ASC
t
RAL
t
CWD
t
RWD
t
CWL
t
CWL
t
CWD
t
AWD
t
AWD
t
WP
t
WP
t
CWL
t
RWL
t
AWD
t
WP
t
ODD
t
OEH
t
DH
t
DS
t
CPA
t
OEZ
t
CLZ
t
DZC
t
AA
t
CAC
t
OEA
t
DS
t
OEZ
t
DH
t
OEH
t
AA
t
ODD
t
DZC
t
CPA
t
OEA
t
CLZ
t
DS
t
DH
t
OEH
t
ODD
RAS
V
IH
V
IL
CAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V OL
WRITE
OE
Address
(Inputs)
(Outputs)
Data In
Data In
Data In
Data
Out
Out
Data
Data Out
Address
Row
Column
Address
Address
Column
Address
Row
Address
t
RASP
t
CSH
Column
t
CPWD
t
CPWD
"H" or "L"
I/O1-I/O8
I/O1-I/O8
Semiconductor Group
138
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Fast Page Mode Read Cycle
t
RASP
t
CAS
t
CAS
t
PC
t
CP
t
RCD
t
CSH
t
CAH
t
CAH
t
ASC
t
ASC
t
ASR
t
RAH
t
RAD
t
RCS
t
RCS
t
RCS
t
ASC
t
CAH
t
CAS
t
RSH
t
CRP
t
RP
t
ASR
t
RCH
t
CPA
t
OEA
t
OEA
t
AA
t
AA
t
DZC
t
DZC
t
CDD
t
RRH
t
CPA
t
OEA
t
AA
t
DZC
t
DZO
t
ODD
t
ODD
t
DZO
t
ODD
t
DZO
t
OFF
t
OEZ
t
OEZ
t
OFF
t
OEZ
t
CAC
t
CAC
t
CLZ
t
CLZ
t
CLZ
t
OFF
t
OFF
t
CAC
Valid
Data Out
Data Out
Data Out
Valid
Valid
Column
Address
Address
Addr
Address
Column
Row
Row
RAS
I/O1-I/O8
(Outputs)
I/O1-I/O8
(Inputs)
OE
WRITE
Address
CAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
"H" or "L"
t
RHCP
t
RCH
V
OH
V
OL
Column
Address
Semiconductor Group
139
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Fast Page Mode Early Write Cycle
t
RASP
t
RP
t
RSH
t
CAS
t
CAS
t
CP
t
CRP
t
RAL
t
CAH
t
ASR
t
CWL
t
RWL
t
CAH
t
ASC
t
ASC
t
CWL
t
CWL
t
WCS
t
WCS
t
WCS
t
WCH
t
WP
t
WP
t
WCH
t
WP
t
WCH
t
RAD
t
CAS
t
RCD
t
PC
t
CAH
t
RAH
t
ASR
t
ASC
t
DH
t
DS
t
DS
t
DH
t
DH
t
DS
Column
Address
Address
Address
Column
Column
Row
Addr
Valid
Data In
Valid
Valid
Data In
Data In
Column
Address
HI-Z
RAS
I/O1-I/O8
(Outputs)
I/O1-I/O8
(Inputs)
OE
WRITE
Address
CAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
"H" or "L"
V
OH
V
OL
Semiconductor Group
140
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
RAS-Only Refresh Cycle
t
CRP
t
RAH
t
RP
t
RAS
t
RC
t
ASR
t
ASR
t
RPC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
Row
Address
Row
Address
HI-Z
Address
RAS
CAS
I/O1-I/O8
(Outputs)
"H" or "L"
Semiconductor Group
141
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
CAS-Before-RAS Refresh Cycle
t
RP
t
RAS
t
RP
t
RC
t
CRP
t
CP
t
RPC
t
CHR
t
WRH
t
WRP
t
CSR
t
RPC
t
OFF
t
OEZ
t
CDD
t
ODD
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
HI-Z
"H" or "L"
RAS
I/O1-I/O8
(Outputs)
I/O1-I/O8
(Inputs)
OE
WRITE
CAS
V
OH
V
OL
Semiconductor Group
142
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Hidden Refresh Cycle (Read)
RAS
I/O1-I/O8
(Outputs)
I/O1-I/O8
(Inputs)
OE
WRITE
Address
CAS
t
RC
t
RC
t
RAS
t
RAS
t
RP
t
RP
t
CRP
t
CHR
t
RAD
t
CAH
t
ASC
t
RAH
t
ASR
t
ASR
t
RCS
t
RRH
t
AA
t
DZC
t
DZO
t
CAC
t
RAC
t
CLZ
t
OEZ
t
OFF
t
ODD
t
CDD
t
RCD
t
RSH
t
OEA
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
WRP
t
WRH
"H" or "L"
Valid Data Out
Row
Address
Column
Address
Row
Addr
HI-Z
V
OH
V
OL
Semiconductor Group
143
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Hidden Refresh Cycle (Early Write)
RAS
I/O1-I/O8
(Outputs)
I/O1-I/O8
(Inputs)
OE
WRITE
V
IH
V
IL
Address
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
CAS
V
IH
V
IL
V
IH
V
IL
"H" or "L"
t
RC
t
RAS
t
RCD
t
RSH
t
RAD
t
CAH
t
WCS
t
WCH
t
WP
t
ASR
t
RAH
t
DS
t
DH
t
ASR
t
CRP
t
CHR
t
RP
t
RAS
t
RC
t
RP
t
ASC
Address
Row
Addr
Row
Address
Valid Data
HI-Z
Column
V
OH
V
OL
Semiconductor Group
144
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
CAS-Before-RAS Refresh Counter Test Cycle
t
CSR
t
ASR
t
ASC
t
CHR
t
CPT
t
WRP
t
RAL
t
CAH
t
RSH
t
RP
t
RAS
t
CAS
t
RCS
t
CDD
t
CAC
t
AA
t
WRH
t
OEA
t
ODD
t
CLZ
t
DZC
t
DZO
t
OEZ
t
OFF
t
RWL
t
CWL
t
WCH
t
WCS
t
WRH
t
WRP
t
DS
t
ODD
t
DH
t
WRH
t
WRP
t
OEZ
t
RWL
t
CWL
t
AWD
t
CWD
t
WP
t
RCS
t
CAC
t
OEA
t
OEH
t
AA
t
CLZ
t
DH
t
DZO
t
DS
t
DZC
t
CAC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
I/O1-I/O8
(Inputs)
RAS
I/O1-I/O8
(Inputs)
OE
WRITE
Address
CAS
I/O1-I/O8
(Outputs)
I/O1-I/O8
(Outputs)
I/O1-I/O8
(Inputs)
WRITE
OE
WRITE
OE
I/O1-I/O8
(Outputs)
Column
Address
Row
Address
Data In
Valid Data Out
Valit
Data In
HI-Z
HI-Z
HI-Z
Read Cycle
Read-Modify-Write Cycle
Write Cycle
t
RRH
t
RCH
D.Out
Semiconductor Group
145
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Test Mode Entry
t
RC
t
RAS
t
RP
t
RPC
t
CRP
t
CHR
t
WTH
t
RPC
t
RP
t
CP
t
CSR
t
WTS
t
CDD
t
OFF
t
OEZ
t
ODD
I/O1-I/O8
(Outputs)
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
I/O1-I/O8
(Inputs)
OE
WRITE
V
IH
V
IL
CAS
RAS
V
IH
V
IL
V
IH
V
IL
"H" or "L"
HI-Z
Adress
t
RAH
t
ASR
V
IH
V
IL
Row
Address
Semiconductor Group
146
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
CAS-before-RAS Self Refresh
t
RPS
t
RASS
t
RP
t
CRP
t
CP
t
RPC
t
WRH
t
WRP
t
CSR
t
OFF
t
OEZ
t
CDD
t
ODD
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
HI-Z
"H" or "L"
RAS
I/O1-I/O8
(Outputs)
I/O1-I/O8
(Inputs)
OE
WRITE
CAS
V
OH
V
OL
t
CHS
Semiconductor Group
147
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Package Outlines
P-SOJ-34-1 (500 mil)
(Plastic Small Outline J-leaded Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book "Package Information".
Dimensions in mm
SMD = Surface Mounted Device
Semiconductor Group
148
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
P-TSOPII-34-1 (500 mil)
(Plastic Thin Small Outline Package Type
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book "Package Information".
Dimensions in mm
SMD = Surface Mounted Device
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