Semiconductor Group 1 12.97

4 194 304 words by 16-bit organization

0 to 70 °C operating temperature

Hyper Page Mode - EDO - operation

Performance:

Single + 3.3 V (

0.3V) power supply

Low power dissipation:

7.2 mW standby (TTL)
3.6 mW standby (MOS)
720

A standby for L-version

Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh and Self Refresh (L-version only

2 CAS / 1 WE byte control

8192 refresh cycles/128 ms , 13 R/ 9C addresses (HYB 3164165BT)
4096 refresh cycles/ 64 ms , 12 R/ 10C addresses (HYB 3165165BT)
2048 refresh cycles/ 32 ms , 11 R/ 11C addresses (HYB 3166165BT)

128 ms refresh period for L-versions

Plastic Package: P-TSOPII-50 400 mil

-40

-50

-60

RAC

RAS access time

CAC

CAS access time

Access time from address

Read/write cycle time

104

HPC

Hyper page mode (EDO)
cycle time

-40

-50

-60

HYB3166165BT(L)

864

702

558

HYB3165165BT(L)

486

396

324

HYB3164165BT(L)

306

252

216

HYB 3164165BT(L) -40/-50/-60

HYB 3165165BT(L) -40/-50/-60

HYB 3166165BT(L) -40/-50/-60

4M x 16-Bit Dynamic RAM

(8k, 4k & 2k Refresh, EDO-version)

Preliminary Information

Semiconductor Group

HYB3164(5/6)165BT(L)-40/-50/-60

4M x 16 EDO-DRAM

This device is a 64 MBit dynamic RAM organized 4 194 304 x 16 bits. The device is fabricated in an
advanced first generation 64Mbit 0,35

m CMOS silicon gate process technology. The circuit and

process design allow this device to achieve high performance and low power dissipation. The
HYB3164(5)165BT operates with a single 3.3 +/-0.3V power supply and interfaces with either
LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB3164(5/6)165BT to be
packaged in 400mil wide TSOPII-50 package. These packages provide high system bit densities
and are compatible with commonly used automatic testing and insertion equipment. The
HYB3164(5/6)165BTL parts have a very low power ,,sleep mode" supported by Self Refresh.

Ordering Information

Type

Ordering
Code

Package

Descriptions

8k-refresh versions:

HYB 3164165BT-40

P-TSOPII-50 400 mil

EDO-DRAM (access time 40 ns)

HYB 3164165BT-50

P-TSOPII-50 400 mil

EDO-DRAM (access time 50 ns)

HYB 3164165BT-60

P-TSOPII-50 400 mil

EDO-DRAM (access time 60 ns)

HYB 3164165BTL-50

P-TSOPII-50 400 mil

EDO-DRAM (access time 50 ns)

HYB 3164165BTL-60

P-TSOPII-50 400 mil

EDO-DRAM (access time 60 ns)

4k-refresh versions:

HYB 3165165BT-40

P-TSOPII-50 400 mil

EDO-DRAM (access time 40 ns)

HYB 3165165BT-50

P-TSOPII-50 400 mil

EDO-DRAM (access time 50 ns)

HYB 3165165BT-60

P-TSOPII-50 400 mil

EDO-DRAM (access time 60 ns)

HYB 3165165BTL-50

P-TSOPII-50 400 mil

EDO-DRAM (access time 50 ns)

HYB 3165165BTL-60

P-TSOPII-50 400 mil

EDO-DRAM (access time 60 ns)

2k-refresh versions:

HYB 3166165BT-40

P-TSOPII-50 400 mil

EDO-DRAM (access time 40 ns)

HYB 3166165BT-50

P-TSOPII-50 400 mil

EDO-DRAM (access time 50 ns)

HYB 3166165BT-60

P-TSOPII-50 400 mil

EDO-DRAM (access time 60 ns)

HYB 3166165BTL-50

P-TSOPII-50 400 mil

EDO-DRAM (access time 50 ns)

HYB 3166165BTL-60

P-TSOPII-50 400 mil

EDO-DRAM (access time 60 ns)

Semiconductor Group

HYB3164(5/6)165BT(L)-40/-50/-60

4M x 16 EDO-DRAM

Pin Names

A0-A12

Address Inputs for 8k-refresh version HYB 3164165T(L)

A0-A11

Address Inputs for 4k-refresh version HYB 3165165T(L)

A0-A10

Address Inputs for 2k-refresh version HYB 3166165T(L)

RAS

Row Address Strobe

Output Enable

I/O1-I/O16

Data Input/Output

UCAS, LCAS

Column Address Strobe

Read/Write Input

Vcc

Power Supply ( + 3.3V)

Vss

Ground

P-TSOPII-50 (400 mil)

* Pin 33 is A12 for HYB 3164165BT(L) and N.C. for HYB 3165(6)165BT(L)

Pin Configuration

** Pin 32 is A11 for HYB 3164(5)165BT(L) and N.C. for HYB 3166165BT(L)

VCC
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
N.C.
VCC
WE
RAS
N.C.
N.C.
N.C.
N.C.

A0
A1
A2
A3
A4
A5
VCC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

VSS
I/O16
I/O15
I/O14
I/O13
VSS
I/O12
I/O11
I/O10
I/O9
N.C.

LCAS
UCAS
OE
N.C.
N.C.
A12/N.C. *
A11/N.C.**
A10
A9
A8
A7
A6
VSS

VSS

27
26

Semiconductor Group

HYB3164(5/6)165BT(L)-40/-50/-60

4M x 16 EDO-DRAM

TRUTH TABLE

FUNCTION

RAS LCAS

UCAS

ROW

ADDR

COL

ADD

I/O1-
I/O16

Standby

H - X

High Impedance

Read:Word

ROW

COL

Data Out

Read:Lower Byte

ROW

COL

Lower Byte:Data Out
Upper-Byte:High-Z

Read:Upper Byte

ROW

COL

Lower Byte:High-Z
Upper Byte:Data Out

Write:Word
(Early-Write)

ROW

COL

Data In

Write:Lower Byte
(Early-Write)

ROW

COL

Lower Byte:Data Out
Upper-Byte:High-Z

Write:Upper Byte
(Early Write)

ROW

COL

Lower Byte:High-Z
Upper Byte:Data Out

Read-Modify-
Write

H - L

L - H ROW

COL

Data Out, Data In

Hyper Page Mode
Read (Word)

1st

Cycle

H - L

ROW

COL

Data Out

Hyper Page Mode
Read (Word)

2nd

Cycle

H - L

n/a

COL

Data Out

Hyper Page Mode
Early Write(Word)

1st

Cycle

H - L

ROW

COL

Data In

Hyper Page Mode
Early Write(Word)

2nd

Cycle

H - L

n/a

COL

Data In

Hyper Page Mode
RMW

1st

Cycle

H - L

L - H ROW

COL

Data Out, Data In

Hyper Page Mode
RMW

2st

Cycle

H - L

L - H

n/a

COL

Data Out, Data In

RAS only refresh

ROW

n/a

High Impedance

CAS-before-RAS
refresh

H - L

n/a

High Impedance

Test Mode Entry

H - L

n/a

High Impedance

Hidden Refresh
(Read)

L-H-

ROW

COL

Data Out

Hidden Refresh
(Write)

L-H-

ROW

COL

Data In

Self Refresh
(L-version only)

H-L

High Impedance

Semiconductor Group

HYB3164(5/6)165BT(L)-40/-50/-60

4M x 16 EDO-DRAM

Absolute Maximum Ratings

Operating temperature range..............................................................................................

0 to 70 °C

Storage temperature range......................................................................................... 55 to 150 °C

Input/output voltage.................................................................................. -0.5 to min (Vcc+0.5,4.6) V

Power supply voltage....................................................................................................

-0.5V to 4.6 V

Power dissipation...............................................................................................................

.......1.1 W

Data out current (short circuit)................................................................................................

..50 mA

Note

Stresses above those listed under ,,Absolute Maximum Ratings" may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may effect device
reliability.

DC Characteristics

= 0 to 70 °C,

= 0 V,

= 3.3 V

0.3 V

Parameter

Symbol

Limit Values

Unit Note

min.

max.

Input high voltage

2.0

Vcc+0.3

Input low voltage

0.3

0.8

Output high voltage (LVTTL)
Output ,,H" level voltage (Iout = -2mA)

2.4

Output low voltage (LVTTL)
Output ,,L"level voltage (Iout = +2mA)

0.4

Output high voltage (LVCMOS)
Output ,,H" level voltage (Iout = -100uA)

Vcc-0.2

Ouput low voltage (LVCMOS)
Output ,,L" level voltage (Iout = +100uA)

0.2

Input leakage current,any input

(0 V < Vin < Vcc , all other pins = 0 V

I(L)

Output leakage current

(DO is disabled, 0 V < Vout < Vcc )

O(L)

Semiconductor Group

HYB3164(5/6)165BT(L)-40/-50/-60

4M x 16 EDO-DRAM

DC-Characteristics (cont'd)

= 0 to 70 °C,

= 0 V,

= 3.3 V

0.3 V

Parameter

Symbol

refresh version

Unit Note

2k 4k 8k

Operating Current
-40 ns version
-50 ns version
- -60 ns version

(RAS, CAS, address cycling: tRC = tRC min.)

CC1

240
195
155

135
110

85
70
60

mA
mA
mA

2) 3)
4)

Standby Current (

RAS

CAS

Vih

)

CC2

RAS Only Refresh Current:

- -40 ns version
-50 ns version
-60 ns version

(RAS cycling: CAS = VIH: tRC = tRC min.)

CC3

240
195
155

135
110

85
70
60

mA
mA
mA

2) 4)

Hyper Page Mode (EDO) Current:

-40 ns version
-50 ns version
-60 ns version

(RAS =

, CAS, address cycling: tHPC=tHPC min.)

CC4

100

mA
mA
mA

2) 3)
4)

Standby Current (

RAS

CAS

Vcc-0.2V

)

CC5

Standby Current (L-Version)

(RAS=CAS= Vcc-0.2V)

CC5

200

CAS Before RAS Refresh Current

-40 ns version

-50 ns version
-60 ns version

(RAS, CAS cycling: tRC = tRC min.)

CC6

240
195
155

135
110

85
70
60

mA
mA
mA

2) 4)

Self Refresh Current (L-version only)

(CBR cycle with tRAS>TRASSmin, CAS held low,
WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)

CC7

400

Capacitance

= 0 to 70 °C,

= 3.3 V

0.3 V,

= 1 MHz

Parameter

Symbol

Limit Values

Unit

min.

max.

Input capacitance (A0 to A11,A12)

Input capacitance (RAS, CAS, WE, OE)

I/O capacitance (I/O1-I/O16)

Semiconductor Group

HYB3164(5/6)165BT(L)-40/-50/-60

4M x 16 EDO-DRAM

AC Characteristics

5)6)

AC64-2E

= 0 to 70 °C,

= 3.3 V

0.3V ,

= 2 ns

Parameter

Symbol

Limit Values

Unit

Note

- 50

- 60

min.

max.

min.

max.

min.

max.

Common Parameters

Random read or write cycle time

104

RAS pulse width

RAS

100k

CAS pulse width

CAS

100k

RAS precharge time

CAS precharge time

Row address setup time

ASR

Row address hold time

RAH

Column address setup time

ASC

Column address hold time

CAH

RAS to CAS delay time

RCD

RAS to column address delay time

RAD

RAS hold time

RSH

CAS hold time

CSH

CAS to RAS precharge time

CRP

Transition time (rise and fall)

Refresh period for 8k-refresh-version

REF

128

Refresh period for 4k-refresh version

REF

Refresh period for L-versions

REF

128

Read Cycle

Access time from RAS

RAC

8, 9

Access time from CAS

CAC

8, 9

Access time from column address

8,10

OE access time

OEA

Column address to RAS lead time

RAL

Read command setup time

RCS

Read command hold time

RCH

Semiconductor Group

HYB3164(5/6)165BT(L)-40/-50/-60

4M x 16 EDO-DRAM

Read command hold time
referenced to RAS

RRH

CAS to output in low-Z

CLZ

Output buffer turn-off delay

OFF

Output buffer turn-off delay from OE

OEZ

Data to CAS low delay

DZC

Data to OE low delay

DZO

CAS high to data delay

CDD

OE high to data delay

ODD

Write Cycle

Write command hold time

WCH

Write command pulse width

Write command setup time

WCS

Write command to RAS lead time

RWL

Write command to CAS lead time

CWL

Data setup time

Data hold time

Read-modify-Write Cycle

Read-write cycle time

RWC

109

133

RAS to WE delay time

RWD

CAS to WE delay time

CWD

Column address to WE delay time

AWD

OE command hold time

OEH

Hyper Page Mode (EDO) Cycle

Hyper page mode (EDO) cycle time

HPC

Access time from CAS precharge

CPA

Output data hold time

COH

AC Characteristics

(cont'd)

5)6)

AC64-2E

= 0 to 70 °C,

= 3.3 V

0.3V ,

= 2 ns

Parameter

Symbol

Limit Values

Unit

Note

- 50

- 60

min.

max.

min.

max.

min.

max.

Semiconductor Group

HYB3164(5/6)165BT(L)-40/-50/-60

4M x 16 EDO-DRAM

RAS pulse width in hyper page mode

RAS

200k

CAS precharge to RAS Delay

RHPC

OE pulse width

OEP

OE hold time from CAS high

OEHC

Output buffer turn-off delay from WE

WEZ

OE setup time prior to CAS

OES

Hyper Page Mode (EDO) Read-
modify-Write Cycle

Hyper page mode (EDO) read-write
cycle time

PRWC

CAS precharge to WE

CPWD

CAS before RAS Refresh Cycle

CAS setup time

CSR

CAS hold time

CHR

RAS to CAS precharge time

RPC

Write to RAS precharge time

WRP

Write hold time referenced to RAS

WRH

Self Refresh Cycle (L-versions only)

RAS pulse width

RASS

100k

100

RAS precharge time

RPS

104

CAS hold time

CHS

-50

AC Characteristics

(cont'd)

5)6)

AC64-2E

= 0 to 70 °C,

= 3.3 V

0.3V ,

= 2 ns

Parameter

Symbol

Limit Values

Unit

Note

- 50

- 60

min.

max.

min.

max.

min.

max.

Semiconductor Group

HYB3164(5/6)165BT(L)-40/-50/-60

4M x 16 EDO-DRAM

Notes:

1) All voltages are referenced to VSS.

Vih may overshoot to Vcc + 2.0 V for pulse widths of < 4ns with 3.3V. Vil may undershoot to -2.0V for pulse

width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.

2) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = Vil. In the case of ICC4 it can be changed once or less

during a Hyper page mode cycle ( thpc).

5) An initial pause of 100

s is required after power-up followed by 8 RAS-only-refresh cycles, before proper

device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS
initialization cycles instead of 8 RAS cycles are required.

6) AC measurements assume tT = 2 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are

measured between VIH and VIL.

8) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a

reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.

10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a

reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.

11) Either tRCH or tRRH must be satisfied for a read cycle.
12) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are

not referenced to output voltage levels.

13) Either tDZC or tDZO must be satisfied.
14) Either tCDD or tODD must be satisfied.
15) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data

sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin
will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD
(min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition
of the I/O pins (at access time) is indeterminate.

16) These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in

Read-Modify-Write cycles.

17) When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM

operation:

If row addresses are being refresh in an evenly distributed manner over the refresh interval using CBR refresh

cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh.

If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the

refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey
after exit from Self Refresh

Semiconductor Group

HYB3164(5/6)165BT(L)-40/-50/-60

4M x 16 EDO-DRAM

Hyper Page Mode (EDO) Read Cycle

RSH

CAS

CRP

RAL

CAH

ASC

CSH

CAS

RCD

RAH

ASR

Column 2

Row

Data Out

RAS

I/O

Address

UCAS

VIL

VIH

VIL

"H" or "L"

RAS

CRP

ASC

HPC

CAH

RAD

RHCP

ASC

RCS

RRH

RCH

(Output)

RAC

CAC

CLZ

OEA

OES

COH

CAC

CPA

Data Out

Column N

Column 1

Data Out

OEZ

OFF

CAC

CPA

COH

WL5

LCAS

Semiconductor Group

HYB3164(5/6)165BT(L)-40/-50/-60

4M x 16 EDO-DRAM

Hyper Page Mode (EDO) Read Cycle (OE Control)

RSH

CAS

CRP

RAL

CAH

ASC

CSH

CAS

RCD

RAH

ASR

Column 2

Row

Data Out

RAS

I/O

Address

UCAS

VIL

VIH

VIL

"H" or "L"

RAS

CRP

ASC

HPC

CAH

RAD

RHCP

ASC

RCS

RRH

RCH

(Output)

RAC

CAC

CLZ

OEA

OES

OEZ

CAC

CPA

Data Out

Column N

Column 1

Data Out

OEZ

OFF

CAC

CPA

OEP

OEHC

OEA

OEP

OEHC

OEZ

OEA

WL6

LCAS

Semiconductor Group

HYB3164(5/6)165BT(L)-40/-50/-60

4M x 16 EDO-DRAM

Hyper Page Mode (EDO) Read Cycle (WE Control)

RSH

CAS

CRP

RAL

CAH

ASC

CSH

CAS

RCD

RAH

ASR

Column 2

Row

Data Out

RAS

I/O

Address

UCAS

VIL

VIH

VIL

"H" or "L"

RAS

CRP

ASC

HPC

CAH

RAD

RHCP

ASC

RCS

RRH

RCH

(Output)

RAC

CAC

CLZ

OEA

OES

WEZ

CAC

CPA

Data Out

Column N

Column 1

Data Out

OEZ

OFF

CAC

CPA

RCH

RCS

WPZ

RCH

RCS

WPZ

WEZ

WL7

LCAS

Semiconductor Group

HYB3164(5/6)165BT(L)-40/-50/-60

4M x 16 EDO-DRAM

Hyper Page Mode (EDO) Early Write Cycle

RSH

CAS

CRP

RAL

CAH

ASC

CWL

WCS

WCH

CSH

CAS

RCD

RAH

ASR

Column 1

Column 2

Row

Addr

Data In N

Data In 2

Data In 1

Column N

RAS

I/O (Input)

Address

UCAS

VIH

VIL

"H" or "L"

RAS

CRP

ASC

CWL

WCS

WCH

CWL

WCS

WCH

RWL

HPC

CAH

RAD

RHCP

ASC

WL8

LCAS

Semiconductor Group

HYB3164(5/6)165BT(L)-40/-50/-60

4M x 16 EDO-DRAM

Hyper Page Mode (EDO) Late Write Cycle

RSH

CAS

CRP

RAL

CAH

ASC

CSH

CAS

RCD

RAH

ASR

Column 2

Row

Data In

RAS

I/O

Address

UCAS

VIL

VIH

VIL

"H" or "L"

RAS

CRP

ASC

HPC

CAH

RAD

ASC

RCS

(Input)

ODD

Data In

Column N

Column 1

Data In

OEH

RCS

WL16

RCS

CWL

RWL

ODD

OEH

ODD

OEH

LCAS

Semiconductor Group

HYB3164(5/6)165BT(L)-40/-50/-60

4M x 16 EDO-DRAM

Hyper Page Mode (EDO) Read-Modify-Write Cycle

OEA

ASR

ASC

CRP

ASR

ASC

CWL

RWL

OEH

OEZ

OEA

OEZ

OEH

OEA

V OL

r
ess

(
I
np

)

(Ou

t
p

ts)

t
a

l
u

ASP

l
u

WL17

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HYB3166165BT-40