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Электронный компонент: HYB39S64400AT-8B

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Semiconductor Group
1
10.98
HYB39S64400/800/160AT(L)
64MBit Synchronous DRAM
64 MBit Synchronous DRAM
The HYB39S64400/800/160AT are four bank Synchronous DRAM's organized as 4 banks x 4MBit
x4, 4 banks x 2MBit x8 and 4 banks x 1Mbit x16 respectively. These synchronous devices achieve
high speed data transfer rates by employing a chip architecture that prefetches multiple bits and
then synchronizes the output data to a system clock. The chip is fabricated with SIEMENS'
advanced quarter micron 64MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible
depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a
single 3.3V +/- 0.3V power supply and are available in TSOPII packages.
The -8 version of this product is best suited for use on a 100 Mhz bus for both CAS latencies 2 & 3.
High Performance:
Fully Synchronous to Positive Clock Edge
0 to 70
C operating temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2 & 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length: 1, 2, 4, 8
full page (optional) for sequential wrap
around
-8
-8B
-10
Units
fCK
max.
125
100
100
MHz
tCK3
8
10
10
ns
tAC3
6
6
7
ns
tCK2
10
12
15
ns
tAC2
6
7
8
ns
Multiple Burst Read with Single Write
Operation
Automatic and Controlled Precharge
Command
Data Mask for Read / Write control (x4, x8)
Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
4096 refresh cycles / 64 ms
Random Column Address every CLK
( 1-N Rule)
Single 3.3V +/- 0.3V Power Supply
LVTTL Interface version
Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
-8 version for PC100 2-2-2 applications
-8B version for PC100 3-2-3 applications
Semiconductor Group
2
HYB39S64400/800/160AT(L)
64MBit Synchronous DRAM
Ordering Information
Pin Description and Pinouts:
Type
Ordering Code
Package
Description
LVTTL-version:
HYB 39S64400AT-8
P-TSOP-54-2 (400mil)
4B x 4M x 4 SDRAM PC100-222
HYB 39S64400AT-8B
P-TSOP-54-2 (400mil)
4B x 4M x 4 SDRAM PC100-323
HYB 39S64400AT-10
P-TSOP-54-2 (400mil)
4B x 4M x 4 SDRAM PC66-222
HYB 39S64800AT-8
P-TSOP-54-2 (400mil)
4B x 2M x 8 SDRAM PC100-222
HYB 39S64800AT-8B
P-TSOP-54-2 (400mil)
4B x 2M x 8 SDRAM PC100-323
HYB 39S64800AT-10
P-TSOP-54-2 (400mil)
4B x 2M x 8 SDRAM PC66-222
HYB 39S64160AT-8
P-TSOP-54-2 (400mil)
4B x 1M x 16 SDRAM PC100-222
HYB 39S64160AT-8B
P-TSOP-54-2 (400mil)
4B x 1M x 16 SDRAM PC100-323
HYB 39S64160AT-10
P-TSOP-54-2 (400mil)
4B x 1M x 16 SDRAM PC66-222
HYB 39S64xxx0ATL-8/-10
P-TSOP-54-2 (400mil)
Low Power (L-versions)
CLK
Clock Input
DQ
Data Input /Output
CKE
Clock Enable
DQM, LDQM, UDQM
Data Mask
CS
Chip Select
Vdd
Power (+3.3V)
RAS
Row Address Strobe
Vss
Ground
CAS
Column Address Strobe
Vddq
Power for DQ's (+ 3.3V)
WE
Write Enable
Vssq
Ground for DQ's
A0-A11
Address Inputs
NC
not connected
BA0, BA1
Bank Select
Semiconductor Group
3
HYB39S64400/800/160AT(L)
64MBit Synchronous DRAM
Pinout for x4, x8 & x16 organised 64M-SDRAMs
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
VDD
NC
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
VSS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
18
19
20
21
22
23
24
25
26
27
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
VDD
NC
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
VSS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
16M x 4
8M x 8
4M x 16
TSOPII-54 (10.16 mm x 22.22 mm, 0.8 mm pitch)
Semiconductor Group
4
HYB39S64400/800/160AT(L)
64MBit Synchronous DRAM
Block Diagram for 4 bank x 4M x 4 SDRAM
Row decoder
Memory array
Bank 0
4096 x 1024
x 4 bi
t
C
o
l
u
mn de
c
o
der
S
ens
e ampl
i
f
i
e
r &
I(O) bus
Row decoder
Memory array
Bank 1
4096 x 1024
x 4 bi
t
C
o
l
u
mn de
c
o
der
S
e
ns
e ampl
i
f
i
e
r &
I(O) bus
Row decoder
Memory array
Bank 2
4096 x 1024
x 4 bi
t
C
o
l
u
mn de
c
o
der
S
e
ns
e ampl
i
f
i
e
r &
I(O) bus
Row decoder
Memory array
Bank 3
4096 x 1024
x 4 bi
t
C
o
l
u
mn de
c
o
der
S
e
ns
e ampl
i
f
i
e
r &
I(O) bus
Input buffer
Output buffer
DQ0-DQ3
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
A0 - A11, BA0, BA1
A0 - A9, AP, BA0, BA1
Control logic & timing generator
CL
K
CK
E
CS
RA
S
CA
S
WE
DQ
M
Row Addresses
Column Addresses
Semiconductor Group
5
HYB39S64400/800/160AT(L)
64MBit Synchronous DRAM
Block Diagram for 4 banks x 2M x 8 SDRAM
Row decoder
Memory array
Bank 0
4096 x 512
x 8 bi
t
C
o
l
u
mn de
c
o
der
S
ens
e ampl
i
f
i
e
r &
I(O) bus
Row decoder
Memory array
Bank 1
4096 x 512
x 8 bi
t
C
o
l
u
mn de
c
o
der
S
e
ns
e ampl
i
f
i
e
r &
I(O) bus
Row decoder
Memory array
Bank 2
4096 x 512
x 8 bi
t
C
o
l
u
mn de
c
o
der
S
e
ns
e ampl
i
f
i
e
r &
I(O) bus
Row decoder
Memory array
Bank 3
4096 x 512
x 8 bi
t
C
o
l
u
mn de
c
o
der
S
e
ns
e ampl
i
f
i
e
r &
I(O) bus
Input buffer
Output buffer
DQ0-DQ7
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
A0 - A11, BA0, BA1
A0 - A8, AP, BA0, BA1
Control logic & timing generator
CL
K
CK
E
CS
RA
S
CA
S
WE
DQ
M
Row Addresses
Column Addresses