SE4100L
PointChargerTM GPS Receiver IC
Preliminary Information
Applications
Mobile phone & PDA accessories
Portable navigation
Personal security
Security systems
Asset tracking
Telematics equipment
Features
30 mW power consumption
4x4mm 24 pin LPCC package
Single conversion radio with integrated IF filters
On-chip, Gain switchable LNA
Low LNA noise figure, 1.3dB typ.
On chip crystal oscillator can be powered up
independently
Fully integrated VCO, VCO tank circuit and PLL.
Remote antenna current detection
Ordering Information
Type
Package
Remark
SE4100L-R
24 Pin LPCC
Shipped in
Tape & Reel
Product Description
The SE4100 is an integrated GPS receiver designed to
receive the L1 signal at 1575.42MHz. The receiver has
a low IF architecture, and integrates all of the amplifier,
oscillator, mixer and demodulation functions.
The external component count is low, requiring just a
16.368MHz crystal and 11 passive components in its
minimum configuration. This and the 24 pin LPCC
package result in a very small circuit footprint, which is
complemented by just 30mW operating power.
Two digitally controlled shutdown modes enable either
to part to be powered down entirely or for just the 16
MHz clock supply to the baseband processor to be
maintained.
A switchable gain LNA enables the SE4100 to be used
with a local passive antenna or with a remote active
antenna without changing the circuit configuration. The
on-chip VCO and PLL generates the required LO
frequency from the external 16.368MHz crystal. All of
the VCO and LO chain is integrated. An image reject
mixer downconverts the RF signal to a 4.092MHz IF.
The integrated IF filter feeds a combiner, limiter and
output latch. The output signal is a 1-bit quantized
4.092 MHz digital IF at CMOS levels.
Functional Block Diagram
~
~
~
~
Phase
Det.
~
~
~
96
Quadrature
2
I
Q
+45 / -45
~
Q
Clk
D
MixIn
LNA
O
ut
LNAIn
LNA
Xtal1
Xtal2
Os
cE
nb
Xtal
Oscillator
Rx
Enb
VCO
Clk
O
ut
DataOut
Phase
Shift /
Combiner
D-type
IF Filter
Mixers
RF Amp
Vtune
SE4100 Block Diagram
AntDetP
AntDetN
AntOK
Ant current
monitor
LowGain
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SE4100L
PointChargerTM GPS Receiver IC
Preliminary Information
Pin Out Diagram
18
15
17
16
14
13
1
4
2
3
5
6
24
21
23
22
20
19
7
10
8
9
11
12
SE4100L
Bottom View
Vss
2
Mix
I
n
Vcc
R
F
LNA
O
ut
Vcc
V
C
O
Vss
1
R2
R1
Rx
E
n
b
Cl
k
O
ut
R0
Dat
a
O
u
t
LowGain
VccLNA
AntOK
AntDetP
AntDetN
LNAIn
Xtal1
R3
OscEnb
Xtal2
Vtune
V
DD
Die Pad
18
15
17
16
14
13
1
4
2
3
5
6
24
21
23
22
20
19
7
10
8
9
11
12
SE4100L
Top View
Vss
2
Mix
I
n
Vcc
R
F
LNA
O
ut
Vcc
V
C
O
Vss
1
R2
R1
Rx
E
n
b
Cl
k
O
ut
R0
Dat
a
O
u
t
LowGain
VccLNA
AntOK
AntDetP
AntDetN
LNAIn
Xtal1
R3
OscEnb
Xtal2
Vtune
V
DD
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SE4100L
PointChargerTM GPS Receiver IC
Preliminary Information
Pin Out Description
Pin No.
Name
Description
1
VccLNA
Power supply connection for LNA
2
AntDetP
Connection to battery side of antenna current sensing resistor
3
AntDetN
Connection to antenna feed side of antenna current sensing resistor
4 LNAIn
LNA
Input
5
LowGain
LNA Gain control, High = low gain
6
AntOK
Antenna OK output flag (high = antenna current OK)
7 DataOut
Data
Output
8
ClkOut
Buffered version of Xtal Osc output / D-type clock
9 RxEnb
Enable control for Receiver (all circuits except Reference oscillator and Data
Registers), active high input
10
R0
Reserved internal connection, must be tied to V
DD
for normal operation
11
R1
Reserved internal connection, must be tied to V
DD
for normal operation
12
R2
Reserved internal connection, must be tied to V
DD
for normal operation
13
R3
Reserved internal connection, must be tied to V
DD
for normal operation
14
Xtal2
Connection to crystal
15
Xtal1
Connection to crystal
16 V
DD
Power supply for digital circuits (Xtal Oscillator, Data Registers and Bias circuits)
17
Vtune
Charge pump output / VCO control voltage input
18
OscEnb
Enable control for Reference oscillator, active high input
19 V
CC
VCO
Decoupling connection for VCO power supply
20 MixIn
Mixer input signal, 50
single ended
21 V
SS
1 Ground
22 V
CC
RF
Power supply connection for all RF circuits except the LNA
23 V
SS
2 Ground
24 LNAOut
LNA Output, 50
single ended
Die Pad
Gnd
Ground connection for all circuits via die pad
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SE4100L
PointChargerTM GPS Receiver IC
Preliminary Information
Functional Description
LNA
The internal LNA consists of two transistors
cascaded. The biasing, gain switching circuit and
output matching to 50
is contained on the IC. A
conceptual diagram of the internal circuit is shown
below.
Vbias1
Vbias2
VccLNA
LNAOut
LNAIn
Gain
Control
The input match to 50
requires three external
components, two capacitors and an inductor. The
inductor should be a high Q type, e.g. wirewound or
microstrip; otherwise the low noise figure of the LNA
will not be obtained.
The output match is optimized to allow for a short
length of narrow track between the IC package and a
filter. Exact lengths and track widths will depend on
the board material and thickness.
The gain of the amplifier is switched between high
and low settings by the CMOS level compatible
LowGain input pin. Internally, this reduces the gain of
the second stage only in the low gain setting, which
maintains a low noise figure for the amplifier.
The power supply for the amplifier is provided through
the VccLNA pin. Care should be taken with the PCB
layout to ensure that the power supply cannot act as a
bypass around any filter between the LNA output and
the mixer input.
Antenna Current Monitor
The antenna current monitor is a window comparator
designed to operate with common mode input
voltages above the chip V
CC
. It is designed to monitor
the supply current to an external active antenna and
provide a logic output indicating if the current is within
the desired range.
The state of the logic output on the AntOK pin is
dependent on the voltage drop between AntDetP and
AntDetN pins, AntDetP being the higher dc voltage.
The current setting this voltage is adjusted by
changing the value of the external current sense
resistor between these pins.
Voltage
between
AntDetP and
AntDetN (V
ANT
)
Logic Output
AntOK
<0.125 Low
0.25>
V>0.5
High
>0.75 Low
The AntOK pin is a CMOS output designed to
interface directly to the LowGain input pin, so that in
the event the supply to the external active antenna is
either shorted or open circuited, the internal LNA gain
is switched to the high gain setting.
The external current sense resistor should be chosen
according to the typical current of the external
antenna I
ANT
, using the formula:
ANT
EXT
I
0.375
R
=
Mixer RF Input
The mixer RF input pin, MixIn, is a single ended 50
input, designed to either interface to the LNAOut pin
or to the output of an external filter using only a dc
blocking capacitor, and without additional matching
components.
The input is a common base configuration providing a
wideband 50
termination. A conceptual diagram of
the input circuit is shown below:
Vbias1
MixIn
800
0.5mA
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SE4100L
PointChargerTM GPS Receiver IC
Preliminary Information
The filter type chosen should require a termination
impedance of 50+j0
. Examples of suitable types are
shown on the application schematic diagram.
The PCB layout should keep the track from the filter
to the MixIn pin as short as possible to minimize
pickup and mismatch (if the track is not 50
). A dc
blocking capacitor should be used, even if the filter
does not present a dc path, as the MixIn pin has 0.4V
dc present which may be detrimental to the filter.
A filter will improve the performance of the receiver in
the presence of out of band blocking signals, but is
not essential if operation in the presence of such
signals is not critical. If the filter is not fitted, the
LNAOut pin should be connected to the MixIn pin via
a coupling capacitor.
PLL and Loop Filter
The entire phase-locked loop generating the local
oscillator for the mixer is contained on-chip, with the
exception of the loop filter.
Values provided on the application circuit should be
used, as these will provide optimum performance
under all conditions.
The capacitors may be ceramic dielectric types, with
either COG/NP0 or X7R dielectric. Higher
capacitance per unit volume dielectrics should be
avoided as the absolute tolerance and temperature
stability may compromise system performance.
The PCB layout should keep the track from the Vtune
pin to the loop filter as short as possible to minimize
noise pickup.
Crystal Oscillator
The crystal oscillator is a Pierce configuration, as
shown in the diagram below. The application circuit is
designed to work with parallel resonant crystals with a
load capacitance of 12pF.
Xtal2
Xtal1
The PCB layout should minimize the lengths of the
tracks to Xtal1 and Xtal2 pins. The capacitors at each
terminal of the crystal should be mounted adjacent to
the crystal and have a low impedance connection to
the ground plane.
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