Revision 1.0
Subject to Change without Notice
Si
I
140/Si
I
140A
PanelLink
Digital Transmitter
March 1999
General Description
Features
Ideal for LCD desktop monitor applications, the Si
I
140/Si
I
140A
uses PanelLink Digital technology to support displays ranging from VGA
to High Refresh XGA (25-86 MHz). The Si
I
140/Si
I
140A transmitter
supports up to true color panels (24 bit/pixel, 16.7M colors) in 1
pixel/clock mode and also features an inter-pair skew tolerance up to 1
full input clock cycle and a highly jitter tolerant PLL design. Since all
PanelLink products are designed on scaleable CMOS architecture to
support future performance requirements while maintaining the same
logical interface, system designers can be assured that the interface will
be fixed through a number of technology and performance generations.
PanelLink Digital technology simplifies PC design by resolving many
of the system level issues associated with high-speed digital design,
providing the system designer with a digital interface solution that is
quicker to market and lower in cost.
High Bandwidth: 25-86 MHz (VGA to High Refresh SXGA)
Low Power: 3.3V core operation & power-down mode
High Skew Tolerance: 1 full input clock cycle (15ns at 65
MHz)
Pin-compatible with Si
I
100
Sync Detect: for Plug & Display "Hot Plugging"
Cable Distant Support: over 5m with twisted-pair, fiber-
optics ready
Compliant with DVI 1.0 (DVI is backwards compatible with
VESA P&D
TM
and DFP)
Si
I
140/Si
I
140A Pin Diagram
Functional Block Diagram
Data
Capture
Logic
Encoder
0
D[7:0]
D[15:8]
D[23:16]
DE0
DE1
DE2
HSYNC
VSYNC
PLL_SYNC
CTL1
CTL2
CTL3
TX0
D[23:0]
DE
HSYNC
VSYNC
CTL1
CTL2
CTL3
DEDGE
CEDGE
Encoder
0
Encoder
0
TX0+
TX0-
TXC+
TXC-
IDCK
Swing
Control
EXT_SWING
10
10
10
24
PLL
TX1
TX1+
TX1-
TX2
TX2+
TX2-
TXC
DE
1
SiI140/SiI140A
64-Pin TQFP
(Top View)
HSYNC
2
VSYNC
3
GND
4
RESERVED
5
CTL1
6
CTL2
7
CTL3
8
DEDGE
9
VCC
10
CEDGE
11
IDCK
12
RESERVED
13
RESERVED
14
RESERVED
15
GND
16
PGND
17
PVCC
18
AGND
19
TXC-
20
TXC+
21
AVCC
22
TX0-
23
TX0+
24
AGND
25
TX1-
26
TX1+
27
AVCC
28
TX2-
29
TX2+
30
AGND
31
48
D15
47
D16
46
GND
45
D17
44
D18
43
D19
42
D20
41
D21
40
VCC
39
D22
38
D23
37
PLL_SYNC
36
PD
35
RESERVED
34
EXT_SWING
33
D14
GND
64
D0
63
D1
62
D2
61
D3
60
D4
59
D5
58
D6
57
D7
56
D8
55
D9
54
IVCC
53
D10
52
D11
51
D12
50
D13
49
8-bit Channel 0 Data
24-bit INPUT DATA
DIFFERENTIAL SIGNAL
VCC
32
8-bit Channel 1 Data
8-bit Channel 2 Data
CONTROL
GENERAL
PURPOSE
CONTROL
MISC.
MISC.
PLL
Silicon Image, Inc.
SiI140/SiI140A
SiI/DS-0003-D
Revision 1.0
2
Subject to Change without Notice
Absolute Maximum Conditions
Note: Permanent device damage may occur if absolute maximum conditions are exceeded.
Functional operation should be restricted to the conditions described under Normal Operating Conditions.
Symbol
Parameter
Min
Max
Units
V
CC
Supply Voltage 3.3V
-0.3
4.0
V
V
I
Input Voltage
-0.3
V
CC
+ 0.3
V
V
O
Output Voltage
-0.3
V
CC
+ 0.3
V
T
A
Ambient Temperature (with power applied)
-25
105
C
T
STG
Storage Temperature
-40
125
C
P
PD
Package Power Dissipation
1
W
Normal Operating Conditions
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Core Supply Voltage
applies to VCC, AVCC, PVCC
3.00
3.3
3.6
V
V
CCN
Supply Voltage Noise
100
mV
P-P
T
A
Ambient Temperature (with power applied)
0
25
70
C
Note:
1
Guaranteed by design.
DC Digital I/O Specifications
Under normal operating conditions unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
IH
High-level Input Voltage
2
V
V
IL
Low-level Input Voltage
0.8
V
V
OH
High-level Output Voltage
2.4
V
V
OL
Low-level Output Voltage
0.4
V
V
CINL
Input Clamp Voltage
1
I
CL
= -18mA
GND -0.8
V
V
CIPL
Input Clamp Voltage
1
I
CL
= 18mA
IVCC + 0.8
V
V
CONL
Output Clamp Voltage
1
I
CL
= -18mA
GND -0.8
V
V
COPL
Output Clamp Voltage
1
I
CL
= 18mA
OVCC + 0.8
V
I
IL
Input Leakage Current
-10
10
A
Note:
1
Guaranteed by design.
DC Specifications
Under normal operating conditions unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
OD
Differential Voltage
Single ended peak to peak amplitude
R
LOAD
= 50
R
EXT_SWING
= 850
R
EXT_SWING
= 680
R
EXT_SWING
= 400
250
310
580
300
370
650
350
430
720
mV
mV
mV
V
DOH
Differential High-level Output Voltage
AVCC
V
I
DOS
Differential Short Circuit Current
V
OUT
= 0 V
5
A
I
PD
Power-down Current
3
25
A
I
CCT
Transmitter Supply Current
IDCK = 86 MHz
R
EXT_SWING
= 680
Typical Pattern
1
52
65
mA
DCLK = 86 MHz
R
EXT_SWING
= 680
Worst Case Pattern
2
56
68
mA
Notes:
1
The Typical Pattern contains a gray scale area, checkerboard area, and text.
2
Black and white checkerboard pattern, each checker is one pixel wide.
3
The value shown assumes the digital inputs to the Si
I
140/Si
I
140A are not toggling.
Silicon Image, Inc.
SiI140/SiI140A
SiI/DS-0003-D
Revision 1.0
3
Subject to Change without Notice
AC Specifications
Under normal operating conditions unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
T
CIP
IDCK Period
11.6
50
ns
F
CIP
IDCK Frequency
20
86
MHz
T
CIH
IDCK High Time @ 86 MHz
3.7
ns
T
CIL
IDCK Low Time @ 86 MHz
3.3
ns
T
IJIT
Worst Case IDCK Clock Jitter
2,3
2
ns
T
SIDF
Data/Control Setup Time to IDCK falling
CEDGE, DEDGE = 0
1
ns
T
HIDF
Data/Control Hold Time to IDCK falling
CEDGE, DEDGE = 0
2.6
ns
T
SIDR
Data/Control Setup Time to IDCK rising
1
CEDGE, DEDGE = 1
2
ns
T
HIDR
Data/Control Hold Time to IDCK rising
1
CEDGE, DEDGE = 1
3
ns
T
DDF
VSYNC, HSYNC, and CTL[3:1] Delay from DE falling edge
T
CIP
ns
T
DDR
VSYNC, HSYNC, and CTL[3:1] Delay from DE rising edge
T
CIP
ns
T
LDE
DE low time
10T
CIP
ns
S
LHT
Small Swing Low-to-High Transition Time
C
LOAD
= 5pF
R
LOAD
= 50
R
EXT_SWING
= 680
0.25
0.3
0.5
ns
S
HLT
Small Swing High-to-Low Transition Time
C
LOAD
= 5pF
R
LOAD
= 50
R
EXT_SWING
= 680
0.25
0.3
0.5
ns
Notes:
1
Guaranteed by design.
2
Jitter can be estimated by: 1) triggering a digital scope at the rising of input clock, and 2) measuring the peak to peak time
spread of the rising edge of the input clock 1
s after the trigger.
3
Actual jitter tolerance may be higher depending on the frequency of the jitter.
Timing Diagrams
Figure 1. Clock Cycle/High/Low Times
Figure 2. Small Swing Transition Times
T
CIH
T
CIL
T
CIP
V
IH
V
IH
V
IL
V
IL
S
LHT
20% V
OD
80% V
OD
S
HLT
Silicon Image, Inc.
SiI140/SiI140A
SiI/DS-0003-D
Revision 1.0
4
Subject to Change without Notice
Input Timing
Figure 2. Input Data Setup/Hold Times to IDCK
Figure 3. VSYNC, HSYNC, and CTL[3:1] Delay Times from DE
Figure 4. DE High/Low Times
Input Pin Description
Pin Name
Pin #
Type
Description
D23 D0
See
In
Input Data is [23:0].
Si
I
140/
Input data is synchronized with input data clock (IDCK).
Si
I
140A
Pin
Diagram
Refer to the TFT Signal Mapping (Si
I
/AN-0007-A) and DSTN Signal Mapping (Si
I
/AN-
0008-A) application notes which tabulate the relationship between the input data to the
transmitter and output data from the receiver.
IDCK
12
In
Input Data Clock. Input data can be valid either on the falling or on the rising edge of
IDCK as selected by DEDGE pin.
DE
1
In
Input Data Enable. This signal qualifies the active data period. DE is always required by
the Si
I
140/Si
I
140A and must be high during active display time and low during blank
time.
HSYNC
2
In
Horizontal Sync input control signal.
VSYNC
3
In
Vertical Sync input control signal.
CTL1
6
In
General input control signal 1.
CTL2
7
In
General input control signal 2
CTL3
8
In
General input control signal 3.
Configuration Pin Description
Pin Name
Pin #
Type
Description
DEDGE
9
In
Data Latching Edge. A low level indicates that input data (D[23:0]) will be latched on the falling edge of IDCK
while a high level (3.3V) indicates that input data will be latched on the rising edge of IDCK.
CEDGE
11
In
Control Latching Edge. Controls latching edge of control signals DE, HSYNC, VSYNC, and CTL[3:1]. A low
level indicates that input data enable and control signals will be latched on the falling edge of IDCK, while a
high level (3.3V) indicates that input data enable and control signals will be latched on rising edge of IDCK.
Power Management Pin Description
Pin Name
Pin #
Type
Description
PD
35
In
Power Down (active low). A high level (3.3V) indicates normal operation and a low
level indicates power down mode. During power down mode, all data and control
inputs are disabled and most internal logic is powered down.
D[23:0], DE,
HSYNC,VSYNC,
CTL[3:1]
IDCK
T
SIDF
T
HIDF
T
SIDR
T
HIDR
V
IL
V
IL
V
IH
V
IL
V
IH
V
IH
V
IH
V
IL
T
DDR
T
DDF
DE
VSYNC, HSYNC,
CTL[3:1]
V
IL
V
IL
V
IL
V
IL
DE
VSYNC, HSYNC,
CTL[3:1]
DE
T
HDE
T
LDE
V
IL
V
IH
V
IL
V
IH
Silicon Image, Inc.
SiI140/SiI140A
SiI/DS-0003-D
Revision 1.0
5
Subject to Change without Notice
Differential Signal Data Pin Description
Pin Name
Pin #
Type
Description
TX0+
24
Analog
Low Voltage Differential Signal output data pairs.
TX0-
23
Analog
TX1+
27
Analog
TX1-
26
Analog
TX2+
30
Analog
TX2-
29
Analog
TXC+
21
Analog
Low Voltage Differential Signal output clock pair.
TXC-
20
Analog
EXT_
SWING
33
Analog
Voltage Swing Adjust. A resistor should tie this pin to AVCC. The amplitude of the
voltage swing is determined by this resistance. For remote display applications,
400
is recommended. For laptop computers, 680
is recommended.
Reserved Pin Description
Pin Name
Pin #
Type
Description
RSVD
5
In
This pin must be tied high, low, or left unconnected. It also may be
connected to pin 36 for backward compatibility with the Si
I
100.
RSVD
13
In
This pin must be tied high.
RSVD
14
In
This pin must be tied high.
RSVD
15
In
This pin must be left unconnected.
RSVD
34
In
This pin must be tied high, low, or left unconnected.
Power and Ground Pin Description
Pin Name
Pin #
Type
Description
VCC
10
Power
Core VCC, must be set to 3.3V.
32
39
IVCC
53
Power
Input VCC, must be set to 3.3V.
GND
4
Ground
Digital GND.
16
45
64
AVCC
22
Power
Analog VCC, must be set to 3.3V.
28
AGND
19
Ground
Analog GND.
25
31
PVCC
18
Power
PLL VCC, must be set to 3.3V.
PGND
17
Ground
PLL GND.
Application Information
To obtain the most updated Application Notes and other useful information for your design application, please visit
the Silicon Image web site at www.siimage.com, or contact your local Silicon Image sales office.
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