Preliminary Rev. 0.4 5/06

Si534

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si534

R Y S TA L

S C I L L A T O R

(XO)

(10 MH

T O

1.4 GH

)

Features

Applications

Description

The Si534 quad frequency XO utilizes Silicon Laboratories' advanced
DSPLL

circuitry to provide a low jitter clock at high frequencies. The Si534

is available with any-rate output frequency from 10 to 945 MHz and select
frequencies to 1400 MHz. Unlike a traditional XO where a different crystal is
required for each output frequency, the Si534 uses one fixed crystal to
provide a wide range of output frequencies. This IC based approach allows
the crystal resonator to provide exceptional frequency stability and reliability.
In addition, DSPLL clock synthesis provides superior supply noise rejection,
simplifying the task of generating low jitter clocks in noisy environments
typically found in communication systems. The Si534 IC-based XO is factory
configurable for a wide variety of user specifications including frequency,
supply voltage, output format, and temperature stability. Specific
configurations are factory programmed at time of shipment, thereby
eliminating long lead times associated with custom oscillators.

Functional Block Diagram

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

Four selectable output frequencies
3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

SONET/SDH
Networking
SD/HD video

Clock and data recovery
FPGA/ASIC clock generation

Fixed

Frequency

Any-rate

101400 MHz

DSPLL

Clock

Synthesis

CLK+

CLK

GND

FS[1]

FS[0]

Ordering Information:

See page 6.

Pin Assignments:

See page 5.

(Top View)

Si5602

(LVDS/LVPECL/CML)

(CMOS)

GND

CLK+

CLK

FS[1]

FS[0]

GND

CLK

FS[1]

FS[0]

R E L I M I N A R Y

A TA

H E E T

Si534

Preliminary Rev. 0.4

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Supply Voltage

3.3 V option

2.97

3.3

3.63

2.5 V option

2.25

2.5

2.75

1.8 V option

1.71

1.8

1.89

Supply Current

Output enabled

TriState mode

Output Enable (OE)

0.75 x V

0.5

Operating Temperature Range

ºC

Notes:

1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 6 for further details.
2. OE pin includes a 17 k

pullup resistor to V

. Pulling OE to ground causes outputs to tristate.

Table 2. CLK± Output Frequency Characteristics

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Nominal Frequency

1,2

LVPECL/LVDS/CML

945

MHz

CMOS

160

Initial Accuracy

Measured at +25 °C at

time of shipping

±1.5

ppm

Temperature Stability

1,3

f/f

20
50

--
--

+20
+50

ppm

Aging f

Frequency drift over pro-

jected 15 year life

±10

ppm

Powerup Time

OSC

Settling Time After FS[1:0] Change

FRQ

Both FS[1] and FS[0]

changing simultaneously

Notes:

1. See Section 3. "Ordering Information" on page 6 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Selectable parameter specified by part number.
4. Time from powerup or tristate mode to f

Si534

Preliminary Rev. 0.4

Table 3. CLK± Output Levels and Symmetry

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

LVPECL Output Option

mid-level

1.42

1.25

swing (diff)

1.1

1.9

swing (single-ended)

0.5

0.93

LVDS Output Option

mid-level

1.125

1.20

1.275

swing (diff)

0.32

0.40

0.50

CML Output Option

mid-level

0.75

swing (diff)

0.70

0.95

1.20

CMOS Output Option

= 32 mA

0.8 x V

= 32 mA

0.4

Rise/Fall time (20/80%)

LVPECL/LVDS/CML

350

CMOS with CL = 15 pF

Symmetry (duty cycle)

SYM

LVPECL:

1.3 V (diff)

LVDS:

1.25 V (diff)

CMOS:

Notes:

1. 50

to V

2.0 V.

2. R

term

= 100

(differential).

3. C

= 15 pF

Table 4. CLK± Output Phase Jitter

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Phase Jitter (RMS)*
for F

OUT

> 500 MHz

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

--
--

0.27
0.30

--
--

Phase Jitter (RMS)*
for F

OUT

of 125 to 500 MHz

12 kHz to 20 MHz (OC-48)

0.50

*Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information.

Table 5. CLK± Output Period Jitter

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Period Jitter*
for F

OUT

< 160 MHz

PER

RMS

Peak-to-Peak

*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles.

Si534

Preliminary Rev. 0.4

Table 6. CLK± Output Phase Noise (Typical)

Configuration

Output

81.25 MHz

LVDS

312.5 MHz

LVPECL

1066 MHz

LVPECL

Units

Offest Frequency (f)

100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
100 MHz

L (f)

dBc/Hz

110

127
134
136
143
147

n/a

100

115
119

123
135
144
147

102
107

111

121
135
142

Table 7. Absolute Maximum Ratings

Parameter

Symbol

Rating

Units

Supply Voltage

0.5 to +3.8

Volts

Input Voltage (any input pin)

0.5 to V

+ 0.3

Volts

Storage Temperature

55 to +125

ºC

ESD Sensitivity (HBM, per JESD22-A114)

ESD

>2500

Volts

Soldering Temperature (Pb-free profile)

PEAK

260

ºC

Soldering Temperature Time @ T

PEAK

(Pb-free profile)

seconds

Notes:

1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional

operation or specification compliance is not implied at these conditions.

2. Refer to Si5xx Packaging FAQ available for download at

www.silabs.com/VCXO

for further information, including

soldering profiles.

Table 8. Environmental Compliance

The Si534 meets the following qualification test requirements.

Parameter

Conditions/ Test Method

Mechanical Shock

MIL-STD-883F, Method 2002.3 B

Mechanical Vibration

MIL-STD-883F, Method 2007.3 A

Solderability

MIL-STD-883F, Method 203.8

Gross & Fine Leak

MIL-STD-883F, Method 1014.7

Resistance to Solvents

MIL-STD-883F, Method 2016

Si534

Preliminary Rev. 0.4

2. Pin Descriptions

Table 9. Pin Descriptions

Pin

Symbol

LVDS/LVPECL/CML Function

CMOS Function

No connection

OE*

Output enable

0 = clock output disabled (outputs tristated)

1 = clock output enabled

Output enable

0 = clock output disabled (outputs tristated)

1 = clock output enabled

GND

Electrical and Case Ground

CLK+

Oscillator Output

CLK

Complementary output

No connection

Power Supply Voltage

FS[1]*

Frequency Select MSB

FS[0]*

Frequency Select LSB

*Note: FS[1:0] and OE include a 17 k

pullup resistor to V

. See Section "Ordering Information" for details on frequency

value ordering.

(Top View)

LVDS/LVPECL/CML

CMOS

GND

CLK+

CLK

FS[1]

FS[0]

GND

CLK

FS[1]

FS[0]

Si534

Preliminary Rev. 0.4

3. Ordering Information

The Si534 XO was designed to support a variety of options including frequency, temperature stability, output
format, and V

. Specific device configurations are programmed into the Si534 at time of shipment. Configurations

can be specified using the Part Number Configuration chart below. Silicon Laboratories provides a web browser-
based part number configuration utility to simplify this process. Refer to

www.silabs.com/VCXOPartNumber

access this tool and for further ordering instructions. The Si534 is supplied in an industry-standard, RoHS
compliant, 6-pad, 5 x 7 mm package.

Figure 1. Part Number Convention

Example Part Number: 534AB000108BGR is a 5 x 7 mm quad XO in a 8 pad package. Since the six digit code (000108) is >
000100, f0 is 644.53125 MHz (lower frequency) and f1 is 693.48299 (higher frequency), with a 3.3 V supply and LVPECL output.
Temperature stability is specified as ± 20 ppm. The part is specified for a 40 to +85 C° ambient temperature range operation and is
shipped in tape and reel format.

R = Tape & Reel
Blank = Trays

Operating Temp Range (°C)

40 to +85 °C

Device Revision Letter

Option Code

Code Temperature Stability (ppm, max, ±)
A

534 Quad XO

Product Family

Option Code

Code

VDD

Output Format

3.3

LVPECL

3.3

LVDS

3.3

CMOS

3.3

CML

2.5

LVPECL

2.5

LVDS

2.5

CMOS

2.5

CML

1.8

CMOS

1.8

CML

Note:
CMOS available to 160 MHz.

6-digit Frequency Designator Code

Four unique frequencies can be specified within the following bands of frequencies: 10 to
945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz. A six digit code will be assigned for
the specified combination of frequencies. Codes > 000100 refer to quad XOs
programmed with the lowest frequency value selected when FS[1:0] = 00, and the highest
value when FS[1:0] = 11. Six digit codes < 000100 refer to quad XOs programmed with
the highest frequency value selected when FS[1:0] = 00, and the lowest value when
FS[1:0] = 11.

534

XXXXXX

Si534

Preliminary Rev. 0.4

4. Outline Diagram and Suggested Pad Layout

Figure 2 illustrates the package details for the Si534. Table 10 lists the values for the dimensions shown in the
illustration.

Figure 2. Si534 Outline Diagram

Table 10. Package Diagram Dimensions (mm)

Dimension

Min

Nom

Max

1.45

1.65

1.85

1.2

1.4

1.6

0.60 TYP

0.97

1.17

1.37

7.00 BSC

6.10

6.2

6.30

2.54 BSC

5.00 BSC

4.30

4.40

4.50

1.07

1.27

1.47

0.8

1.0

1.2

1.815 BSC

0.7 REF

aaa

0.15

bbb

0.15

ccc

0.10

ddd

0.10

Si534

Preliminary Rev. 0.4

5. 8-Pin PCB Land Pattern

Figure 3 illustrates the 8-pin PCB land pattern for the Si554. Table 11 lists the values for the dimensions shown in
the illustration.

Figure 3. Si534 PCB Land Pattern

Table 11. PCB Land Pettern Dimensions (mm)

Dimension

Min

Max

5.08 REF

5.705 REF

2.54 BSC

4.20 REF

0.84

2.00

8.20 REF

7.30 REF

1.70 TYP

1.545 TYP

2.15 REF

1.3 REF

6.78

6.30

Note:

1. Dimensioning and tolerancing per the ANSI Y14.5M-1994

specification.

2. Land pattern design follows IPC-7351 guidelines.
3. All dimensions shown are at maximum material condition

(MMC).

4. Controlling dimension is in millimeters (mm).

Si534

Preliminary Rev. 0.4

ONTACT

NFORMATION

Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: VCXOinfo@silabs.com
Internet: www.silabs.com

Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 534JAXXXXXXBG

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 534JAXXXXXXBG