Precision Mixed Signal
Copyright 2004 by Silicon Laboratories
6.15.2004
Port 0
Latch
Port 1
Latch
JTAG
Logic
TCK
TMS
TDI
TDO
UART
SMBus
SPI Bus
5-Chnl
PCA
32 kB
FLASH
VDD
Monitor
SFR Bus
Port 2
Latch
Port 3
Latch
8
0
5
1
C
o
r
e
Timers
0,1,2
Timer 3
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P
1
D
r
v
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P
0
D
r
v
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P
3
D
r
v
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P
2
D
r
v
C
R
O
S
S
B
A
R
S
W
I
T
C
H
AV+
AV+
VDD
VDD
VDD
DGND
DGND
DGND
AGND
AGND
Reset
RST
XTAL1
XTAL2
External
Oscillator
Circuit
System Clock
Internal
Oscillator
Digital Power
Analog Power
Debug HW
Boundary Scan
256 Byte
RAM
WDT
DAC1
DAC1
(12-Bit)
DAC0
(12-Bit)
ADC
100 ksps
(10-Bit)
A
M
U
X
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
DAC0
CP0+
CP0-
CP1+
CP1-
TEMP
SENSOR
VREF
Prog
Gain
CP0
CP1
VREF
C8051F010
20 MIPS, 32 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU
Analog Peripherals
10-Bit ADC
-
1 LSB INL; no missing codes
-
Programmable throughput up to 100 ksps
-
8 external inputs; programmable as single-ended or differential
-
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
-
Data-dependent windowed interrupt generator
-
Built-in temperature sensor (3 C)
Two 12-Bit DACs
-
Voltage output
-
10 sec settling time
Two Comparators
-
16 programmable hysteresis values
-
Configurable to generate interrupts or reset
Internal Voltage Reference
V
DD
Monitor/Brown-out Detector
On-Chip JTAG Debug
-
On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit
emulation
-
Supports breakpoints, single stepping, watchpoints, inspect/modify
memory, and registers
-
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
-
Fully compliant with IEEE 1149.1 specification
High-Speed 8051 C Core
-
Pipelined instruction architecture; executes 70% of Instructions in 1 or 2
system clocks
-
Up to 20 MIPS throughput with 20 MHz clock
-
Expanded interrupt handler; up to 21 interrupt sources
Memory
-
256 bytes data RAM
-
32 kB Flash; in-system programmable in 512-byte sectors (512 bytes
are reserved)
Digital Peripherals
-
32 port I/O; all are 5 V tolerant
-
Hardware SMBusTM (I2CTM compatible), SPITM, and UART serial ports
available concurrently
-
Programmable 16-bit counter/timer array with five capture/compare
modules
-
4 general-purpose 16-bit counter/timers
-
Dedicated watchdog timer; bidirectional reset
Clock Sources
-
Internal programmable oscillator: 216 MHz
-
External oscillator: Crystal, RC, C, or Clock
-
Can switch between clock sources on-the-fly
Supply Voltage: 2.7 to 3.6 V
-
Typical operating current: 10 mA at 20 MHz
-
Multiple power saving sleep and shutdown modes
64-Pin TQFP
Temperature Range: 40 to +85 C
Precision Mixed Signal
Copyright 2004 by Silicon Laboratories
6.15.2004
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders
C8051F010
20 MIPS, 32 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU
Selected Electrical Specifications
(T
A
= 40 to +85 C, V
DD
= 2.7 V unless otherwise specified)
PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
GLOBAL CHARACTERISTICS
Analog Supply Voltage
2.7
3.6
V
Analog Supply Current
Internal REF, ADC, DAC, Comparators all
active
0.8 mA
Analog Supply Current with
analog sub-systems inactive
Internal REF, ADC, DAC, Comparators all
disabled
5
A
Digital Supply Voltage
2.7
3.6
V
Digital Supply Current with
CPU active
Clock = 20 MHz
Clock = 1 MHz
Clock = 32 kHz
10
0.5
20
mA
mA
A
Digital Supply Current
(shutdown mode)
Oscillator not running
2
A
V
DD
Data Retention Voltage
RAM remains valid
1.5
V
CPU & DIGITAL I/O
Clock Frequency Range
DC
20
MHz
Port Output High Voltage
I
OH
= 3 mA, Port I/O push-pull
V
DD
0.7
V
Port Output Low Voltage
I
OL
= 8.5 mA
0.6
V
Input High Voltage
0.8 x V
DD
V
Input Low Voltage
0.2 x V
DD
V
SMBus SCL Frequency
SYSCLK = MCU system clock
SYSCLK/8
MHz
SPI Bus Clock Frequency
SYSCLK = MCU system clock
SYSCLK/2
MHz
A/D CONVERTER
Resolution
10
bits
Integral Nonlinearity
1
LSB
Differential Nonlinearity
Guaranteed Monotonic
1
LSB
Throughput Rate
100
ksps
Input Voltage Range
0
V
REF
V
D/A CONVERTERS
Resolution
12
bits
Integral Nonlinearity
Specified from Data Word 014h to FEBh
4
LSB
Differential Nonlinearity
Guaranteed Monotonic
1
LSB
Offset Error
Data Word = 014h
3
LSB
Output Settling Time
To LSB of full-scale
10
s
Output Voltage Swing
0
V
REF
1 LSB
V
COMPARATORS
Supply
Current
(each
Comparator)
1.5 A
Response Time
| (CP+) (CP-) | = 100 mV
4
s
Input Voltage Range
0.25
(AV+) +0.25
V
Input Bias Current
5
0.001
+5
nA
Input Offset Voltage
10
+10
mV
Package Information
A
A1
A2
b
D
D1
e
E
E1
-
0.05
0.95
0.17
-
-
-
-
-
-
-
-
0.22
12.00
10.00
0.50
12.00
10.00
1.20
0.15
1.05
0.27
-
-
-
-
-
MIN
(mm)
NOM
(mm)
MAX
(mm)
1
64
E
E1
e
A1
b
D
D1
PIN 1
DESIGNATOR
A2
A
C8051F005DK Development Kit
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