Rev. 1.2 2/06

Si3220/25

U A L

R O

SLIC

R O G R A M M A B L E

CMOS SLIC/C

O D E C

Features

Applications

Description

The Dual ProSLIC

is a series of low-voltage CMOS devices that integrate both

SLIC and codec functionality into a single IC to provide a complete dual-channel

analog telephone interface in accordance with all relevant LSSGR, ITU, and ETSI

specifications. The Si3220 includes internal ringing generation to eliminate

centralized ringers and ringing relays, and the Si3225 supports centralized ringing

for long loop and legacy applications. On-chip subscriber loop and audio testing

allows remote diagnostics and fault detection with no external test equipment or

relays. The Si3220 and Si3225 operate from a single 3.3 or 5 V supply and

interface to standard PCM/SPI or GCI bus digital interfaces. The Si3200 linefeed

interface IC performs all high-voltage functions and operates from a 3.3 V or 5 V

supply as well as single or dual battery supplies up to 100 V. The Si3220 and

Si3225 are available in a 64-pin thin quad flat package (TQFP), and the Si3200 is

available in a thermally-enhanced 16-pin small outline (SOIC) package.

Functional Block Diagram

Performs all BORSCHT functions
Ideal for applications up to 18 kft
Internal balanced ringing to 65 V

rms

(Si3220)
External bulk ringer support (Si3225)
Software-programmable parameters:

Ringing frequency, amplitude, cadence,
and waveshape (Si3220)

Two-wire ac impedance

Transhybrid balance

DC current loop feed (1845 mA)

Loop closure and ring trip thresholds

Ground key detect threshold

Automatic switching of up to three battery
supplies
On-hook transmission

Loop or ground start operation with
smooth/abrupt polarity reversal
Modem/fax tone detection
DTMF generation/decoding
Dual tone generators
A-Law/µ-Law, linear PCM
companding
PCM and SPI bus digital interfaces
with programmable interrupts
GCI mode support
3.3 or 5 V operation
GR-909 loop diagnostics
Audio diagnostics with loopback
12 kHz/16 kHz pulse metering
(Si3220)
FSK caller ID generation
Lead-free/RoHS-compliant

Digital loop carriers

Central Office telephony

Pair gain remote terminals

Wireless local loop

Private Branch Exchange (PBX) systems

Cable telephony

Voice over IP/voice over DSL

ISDN terminal adapters

text

DAC

ADC

Linefeed

Control

Linefeed

Monitor

DAC

ADC

Linefeed

Control

Linefeed

Monitor

SLIC A

SLIC B

Codec A

Codec B

DSP

SPI

Control

Interface

PCM /

GCI

Interface

PLL

Si3220/25

Linefeed
Interface

2-Wire AC

Impedance

Hybrid Balance

Pulse Metering

Subscriber Line

Diagnostics

DTMF Decode

Programmable

Audio Filters

Gain Adjust

Dual Tone

Generators

Modem Tone

Detection

Ringing

Generator

& Ring Trip

Sense

Loop Closure,
& Ground Key

Detection

FSK

Caller ID

Relay Drivers

SCLK

SDO

SDI

DTX

DRX

FSYNC

INT RESET

PCLK

TIP

Channel A

RING

TIP

RING

Channel B

U.S. Patent #6,567,521
U.S. Patent #6,812,744
Other patents pending

Ordering Information

See "Dual ProSLIC Selection

Guide" on page 109.

Part Number

Ringing

Method

Si3220

Internal

Si3225

External

Ringer

Si3220/25

Rev. 1.2

A B L E

O F

O N T E N TS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3.1. Dual ProSLIC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.2. Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.3. DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.4. Adaptive Linefeed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.5. Ground Start Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.6. Linefeed Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.7. Loop Voltage and Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.8. Power Monitoring and Power Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.9. Automatic Dual Battery Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3.10. Loop Closure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
3.11. Ground Key Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
3.12. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.13. Internal Unbalanced Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.14. Ringing Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
3.15. Ring Trip Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.16. Relay Driver Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
3.17. Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.18. Two-Wire Impedance Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.19. Transhybrid Balance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
3.20. Tone Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
3.21. Caller ID Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
3.22. Pulse Metering Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
3.23. DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
3.24. Modem Tone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
3.25. Audio Path Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
3.26. System Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
3.27. Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
3.28. SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
3.29. PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
3.30. PCM Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
3.31. General Circuit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
3.32. System Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

4. Pin Descriptions: Si3220/25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
5. Pin Descriptions: Si3200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
6. Package Outline: 64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
7. Package Outline: 16-Pin ESOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
8. Silicon Labs Si3220/25 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
9. Dual ProSLIC Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

Si3220/25

Rev. 1.2

1. Electrical Specifications

Table 1. Absolute Maximum Ratings and Thermal Information

Parameter

Symbol

Test

Condition

Value

Unit

Supply Voltage, Si3200 and Si3220/Si3225

, V

DD1

DD4

0.5 to 6.0

High Battery Supply Voltage, Si3200

BATH

Continuous

0.4 to 104

10 ms

0.4 to 109

Low Battery Supply Voltage, Si3200

BAT

BATL

Continuous

BATH

TIP or RING Voltage, Si3205

TIP

RING

Continuous

Pulse < 10 µs

Pulse < 4 µs

104

BATH

TIP, RING Current, Si3200

TIP

, I

RING

±100

STIPAC, STIPDC, SRINGAC, SRINGDC Current,
Si3220/Si3225

±20

Input Current, Digital Input Pins

Continuous

±10

Si3220/25 Analog Ground Differential Voltage
(GND1 to ePad, GND2 to ePad, or GND1 to GND2)

GNDA

±50

Si3220/25 Digital Ground Differential Voltage (GND3
to GND4)

GNDD

±50

Si3220/25 Analog to Digital Ground Differential Volt-
age (GND1/GND2/ePad to GND3/GND4)

GND,AD

±200

Digital Input Voltage

IND

0.3 to (

DDD

+ 0.3)

Operating Temperature Range

40 to 100

°C

Storage Temperature Range

STG

40 to 150

°C

Si3220/Si3225 Thermal Resistance,
Typical

(TQFP-64 ePad)

°C/W

Si3200 Thermal Resistance, Typical

(SOIC-16 ePad)

°C/W

Continuous Power Dissipation, Si3200

= 85 °C,

SOIC-16

Continuous Power Dissipation, Si3220/25

= 85 °C,

TQFP-64

1.6

Notes:

1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be

restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

2. The dv/dt of the voltage applied to the V

BAT

, V

BATH

, and V

BATL

pins must be limited to 10 V/µs.

3. The PCB pad placed under the device package must be connected with multiple vias to the PCB ground layer and to the

GND1-GND4 pins via short traces. The TQFP-64 e-Pad must be properly soldered to the PCB pad during PCB
assembly. This type of low-impedance grounding arrangement is necessary to ensure that maximum differentials are not
exceeded under any operating condition in addition to providing thermal dissipation.

4. The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout

guidelines are followed correctly. The specified performance requires that the exposed pad be soldered to an exposed
copper surface of equal size and that multiple vias are added to enable heat transfer between the top-side copper
surface and a large internal copper ground plane. Refer to "AN55: Dual ProSLIC

User Guide" or to the Si3220/3225

evaluation board data sheet for specific layout examples.

5. On-chip thermal limiting circuitry will shut down the circuit at a junction temperature of approximately 150 °C. For optimal

reliability, junction temperatures above 140 °C should be avoided.

Si3220/25

Rev. 1.2

Table 2. Recommended Operating Conditions

Parameter

Symbol

Test

Condition

Min*

Typ

Max*

Unit

Ambient Temperature

K/F-Grade

Ambient Temperature

B/G-Grade

Supply Voltage, Si3220/Si3225

DD1

DD4

3.13

3.3/5.0

5.25

Supply Voltage, Si3200

3.13 3.3/5.0

5.25

High Battery Supply Voltage, Si3200

BATH

Low Battery Supply Voltage, Si3200

BATL

BATH

*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.

Table 3. 3.3 V Power Supply Characteristics

, V

DD1

DD4

3.3 V, T

0 to 70 °C for K/F-Grade, 40 to 85 °C for B/G-Grade)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

DD1

DD4

Supply

Current (Si3220/
Si3225)

VDD1

VDD4

Sleep mode, RESET = 0

200

µA

Open (high-impedance)

Active on-hook standby

Forward/reverse active off-hook

45 + I

LIM

+ ABIAS

Forward/reverse active OHT

OBIAS = 4 mA, V

BAT

= 70 V

Ringing, V

RING

= 45 V

rms

, V

BAT

= 70 V,

Sine Wave, 1 REN load

Notes:

1. All specifications are for a single channel based on measurements with both channels in the same operating state.
2. See "3.14.4. Ringing Power Considerations" on page 53 for current and power consumption under other operating

conditions.

3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must

include an additional (V

+ |V

BAT

|) x I

LOOP

term.

Si3220/25

Rev. 1.2

Supply Current

(Si3200)

VDD

Sleep mode, RESET = 0

110

µA

Open (high-impedance)

110

µA

Active on-hook standby

110

µA

Forward/reverse active off-hook,

ABIAS = 4 mA, V

BAT

= 24 V

110

µA

Forward/reverse OHT, OBIAS = 4 mA,

BAT

= 70 V

110

µA

Ringing, V

RING

= 45 V

rms

BAT

= 70 V,

Sine Wave, 1 REN load

110

µA

BAT

Supply Current

(Si3200)

VBAT

Sleep mode, RESET=0,

BAT

= 70 V

100

µA

Open (high-impedance),

BAT

= 70 V

189

µA

Active on-hook standby,

BAT

= 70 V

517

µA

Forward/reverse active off-hook,

ABIAS = 4 mA, V

BAT

= 24 V

4.5 +

LIM

Forward/reverse OHT, OBIAS = 4 mA,

BAT

= 70 V

8.6

Ringing, V

RING

= 45 V

rms

BAT

= 70 V,

Sine Wave, 1 REN load

6.5

Table 3. 3.3 V Power Supply Characteristics

(Continued)

, V

DD1

DD4

3.3 V, T

0 to 70 °C for K/F-Grade, 40 to 85 °C for B/G-Grade)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Notes:

conditions.

3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must

include an additional (V

+ |V

BAT

|) x I

LOOP

term.

Si3220/25

Rev. 1.2

Chipset Power
Consumption

SLEEP

Sleep mode, RESET = 0,

BAT

= 70 V

OPEN

Open (high-impedance), V

BAT

= 70 V

STBY

Active on-hook standby, V

BAT

= 70 V

ACTIVE

Forward/reverse active off-hook,

ABIAS = 4 mA, V

BAT

= 24 V

267

OHT

Forward/reverse OHT, OBIAS = 4 mA,

BAT

= 70 V

757

RING

Ringing, V

RING

= 45 v

rms

BAT

= 70 V, 1 REN load

541

Table 3. 3.3 V Power Supply Characteristics

(Continued)

, V

DD1

DD4

3.3 V, T

0 to 70 °C for K/F-Grade, 40 to 85 °C for B/G-Grade)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Notes:

conditions.

3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must

include an additional (V

+ |V

BAT

|) x I

LOOP

term.

Si3220/25

Rev. 1.2

Table 4. 5 V Power Supply Characteristics

, V

DD1

DD4

5 V, T

0 to 70 °C for K/F-Grade, 40 to 85 °C for B/G-Grade)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

DD1

DD4

Supply

Current (Si3220/Si3225)

VDD1

VDD4

Sleep mode, RESET = 0

Open (high-impedance)

Active on-hook standby

Forward/reverse active off-hook

62 +

LIM

ABIAS

Forward/reverse active OHT

OBIAS = 4 mA

Ringing, V

RING

= 45 V

rms

BAT

= 70 V, 1 REN load

Supply Current

(Si3200)

VDD

Sleep mode, RESET = 0

110

µA

Open (high-impedance)

110

µA

Active on-hook standby

110

µA

Forward/reverse active off-hook,

ABIAS = 4 mA, V

BAT

= 24 V

110

µA

Forward/reverse OHT, OBIAS = 4 mA,

BAT

= 70 V

110

µA

Ringing, V

RING

= 45 V

rms

BAT

= 70 V,

1 REN load

110

µA

Notes:

conditions.

3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must

include an additional (V

+ |V

BAT

|) x I

LOOP

term.

Si3220/25

Rev. 1.2

BAT

Supply Current

(Si3200)

VBAT

Sleep mode, RESET = 0,

BAT

= 70 V

125

µA

Open (high-impedance), V

BAT

= 70 V

190

µA

Active on-hook standby, V

BAT

= 70 V

700

µA

Forward/reverse active off-hook,

ABIAS = 4 mA, V

BAT

= 24 V

4.7 +

LIM

Forward/reverse OHT, OBIAS = 4 mA,

BAT

= 70 V

8.8

Ringing, V

RING

= 45 V

rms

BAT

= 70 V,

1 REN load

6.5

Chipset Power
Consumption

SLEEP

Sleep mode, RESET = 0,

BAT

= 70 V

13.8

OPEN

Open (high-impedance), V

BAT

= 70 V

123

STBY

Active on-hook standby, V

BAT

= 70 V

154

ACTIVE

Forward/reverse active off-hook,

ABIAS = 4 mA, V

BAT

= 24 V

436

OHT

Forward/reverse OHT, OBIAS = 4 mA,

BAT

= 70 V

941

RING

Ringing, V

RING

= 45 V

rms

BAT

= 70 V, 1 REN load

610

Table 4. 5 V Power Supply Characteristics

(Continued)

, V

DD1

DD4

5 V, T

0 to 70 °C for K/F-Grade, 40 to 85 °C for B/G-Grade)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Notes:

conditions.

3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must

include an additional (V

+ |V

BAT

|) x I

LOOP

term.

Si3220/25

Rev. 1.2

Table 5. AC Characteristics

, V

DD1

DD4

3.13 to 5.25 V, T

= 0 to 70 °C for K/F-Grade, 40 to 85 °C for B/G-Grade)

Parameter

Test Condition

Min

Typ

Max

Unit

TX/RX Performance

Overload Level

2.5

Overload Compression

2-Wire PCM

Figure 6

Single Frequency Distortion

2-Wire PCM or PCM 2-Wire:

200 Hz to 3.4 kHz

PCM 2-Wire PCM:

200 Hz 3.4 kHz,

16-bit Linear mode

Signal-to-(Noise + Distortion)
Ratio

200 Hz to 3.4 kHz

D/A or A/D 8-bit

Active off-hook, and OHT, any Z

Figure 5

Audio Tone Generator Signal-to-
Distortion Ratio

0 dBm0, Active off-hook, and

OHT, any Z

Intermodulation Distortion

Gain Accuracy

2-Wire to PCM or PCM to 2-Wire

1014 Hz, Any gain setting

0.25

+0.25

Attenuation Distortion vs. Freq.

0 dBm 0

Figure 7,8

Group Delay vs. Frequency

Figure 9

Gain Tracking

1014 Hz sine wave,

reference level 10 dBm

Signal level:

3 dB to 37 dB

± 0.25

37 dB to 50 dB

± 0.5

50 dB to 60 dB

± 1.0

Round-Trip Group Delay

1014 Hz, Within same time-slot

600

700

µs

Crosstalk between Channels
TX or RX to TX
TX or RX to RX

0 dBm0,

300 Hz to 3.4 kHz
300 Hz to 3.4 kHz

--
--

108
108

75
75

dB
dB

Gain Step Increment

Step size around 0 dB

±0.0005

2-Wire Return Loss

200 Hz to 3.4 kHz

Notes:

1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should

be 10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified.

2. Analog signal measured as V

TIP

RING

. Assumes ideal line impedance matching.

3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking

performance in the signal range of 3 to 37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.

4. The digital gain block is a linear multiplier that is programmable from

to +6 dB. The step size in dB varies over the

complete range. See "3.25. Audio Path Processing" on page 69.

5. V

DD1

DD4

3.3 V, V

BAT

52 V, no fuse resistors, R

600

, Z

600

synthesized using RS register

coefficients.

6. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed 55 dBm.
7. The OBIAS and ABIAS registers program the dc bias current through the SLIC in the on-hook transmission and off-

hook active conditions, respectively. This per-pin total current setting should be selected so it can accommodate the
sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given application.

Si3220/25

Rev. 1.2

Transhybrid Balance

300 Hz to 3.4 kHz

Noise Performance

Idle Channel Noise

C-Message weighted

dBrnC

Psophometric weighted

dBmP

3 kHz flat

dBrn

PSRR from V

DD1

DD4

RX and TX, dc to 3.4 kHz

PSRR from V

BAT

RX and TX, dc to 3.4 kHz

Longitudinal Performance

Longitudinal to Metallic/PCM
Balance (forward or reverse)

200 Hz to 1 kHz

1 kHz to 3.4 kHz

Metallic/PCM to Longitudinal
Balance

200 Hz to 3.4 kHz

Longitudinal Impedance

200 Hz to 3.4 kHz at TIP or RING

OBIAS/ABIAS

00 = 4 mA
01 = 8 mA

10 = 12 mA

11 = 16 mA

--
--
--
--

50
25
25
20

--
--
--
--

Longitudinal Current per Pin

Active off-hook

200 Hz to 3.4 kHz

OBIAS/ABIAS

00 = 4 mA
01 = 8 mA

10 = 12 mA

11 = 16 mA

--
--
--
--

4
8
8

--
--
--
--

mA
mA
mA
mA

Table 5. AC Characteristics (Continued)

, V

DD1

DD4

3.13 to 5.25 V, T

= 0 to 70 °C for K/F-Grade, 40 to 85 °C for B/G-Grade)

Parameter

Test Condition

Min

Typ

Max

Unit

Notes:

1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should

be 10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified.

2. Analog signal measured as V

TIP

RING

. Assumes ideal line impedance matching.

3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking

performance in the signal range of 3 to 37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.

4. The digital gain block is a linear multiplier that is programmable from

to +6 dB. The step size in dB varies over the

complete range. See "3.25. Audio Path Processing" on page 69.

5. V

DD1

DD4

3.3 V, V

BAT

52 V, no fuse resistors, R

600

, Z

600

synthesized using RS register

coefficients.

Si3220/25

Rev. 1.2

Table 6. Linefeed Characteristics

, V

DD1

DD4

3.13 to 5.25 V, T

0 to 70 °C for K/F-Grade, 40 to 85 °C for B/G-Grade)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Maximum Loop Resistance (adaptive
linefeed disabled

)

LOOP

DC,MAX

= 430

LOOP

= 18 mA, V

BAT

= 52 V,

ABIAS = 8 mA

VOCDELTA = 0

1870

Maximum Loop Resistance (adaptive
linefeed enabled

)

LOOP

DC,MAX

= 430

LOOP

= 18 mA, V

BAT

= 52 V,

ABIAS = 8 mA

VOCDELTA

2030

DC Loop Current Accuracy

LIM

= 18 mA

±10

DC Open Circuit Voltage Accuracy

Active Mode; V

= 48 V,

TIP

RING

±4

DC Differential Output Resistance

LOOP

< I

LIM

320

DC On-Hook Voltage Accuracy--Ground
Start

OHTO

RING

LIM

; V

RING

wrt ground,

RING

= 51 V

±4

DC Output Resistance--Ground Start

ROTO

RING

LIM

; RING to ground

320

DC Output Resistance--Ground Start

TOTO

TIP to ground

300

Loop Closure Detect Threshold Accuracy

THR

= 13 mA

±10

±15

Ground Key Detect Threshold Accuracy

THR

= 13 mA

±10

±15

Ring Trip Threshold Accuracy

Si3220, ac detection,

VRING = 70 Vpk, no offset,

= 80 mA

±4

±5

Si3220, dc detection,

20 V dc offset, I

= 13 mA

±1.5

±2

Si3225, dc detection,

48 V dc offset, R

loop

= 1500

±4.5

Ringing Amplitude, Si3220

RING

Open circuit, V

BATH

= 100 V

5 REN load, R

LOOP

= 0

BATH

= 100 V

Sinusoidal Ringing Total
Harmonic Distortion

THD

Ringing Frequency Accuracy

f = 16 Hz to 100 Hz

±1

Ringing Cadence Accuracy

Accuracy of ON/OFF times

±50

Calibration Time

CAL to CAL bit

600

Notes:

1. Adaptive linefeed is enabled when the VOCDELTA RAM address is set to a non-zero value and is disabled when

VOCDELTA is set to 0.

2. R

DC,MAX

is the maximum dc resistance of the CPE; hence the specified total loop resistance is R

LOOP

+ R

DC,MAX

3. Ringing amplitude is set for 93 V peak using the RINGAMP RAM address and measured at TIP-RING using no series

protection resistance.

Si3220/25

Rev. 1.2

Loop Voltage Sense Accuracy

Accuracy of boundaries for

each output code;

TIP

RING

= 48 V

±2

±4

Loop Current Sense Accuracy

Accuracy of boundaries for

each output code;

LOOP

= 18 mA

±7

±10

Power Alarm Threshold Accuracy

Power Threshold = 300 mW

±25

Table 7. Monitor ADC Characteristics

, V

DD1

DD4

3.13 to 5.25 V, T

0 to 70 °C for K/F-Grade, 40 to 85 °C for B/G-Grade)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Resolution

Bits

Differential Nonlinearity

DNL

1.0

±0.75

+1.5

LSB
LSB

Integral Nonlinearity

INL

±0.6

±1.5

LSB

Gain Error

±0.1

±0.25

LSB

Table 6. Linefeed Characteristics (Continued)

, V

DD1

DD4

3.13 to 5.25 V, T

0 to 70 °C for K/F-Grade, 40 to 85 °C for B/G-Grade)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Notes:

1. Adaptive linefeed is enabled when the VOCDELTA RAM address is set to a non-zero value and is disabled when

VOCDELTA is set to 0.

2. R

DC,MAX

is the maximum dc resistance of the CPE; hence the specified total loop resistance is R

LOOP

+ R

DC,MAX

3. Ringing amplitude is set for 93 V peak using the RINGAMP RAM address and measured at TIP-RING using no series

protection resistance.

Si3220/25

Rev. 1.2

Table 8. Si3200 Characteristics

3.13 to 5.25 V, T

0 to 70 °C for K/F-Grade, 40 to 85 °C for B/G-Grade)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

TIP/RING Pulldown Transistor Satura-
tion Voltage

RING

BAT

(Forward)

TIP

BAT

(Reverse)

LIM

= 22 mA, I

ABIAS

= 4 mA

LIM

= 45 mA,

ABIAS

= 16 mA

V
V

TIP/RING Pullup Transistor
Saturation Voltage

GND V

TIP

(Forward)

GND V

RING

(Reverse)

LIM

= 22 mA

LIM

= 45 mA

V
V

Battery Switch Saturation
Impedance

SAT

BAT

BATH

)/I

OUT

(Note 2)

OPEN State TIP/RING Leakage Current

LKG

= 0

100

µA

Internal Blocking Diode Forward Voltage

BAT

BATL

(Note 2)

0.8

Notes:

1. V

2.5 V

, R

LOAD

600

2. I

OUT

= 60 mA.

Table 9. DC Characteristics (V

, V

DD1

DD4

5 V)

, V

DD1

DD4

4.75 to 5.25 V, T

0 to 70 °C for K/F-Grade, 40 to 85 °C for B/G-Grade)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

High Level Input
Voltage

0.7 x

5.25

Low Level Input
Voltage

0.3 x

High Level Output
Voltage

= 8 mA

0.6

Low Level Output
Voltage

DTX, SDO, INT, SDITHRU:

= 8 mA

0.4

BATSELa/b, RRDa/b,

GPOa/b, TRD1a/b,TRD2a/b:

= 40 mA

0.72

SDITHRU Internal
Pullup Resistance

Relay Driver Source
Impedance

OUT

DD1

DD4

= 4.75 V

< 28 mA

Relay Driver Sink
Impedance

DD1

DD4

= 4.75 V

< 85 mA

Input Leakage Current

±10

µA

Si3220/25

Rev. 1.2

Table 10. DC Characteristics (V

, V

DD1

DD4

3.3 V)

, V

DD1

DD4

3.13 to 3.47 V, T

0 to 70 °C for K/F-Grade, 40 to 85 °C for B/G-Grade)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

High Level Input Voltage

0.7 x V

5.25

Low Level Input Voltage

0.3 x V

High Level Output
Voltage

= 4 mA

0.6

Low Level Output
Voltage

DTX, SDO, INT,

SDITHRU:

= 4 mA

0.4

BATSELa/b, RRDa/b,

GPOa/b, TRD1a/b, TRD2a/b:

= 40 mA

0.72

SDITHRU internal pullup
resistance

Relay Driver Source Imped-
ance

OUT

DD1

DD4

= 3.13 V

IO < 28 mA

Relay Driver Sink Impedance

DD1

DD4

= 3.13 V

IO < 85 mA

Input Leakage Current

±10

µA

Table 11. Switching Characteristics--General Inputs

, V

DD1

DD4

3.13 to 5.25 V, T

0 to 70 °C for K/F-Grade, 40 to 85 °C for B/G-Grade, C

20 pF)

Parameter

Symbol

Min

Typ

Max

Unit

Rise Time, RESET

RESET Pulse Width, GCI Mode

500

RESET Pulse Width, SPI Daisy Chain Mode

µs

Notes:

1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are V

0.4 V, V

0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.

2. The minimum RESET pulse width assumes the SDITHRU pin is tied to ground via a pulldown resistor no greater than

10 k

per device.

Si3220/25

Rev. 1.2

Figure 1. SPI Timing Diagram

Table 12. Switching Characteristics--SPI

DDA

= V

DDA

= 3.13 to 5.25 V, T

= 0 to 70 °C for K/F-Grade, 40 to 85 °C for B/G-Grade, C

= 20 pF

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Cycle Time SCLK

Rise Time, SCLK

Fall Time, SCLK

Delay Time, SCLK Fall to SDO Active

Delay Time, SCLK Fall to SDO
Transition

Delay Time, CS Rise to SDO Tri-state

Setup Time, CS to SCLK Fall

su1

Hold Time, CS to SCLK Rise

Setup Time, SDI to SCLK Rise

su2

Hold Time, SDI to SCLK Rise

Delay Time between Chip Selects

220

SDI to SDITHRU Propagation Delay

Note: All timing is referenced to the 50% level of the waveform. Input test levels are V

= V

DDD

0.4 V, V

= 0.4 V

SCLK

SDI

SDO

su1

su2

SDITHRU

Si3220/25

Rev. 1.2

Table 13. Switching Characteristics--PCM Highway Interface

, V

DD1

DD4

3.13 to 5.25 V, T

0 to 70 °C for K/F-Grade, 40 to 85 °C for B/G-Grade, C

20 pF)

Parameter

Symbol

Test

Conditions

Min

Typ

Max

Units

PCLK Period

122

3906

Valid PCLK Inputs

--
--
--
--
--
--
--
--
--

256
512
768

1.024
1.536
1.544
2.048
4.096
8.192

--
--
--
--
--
--
--
--
--

kHz
kHz
kHz

MHz
MHz
MHz
MHz
MHz
MHz

FSYNC Period

125

µs

PCLK Duty Cycle Tolerance

dty

PCLK Period Jitter Tolerance

jitter

±120

Rise Time, PCLK

Fall Time, PCLK

Delay Time, PCLK Rise to DTX Active

Delay Time, PCLK Rise to DTX
Transition

Delay Time, PCLK Rise to DTX
Tristate

Setup Time, FSYNC to PCLK Fall

su1

Hold Time, FSYNC to PCLK Fall

Setup Time, DRX to PCLK Fall

su2

Hold Time, DRX to PCLK Fall

FSYNC Pulse Width

wfs

125 µst

Notes:

1. All timing is referenced to the 50% level of the waveform. Input test levels are V

I/O

0.4 V, V

0.4 V.

2. FSYNC source is assumed to be 8 kHz under all operating conditions.
3. Specification applies to PCLK fall to DTX tristate when that mode is selected.

Si3220/25

Rev. 1.2

Table 14. Switching Characteristics--GCI Highway Serial Interface

, V

DD1

DD4

3.13 to 5.25 V, T

0 to 70 °C for K/F-Grade, 40 to 85 °C for B/G-Grade)

Figure 3. GCI Highway Interface Timing Diagram (2.048 MHz PCLK Mode)

Parameter

Symbol

Test

Conditions

Min

Typ

Max

Units

PCLK Period (2.048 MHz PCLK Mode)

488

PCLK Period (4.096 MHz PCLK Mode)

244

FSYNC Period

125

µs

PCLK Duty Cycle Tolerance

dty

FSYNC Jitter Tolerance

jitter

±120

Rise Time, PCLK

Fall Time, PCLK

Delay Time, PCLK Rise to DTX Active

Delay Time, PCLK Rise to DTX Transition

Delay Time, PCLK Rise to DTX Tristate

Setup Time, FSYNC Rise to PCLK Fall

su1

Hold Time, PCLK Fall to FSYNC Fall

Setup Time, DRX Transition to PCLK Fall

su2

Hold Time, PCLK Falling to DRX Transition

FSYNC Pulse Width

wfs

Notes:

1. All timing is referenced to the 50% level of the waveform. Input test levels are V

0.4 V, V

0.4 V, rise and

fall times are referenced to the 20% and 80% levels of the waveform.

2. FSYNC source is assumed to be 8 kHz under all operating conditions.
3. Specification applies to PCLK fall to DTX tristate when that mode is selected.

su1

PCLK

FSYNC

DRX

DTX

su2

Frame 0,

Bit 0

Frame 0,

Bit 0

Si3220/25

Rev. 1.2

2. Bill of Materials

Table 15. Si3220 + Si3200 External Component Values

Component

Value

Function

C1, C2, C11, C12

100 nF, 100 V, X7R, ±20% Filter capacitors for TIP, RING ac-sensing inputs.

C3, C4, C13, C14

10 nF, 100 V, X7R, ±20%

TIP/RING compensation capacitors.

C5, C6, C15, C16

1 µF, 6.3 V, X7R, ±20%

Low-pass filter capacitors to stabilize differential and
common-mode SLIC feedback loops.

C30C33

0.1 µF, 100 V, Y5V

Decoupling for battery voltage supply pins.

C20C25

0.1 µF, 10 V, Y5V

Decoupling for analog and digital chip supply pins.

R1, R2, R11, R12

402 k

, 1/10 W, ±1%

Sense resistors for TIP, RING voltage-sensing nodes.

R3, R4, R13, R14

4.7 k

, 1/10 W, ±1%

Current limiting resistors for TIP, RING ac-sensing inputs.

R5, R15

806 k

, 1/10 W, ±1%

Sense resistor for battery dc-sensing nodes.

R6, R16

40.2 k

, 1/10 W, ±5%

Sets bias current for battery-switching circuit.

R7, R8, R17, R18

182

, 1/10 W, ±1%

Reference resistors for internal transconductance amplifier.

R10

40.2 k

, 1/10 W, ±1%

Generates a high accuracy reference current.

R20, R22

, 1/10 W, ±5%

Protection against power supply transients.

R21, R23

, 1/8 W, ±5%

Protection against power supply transients.

R24, R25*

39 k

, 1/10 W, ±5%

Pulldown resistors.

*Note: R24 and R25 must be populated for each Si3220 in the system.

Si3220/25

Rev. 1.2

Table 16. Si3225 + Si3200 External Component Values

Component

Value

Function

C1, C2, C11, C12

100 nF, 100 V, X7R, ±20% Filter capacitors for TIP, RING ac sensing inputs.

C3, C4, C13, C14

10 nF, 100 V, X7R, ±20% TIP/RING compensation capacitors.

C5, C6, C15, C16

1 µF, 6.3 V, X7R, ±20%

Low-pass filter capacitors to stabilize differential and com-
mon mode SLIC feedback loops.

C30

, C31

, C32, C33

0.1 µF, 100 V, Y5V

Decoupling for battery voltage supply pins.

C20C25

0.1 µF, 10 V, Y5V

Decoupling for analog and digital chip supply pins.

R1, R2, R11, R12

402 k

, 1/10 W, ±1%

Sense resistors for TIP, RING dc sensing nodes.

R5, R15

806 k

, 1/10 W, ±1%

Sense resistors for battery voltage sensing nodes.

R3, R4, R13, R14

4.7 k

, 1/10 W, ±1%

Current limiting resistors for TIP, RING ac sensing inputs.

, R16

40.2 k

, 1/10 W, ±5%

Sets bias current for battery switching circuit.

R7, R8, R17, R18

182

, 1/10 W, ±1%

Reference resistors for internal transconductance amplifier.

R9, R19, R20

806 k

, 1/10 W, ±1%

Sense registers for ringing generator feed.

R10

40.2 k

, 1/10 W, ±1%

Generates a high accuracy reference current.

R21, R22

510

, 2W, ±2%

Feed resistor for ringing generator source.

R23, R25

, 1/10 W, ±5%

Protection against power supply transients.

R24, R26

, 1/8 W, ±5%

Protection against power supply transients.

R27, R28

39 k

, 1/10 W, ±5%

Pulldown resistors.

Notes:

1. Optional. Only required when using dual-battery architecture.
2. Example power rating.
3. R27 and R28 must be populated for each Si3225 in the system.

Si3220/25

Rev. 1.2

3. Functional Description

The Dual ProSLIC

chipset is a three-chip integrated

solution that provides all SLIC, codec, and DTMF
detection/decoding functions needed for a complete
dual-channel analog telephone interface. Intended for
multiple-channel long-loop (up to 18 kft) applications
requiring high-density line card designs, the Dual
ProSLIC chipset provides high integration and low-
power operation for applications, such as Central Office
(CO) and digital loop carrier (DLC) enclosures. The
Dual ProSLIC chipset is also ideal for short-loop
applications requiring a space-effective solution, such
as terminal adapters, integrated access devices (IADs),
PBX/key systems, and voice-over IP systems. The
chipset meets all relevant Bellcore LSSGR, ITU, and
ETSI standards.
The Si3220/Si3225 ICs perform all battery, overvoltage,
ringing, supervision, codec, hybrid, and test
(BORSCHT) functions on-chip in a low-power, small-
footprint solution. DTMF decoding and generation,
phase continuous FSK (caller ID) signaling, and pulse
metering are also integrated. All high-voltage functions
are implemented using the Si3200 Linefeed Interface IC
allowing a highly-programmable integrated solution that
offers the lowest total system cost.
The internal linefeed circuitry provides programmable
on-hook voltage and off-hook loop current, reverse
battery operation, loop or ground-start operation, and
on-hook transmission. Loop current and voltage are
continuously monitored using an integrated 8-bit
monitor A/D converter. The Si3220 provides on-chip
balanced 5 REN ringing with or without a programmable
dc offset, eliminating the need for an external bulk ring
generator and per-channel ringing relay. Both sinusoidal
and trapezoidal ringing waveshapes are available.
Ringing parameters, such as frequency, waveshape,
cadence, and offset, are available in registers to reduce
external controller requirements. The Si3225 supports
external ringing generation with ring relay driver and
external ring trip sensing to address legacy systems
that implement a centralized ringing architecture. All
ringing options are software-programmable over a wide
range of parameters to address a wide variety of
application requirements.
The Si3220/Si3225 ICs also provide a variety of line
monitoring and subscriber loop testing functions. All
versions have the ability to generate specific dc and
audio signals and continuously monitor and store all line
voltage and current parameters. This combination of
signal generation and measurement tools allows remote
line card and loop diagnostics without requiring
additional test equipment. These diagnostic functions

comply with relevant LSSGR and ITU requirements for
line-fault detection and reporting, and measured values
are stored in registers for later use or further
calculations. The Si3220 and Si3225 also include two
relay drives per channel to support legacy systems
implementing centralized test equipment.
A complete audio transmit and receive path is
integrated, including DTMF generation and decoding,
tone generation, modem/fax tone detection,
programmable ac impedance synthesis, and
programmable transhybrid balance and programmable
gain attenuation. These features are software-
programmable providing a single hardware design to
meet international requirements. Digital voice data
transfer occurs over a standard PCM bus, and control
data is transferred using a standard 4-wire serial
peripheral interface (SPI). The Si3220 and Si3225 can
also be configured to support a 4-wire general circuit
interface (GCI). The Si3220 and Si3225 are available in
a 64-lead TQFP, and the Si3200 is available in a
thermally-enhanced 16-lead SOIC.

3.1. Dual ProSLIC Architecture

The Dual ProSLIC chipset is comprised of a low-voltage
CMOS device that uses a low-cost integrated linefeed
interface IC to control the high voltages needed for
operating the terminal equipment connected to the
telephone line. Figure 15 presents a simplified diagram
of the linefeed control loop circuit for controlling the TIP
and RING leads. The diagram illustrates a single-ended
model for simplicity, showing either the TIP or the RING
lead.
The Dual ProSLIC chipset produces line voltages and
currents on the TIP/RING pair using register-
programmable settings as well as direct ac and dc
voltage/current sensing from the line. The Si3200 LFIC
provides a low-cost interface for bridging the low-
voltage CMOS devices to the high-voltage TIP/RING
pair. Sense resistors allow the voltage and current to be
measured on each lead or across T-R using the low-
voltage circuitry inside the Si3220 and Si3225
eliminating expensive analog sensing circuitry inside
the high-voltage Si3200. In addition, the total power
inside the Si3200 is constantly monitored and controlled
to provide optimal reliability under all operating
conditions. The sensing circuitry is calibrated for
environmental and process variations to guarantee
accuracy with standard external resistor tolerances.

Si3220/25

Rev. 1.2

3.2. Power Supply Sequencing

To ensure proper operation, the following power
sequencing guidelines should be followed:

should be allowed to reach its steady state

voltage at least 20 ms before V

BATH

is allowed to

begin to ramp to its desired voltage.
Transients and oscillations with a dv/dt above 10 V/
µs on the V

and V

BATH

supplies should always be

avoided.
The ramp-up time for V

should be in the range of

2 ms to 20 ms. The ramp-up time for V

BATH

should

be in the range of 10 ms to 150 ms. Slower ramp-up
times are not recommended.
V

BATL

rail must never be more negative than the

BATH

rail during any part of the power supply ramp-

up.

The Si3200 features an ESD clamp protection circuit
connected between the V

and V

BATH

rails. This

clamp protects the Si3200 against ESD damage when
the device is being handled out-of-circuit during
manufacture. Precautions must be taken in the V

and

BATH

system power supply design. At power-up, the

and V

BATH

rails must ramp-up from 0 V to their

respective target values in a linear fashion and must not
exhibit fast transients or oscillations which could cause
the ESD clamp to be activated for an extended period of
time resulting in damage to the Si3200. The resistors
shown as R20 through R23 together with capacitors
C23, C24, C30 and C31 on Figure 12 and R23 through
R26 along with capacitors C24, C25, C32 and C33 in
Figure 13 provide some measure of protection against
in-circuit ESD clamp activation by forming a filter time
constant and by providing current limiting action in case
of momentary clamp activation during power-up. These
resistors and capacitors must be included in the
application circuit, while ensuring that the V

and

BATH

system power supplies are designed to exhibit

start-up behavior that is free of undesirable transients or
oscillations. Once the V

and V

BATH

are in their steady

state final values, the ESD clamp has circuitry that
prevents it from being activated by transients slower
than 10 V/µs. In the steady powered-up state, the V

and V

BATH

rails must therefore not exhibit transients

resulting in a voltage slew rate greater than 10 V/µs.

3.3. DC Feed Characteristics

The Si3220 and Si3225 offer programmable constant-
voltage and constant-current operating regions as
illustrated in Figure 14. The constant voltage region
(defined by the open-circuit voltage, V

) is

programmable from 0 to 63.3 V in 1 V steps. The

constant current region (defined by the loop current
limit, I

LIM

) is programmable from 18 to 45 mA in

0.87 mA steps. The Si3220 and Si3225 exhibit a
characteristic dc impedance of 640

or 320 during

active mode. (See "3.4. Adaptive Linefeed" on page 33).
The TIP-RING voltage (V

) is offset from ground by a

programmable voltage (V

) to provide sufficient

voltage headroom to the most positive terminal
(typically the TIP lead in normal polarity or the RING
lead in reverse polarity) for carrying audio signals. A
similar programmable voltage (V

) is an offset

between the most negative terminal and the battery
supply rail for carrying audio signals. (See Figure 14.)
The user-supplied battery voltage must have sufficient
amplitude under all operating states to ensure sufficient
headroom. The Si3200 may be powered by a lower
secondary battery supply (V

BATL

) to reduce total power

dissipation when driving short-loop lengths.

Figure 14. DC Linefeed Overhead Voltages

(Forward State)

3.3.1. Calculating Overhead Voltages
The two programmable overhead voltages (V

and

) represent one portion of the total voltage between

BAT

and ground as illustrated in Figure 14. Under

normal operating conditions, these overhead voltages
are sufficiently low to maintain the desired TIP-RING
voltage (V

). However, there are certain conditions

under which the user must exercise care in providing a
battery supply with enough amplitude to supply the
required TIP-RING voltage and enough margin to
accommodate these overhead voltages. The V

voltage is programmed for a given operating condition.
Therefore, the open-circuit voltage (V

) varies

according to the required overhead voltage (V

) and

the supplied battery voltage (V

BAT

). The user should

pay attention to the maximum V

and V

that might

be required for each operating state.
In the off-hook active state, sufficient V

must be

maintained to correctly power the phone from the
battery supply that is provided. Because the battery
supply depends on the state of the input supply (i.e.,

Constant I Region

Constant V Region

LOOP

BATH

TIP

RING

BATL

Secondary V

BAT

Selected

Loop Closure Threshold

Si3220/25

Rev. 1.2

charging, discharging, or battery backup mode), the
user must decide how much loop current is required and
determine the maximum loop impedance that can be
driven based on the battery supply provided. The
minimum battery supply required can be calculated with
the following equation:

where V

and V

are provided in Table 8 on page 14.

The default V

value of 3 V provides sufficient

overhead for a 3.1 dBm signal into a 600

loop

impedance with an I

LIM

setting of 22 mA and an ABIAS

setting of 4 mA. A V

value of 4 V provides sufficient

headroom to source a maximum I

LOOP

of 45 mA with a

3.1 dBm audio signal and an ABIAS setting of 16 mA.
For a typical operating condition of V

BAT

= 56 V and

LIM

= 22 mA:

These conditions apply when the dc-sensing inputs
(STIPDCa/b and SRINGDCa/b) are placed on the SLIC

side of any protection resistance placed in series with
the TIP and RING leads. If line-side sensing is desired,
both V

and V

must be increased by a voltage

equal to R

PROT

x I

LIM

where R

PROT

is the value of each

protection resistor. Other safety precautions may also
apply.
See "3.14.3. Linefeed Overhead Voltage Considerations
During Ringing" on page 53 for details on calculating the
overhead voltage during the ringing state.
The Dual ProSLIC chipset uses both voltage and
current information to control TIP and RING. Sense
resistor R

measures dc line voltages on TIP and

RING; Capacitor C

couples the ac line voltages on

the TIP and RING leads to be measured. The Si3220
and Si3225 both use the Si3200 to drive TIP and RING
and isolate the high-voltage line from the low-voltage
CMOS devices.
The Si3220 and Si3225 measure voltage at various
nodes to monitor the linefeed current. R

and R

BAT

provide these measuring points. The sense circuitry is
calibrated on-chip to guarantee measurement accuracy.
See "3.6. Linefeed Calibration" on page 36 for details.

Figure 15. Simplified Dual ProSLIC Linefeed Architecture for TIP and RING Leads

(Diagram Illustrates either TIP or RING Lead of a Single Channel)

BAT

OC MAX

56 V

3 V 4 V

(

)

49 V

DSP

A/D

D/A

A/D

SLIC

Control

Audio

Control

SLIC

Control

Loop

Audio

Control

Loop

BAT

Sense

BAT

TIP or

RING

Si3220/

Si3225

Monitor A/D

SLIC DAC

Current

Mirror

Battery

Select

Control

BAT

BATH

Si3200

Low
Frequency
Diagnostic
Filters

Audio
Diagnostic
Filters

Audio

Codec

BATL

BAT

BATSEL

/
S

ITI

P/IRI

I
T

IPN/IR

INGN

IPAC/SRINGAC

Si3220/25

Rev. 1.2

3.3.2. Linefeed Operation States
The linefeed interface includes eight different operating
states as shown in Table 17. The linefeed register
settings (LF[2:0], linefeed register) are also listed. The
open state is the default condition in the absence of any
pre-loaded register settings. The device may also
automatically enter the open state if excess power
consumption is detected in the Si3200. See "3.8. Power
Monitoring and Power Fault Detection" on page 36 for

more details. The register and RAM locations used for
programming the linefeed parameters are provided in
Table 18. See "3.7. Loop Voltage and Current
Monitoring" and "3.8. Power Monitoring and Power Fault
Detection" on page 36, and "3.8.5. Power Dissipation
Considerations" on page 39 for detailed descriptions
and register/RAM locations for these functions.

Table 17. Linefeed States

Open (LF[2:0]

= 000).

The Si3200 output is high-impedance. This mode can be used in the presence of line fault conditions and to
generate open-switch intervals (OSIs). The device can also automatically enter the open state if excess power
consumption is detected in the Si3200 or in the discrete bipolar transistors.

Forward Active (LF[2:0]

= 001).

Linefeed is active, but audio paths are powered down until an off-hook condition is detected. The Si3220 and
Si3225 automatically enter a low-power state to reduce power consumption during on-hook standby periods.

Forward On-Hook Transmission (LF[2:0]

= 010).

Provides data transmission during an on-hook loop condition (e.g., transmitting FSK caller ID information
between ringing bursts).

Tip Open (LF[2:0]

= 011).

Sets the portion of the linefeed interface connected to the TIP side of the subscriber loop to high-impedance
and provides an active linefeed on the RING side of the loop for ground-start operation.

Ringing (LF[2:0]

= 100).

Drives programmable ringing waveforms onto the subscriber loop (Si3220) or switches in a centralized ringing
generator by driving an external relay (Si3225).

Reverse Active (LF[2:0]

= 101).

Linefeed circuitry is active, but audio paths are powered down until an off-hook condition is detected. The
Si3220 and Si3225 automatically enter a low-power state to reduce power consumption during on-hook
standby periods.

Reverse On-Hook Transmission (LF[2:0]

= 110).

Provide data transmission during an on-hook loop condition.

Ring Open (LF[2:0]

= 111).

Sets the portion of the linefeed interface connected to the RING side of the subscriber loop to high impedance
and provides an active linefeed on the TIP side of the loop for ground start operation.

Si3220/25

Rev. 1.2

3.4. Adaptive Linefeed

The Si3220/Si3225 features a proprietary dc feed
design known as adaptive linefeed.
Figure 16 shows the V/I characteristics of adaptive
linefeed. Essentially, adaptive linefeed changes the
source impedance of the dc feed as well as the
apparent open-circuit voltage (VOC) in order to ensure
the ability to source extended loop lengths. The
following sections provide a detailed explanation of
adaptive linefeed.
3.4.1. Adaptive Linefeed Example
This section provides a detailed description of adaptive
linefeed operation by utilizing an example. The behavior
of adaptive linefeed is controlled by the following RAM
locations: VOV, VCM, VOC, VOCLTH, VOCHTH, and
VOCDELTA (see Equation 1). The ILIM register also
plays a role in determining the behavior of the dc feed
as it sets the current limit for the constant current

source. ILIM is a 5-bit register field, which is
programmable from 18 to 45 mA in 0.875 mA steps (i.e.,
ILIM = 0x0 corresponds to 18 mA, and ILIM= 0x1F
corresponds to 45 mA).
The following equation is used to calculate VOV, VCM,
VOC, VOCLTH, VOCHTH, and VOCDELTA.

In the above equation, the ROUND function rounds the
result to the nearest integer while the CEILING function
rounds-up the result to the nearest integer. The
DEC2HEX function converts a decimal integer into a
hexadecimal integer.
The RAM values shown in Table 19 where used to
generate the adaptive linefeed V/I curve shown in
Figure 16. Note that a battery voltage of 56 V was
assumed, as shown in Table 19.

Table 18. Register and RAM Locations for Linefeed Control

Parameter

Register/

RAM

Mnemonic

Register/RAM

Bits

Programmable

Range

LSB Size

Effective

Resolution

Linefeed

LINEFEED

LF[2:0]

See Table 17

N/A

Linefeed Shadow

LINEFEED

LFS[2:0]

Monitor Only

N/A

Battery Feed Control

RLYCON

BATSEL

BATH

BATL

N/A

Loop Current Limit

ILIM

ILIM[4:0]

1845 mA

0.875 mA

On-Hook Line Voltage

VOC

VOC[14:0]

0 to 63.3 V

4.907 mV

1.005 V

Common Mode Voltage

VCM

VCM[14:0]

0 to 63.3 V

4.907 mV

1.005 V

Delta for Off-Hook

VOCDELTA

VOCDELTA[14:0]

0 to 63.3 V

4.907 mV

1.005 V

Delta Threshold, Low

VOCLTH

VOCLTH[15:0]

0 to 63.3 V

4.907 mV

1.005 V

Delta Threshold, High

VOCHTH

VOCHTH[15:0]

0 to 63.3 V

4.907 mV

1.005 V

Overhead Voltage

VOV

VOV[14:0]

0 to 63.3 V

4.907 mV

1.005 V

Ringing Overhead Voltage

VOVRING

VOVRING[14:0]

0 to 63.3 V

4.907 mV

1.005 V

During Battery Tracking

VOCTRACK

VOCTRACK[15:0]

0 to 63.3 V

4.907 mV

1.005 V

512

005

voltage

desired

ROUND

CEILING

HEX

DEC

RAMValue

Table 19. Adaptive Linefeed Example Values

VBAT

VOV

VCM

VOC

ILIM

VOCLTH

VOCHTH

VOCDELTA

56 V

4 V

3 V

48 V

20 mA

7 V

+2 V

+6 V

Si3220/25

Rev. 1.2

Figure 16. Adaptive Linefeed V/I Behavior

When the Si3220/Si3225 is used with the Si3200
linefeed device, the source impedance of the dc feed is
640

before the adaptive linefeed transition and 320

after the adaptive linefeed transition, as shown in
Figure 16. On the other hand, when the Si3220/Si3225
is used with a discrete bipolar transistor linefeed, the
source impedance of the dc feed is 320

both before

and after the adaptive linefeed transition.
The loop closure thresholds are programmable via the
LCROFFHK and LCRONHK RAM addresses. The
LCRLPF RAM address provides filtering of the
measured loop current, and the LCRDBI RAM address
provides de-bouncing. The LCR status bit in register
LCRRTP indicates when a loop closure event has been
detected. See "3.10. Loop Closure Detection" on
page 44 for additional details.
3.4.2. On-Hook to Off-Hook Transition
Referring to Figure 16, point 1 represents the open-
circuit voltage (VOC = 48 V) of the dc feed. At point 1,
the source impedance of the dc feed is 640

(320 for

discrete bipolar transistor linefeed) and VTIP/
RING = VOC, since no current flows in the loop. When

a dc load is connected across TIP and RING and as dc
current begins to flow in the dc loop, the product of the
dc loop current and the 640

source impedance

(320

for a discrete bipolar transistor linefeed) causes

the VTIP/RING voltage to decline linearly with
increasing loop current. When the VTIP/RING voltage
reaches the VOCLTH threshold (point 2), adaptive
linefeed switches the source impedance of the dc feed
to 320

and simultaneously boosts the value of VOC

by VOCDELTA (point 3). The source impedance of the
dc feed will now remain at 320

until the programmed

current limit (ILIM) is reached (point 4). At point 4, the dc
feed has entered into the constant current mode of
operation.
Adaptive linefeed can be disabled by writing a value of
zero into the VOCDELTA RAM address. Writing a value
of zero to VOCDELTA simply eliminates the apparent
VOC voltage boost associated with a non-zero
VOCDELTA value. With VOCDELTA = 0 in the case of
the Si3200, the adaptive linefeed transition still changes
the source impedance from 640

to 320 , and there

is a corresponding discontinuity at the transition point.

0.005

0.01

0.015

0.02

0.025

Iloop (A)

ip/

r
i
n

g (

)

320 Ohms

VOCHTH

VOCLTH

VOCDELTA

10 kOhms

2450 Ohms

1930 Ohms

1800 Ohms

Si3220/25

Rev. 1.2

In the case of the discrete bipolar linefeed, since the
source impedance is 320

both before and after the

adaptive linefeed transition, the V/I curve exhibits no
discontinuity at the transition points when
VOCDELTA = 0.
3.4.3. Off-Hook to On-Hook Transition
Load lines of 10 k

, 1930 , and 1800 are shown in

Figure 16. These load lines intercept the linefeed V/I
curve at the V/I point that would result if a load of that
resistance value were connected across TIP and RING.
As the dc loop is opened, the dc feed will exit the
constant current region (point 4) and enter the 320

source impedance region. As the current in the loop
collapses, the VTIP/RING voltage will linearly increase
until VOCHTH (point 5) is reached. At this point,
adaptive linefeed will transition to a source impedance
of 640

(320 for discrete bipolar transistor linefeed)

and decrease the VOC voltage by VOCDELTA (point 6).
3.4.4. VOCTRACK and Adaptive Linefeed

Hysteresis

The two thresholds, VOCLTH and VOCHTH, control
adaptive linefeed hysteresis as shown in Figure 16.
VOCTRACK is a RAM location and is the actual open-
circuit voltage that is being fed to the line. VOCTRACK
is dependent on the measured V

BAT

voltage. The

behavior of VOCTRACK is as shown in the equation
below. As long as V

BAT

is sufficient to supply VOC +

VOV + VCM, VOCTRACK is equal to the programmed
VOC. However, if V

BAT

becomes too small to support

VOC + VOV + VCM, then VOCTRACK will track the
battery voltage so that the programmed VOV and VCM
are satisfied at the expense of a reduced VOC voltage.
In the example of Figure 16, therefore,
VOCTRACK = VOC = 48 V.
The following equation describes VOCTRACK behavior:

The values of VOCLTH and VOCHTH are set relative to
VOCTRACK. In the example shown in Figure 16,
VOCLTH is given as 7 V and VOCHTH as +2 V. This
implies that the VOCLTH threshold is located 7 V below
the prevailing value of VOCTRACK, while the VOCHTH
threshold is located 2 V above the prevailing value of
VOCTRACK.

Therefore, the VOCLTH and VOCHTH thresholds will
automatically track the battery voltage along with
VOCTRACK.
In order to provide an adequate level of adaptive
linefeed hysteresis between the on-hook to off-transition
and the off-hook to on-hook transition, VOCLTH is
programmed below VOCTRACK (e.g., 7 V relative to
VOCTRACK), and VOCHTH is programmed above
VOCTRACK (e.g., +2 V above VOCTRACK). Also,
VOCHTH must be less than VOV 1 V to ensure that a
proper adaptive linefeed transition will occur in a
reduced battery scenario.

3.5. Ground Start Operation

To configure the dc feed for ground start operation, it is
necessary to write the LINEFEED register with the
value corresponding to either TIP-OPEN (LF[2:0] = 011)
or RING-OPEN (LF[2:0] = 111). The TIP-OPEN and
RING-OPEN linefeed modes place the indicated lead in
the OPEN state (>150 k

) while the other lead remains

active.
In ground start operation, an off-hook condition is
signaled by the CPE (Customer Premise Equipment) by
connecting the active lead to earth ground.
The active lead presents a 640

source impedance

before the adaptive linefeed transition (320

for a

discrete bipolar linefeed), and a 320

source

impedance after the adaptive linefeed transition, as
shown in Figure 17. As for loop start operation, the
adaptive linefeed transitions are governed by the
contents of the VOCLTH and VOCHTH RAM
addresses.
The OPEN lead presents a high-impedance (>150 k

Figure 17 illustrates the ground-start VRING/IRING
behavior using VOC = 48 V and I

LIM

= 24 mA in the

TIP-OPEN linefeed state. The ground key current
thresholds are programmable via the LONGLOTH and
LONGHITH RAM addresses. The LONGLPF RAM
address provides filtering of the measured longitudinal
currents, and the LONGDBI RAM address provides de-
bouncing. The LONGHI status bit in register LCRRTP
indicates when a ground key event has been detected.
Upon detecting a ground key event, the linefeed
automatically transitions to the FORWARD ACTIVE (if
initially in TIP-OPEN) or REVERSE ACTIVE (if initially
in RING-OPEN). See "3.11. Ground Key Detection" on
page 45 for additional details.

)

(

VOCTRACK

VOC

VOCTRACK

BAT

Si3220/25

Rev. 1.2

Figure 17. Ground Start V

RING

Behavior

3.6. Linefeed Calibration

An internal calibration algorithm corrects for internal and
external component errors. The calibration is initiated by
setting the CAL register bit. This bit automatically resets
upon completion of the calibration cycle.
A calibration should be executed following system
powerup. Upon release of the chip reset, the chipset will
be in the open state, and calibration may be initiated.
Only one calibration should be necessary if the system
remains powered up.
To optimize Dual ProSLIC performance, the calibration
routine in "AN58: Si3220/Si3225 Programmer's Guide"
should be followed.

3.7. Loop Voltage and Current Monitoring

The Dual ProSLIC chipset continuously monitors the
TIP and RING voltages and currents. These values are
available in registers. An internal 8-bit A/D converter
samples the measured voltages and currents from the
analog sense circuitry and translates them into the
digital domain. The A/D updates the samples at an
800 Hz rate for all inputs except VRNGNG and
IRNGNG, which are sampled at 8 kHz to provide higher
resolution for zero-crossing detection in external ringing
applications. Two derived values, the loop voltage

TIP

RING

) and the loop current are also reported.

For ground start operation, the values reported are
V

RING

and the current flowing in the RING lead.

Table 20 lists the register set associated with the loop
monitoring functions.
The Dual ProSLIC chipsets also include the ability to
perform loop diagnostic functions as outlined in "3.32.2.
Line Test and Diagnostics" on page 95.

3.8. Power Monitoring and Power Fault

Detection

The Dual ProSLIC line monitoring functions can be
used to protect the high-voltage circuitry against
excessive power dissipation and thermal overload
conditions. The Dual ProSLIC devices can prevent
thermal overloads by regulating the total power inside
the Si3200 or in each of the external bipolar transistors
(if using a discrete linefeed circuit). The DSP engine
performs all power calculations and provides the ability
to automatically transition the device into the OPEN
state and generate a power alarm interrupt when
excessive power is detected. Table 21 on page 40
describes the register and RAM locations used for
power monitoring.

0 mA

-48 V

-80 V

-40 V

-20 V

-0 V

24 mA

VOCLTH

VOCHTH

640

320

VOC DELTA

=
24 mA

RING

Si3220/25

Rev. 1.2

Figure 18. Discrete Linefeed Circuit for Power Monitoring

Table 20. Register and RAM Locations Used for Loop Monitoring

Parameter

Register/RAM

Mnemonic

Register/RAM

Bits

Measurement

Range

LSB Size

Effective

Resolution

Loop Voltage Sense
(V

TIP

RING

)

VLOOP

VLOOP[15:0]

0 to 64.07 V

64.07 to 160.173 V

4.907 mV

251 mV
628 mV

TIP Voltage Sense

VTIP

VTIP[15:0]

0 to 64.07 V

64.07 to 160.173 V

4.907 mV

251 mV
628 mV

RING Voltage Sense

VRING

VRING[15:0]

0 to 64.07 V

64.07 to 160.173 V

4.907 mV

251 mV
628 mV

Loop Current Sense

ILOOP

ILOOP[15:0]

0 to 101.09 mA

3.097 µA

500

µA*

Battery Voltage Sense

VBAT

VBAT[15:0]

0 to 63.3 V

0 to 160.173 V

4.907 mV

251 mV
628 mV

Longitudinal Current
Sense

ILONG

ILONG[15:0]

0 to 101.09 mA

3.097 µA

500 µA*

External Ringing Gen-
erator Voltage Sense

VRNGNG

VRNGNG[15:0]

332.04 V

10.172 mV

1.302 V

External Ringing Gen-
erator Current Sense

IRNGNG

IRNGNG[15:0]

662.83 mA

20.3 µA

2.6 mA

*Note: I

LOOP

and I

LONG

are calculated values based on measured I

currents. The resulting effective resolution is

approximately 500 µA.

IRINGP

R7*gain

IRINGN

RING

ITIPP

Q10

R6*gain

ITIPN

TIP

VBAT

RBQ6

RBQ5

82.5

1.74k

82.5

1.74k

Si3220/25

Rev. 1.2

3.8.1. Transistor Power Equations

(Using Discrete Transistors)

When using the Si3220 or Si3225 with discrete bipolar
transistors, it is possible to control the total power of the
solution by individually regulating the power in each
discrete transistor. Figure 18 illustrates the basic
transistor-based linefeed circuit for one channel. The
power dissipation of each external transistor is
estimated based on the A/D sample values. The
approximate power equations for each external BJT are
as follows:
P

CE1

x I

(|V

TIP

| + 0.75 V) x (I

)

CE2

x I

(|V

RING

| + 0.75 V) x (I

)

CE3

x I

(|V

BAT

| R7 x I

) x (I

)

CE4

x I

(|V

BAT

| R6 x I

) x (I

)

CE5

x I

(|V

BAT

| |V

RING

R7 x I

) x (I

)

CE6

x I

(|V

BAT

| |V

TIP

R6 x I

) x (I

)

The maximum power threshold for each device is
software-programmable and should be set based on the
characteristics of the transistor package, PCB design,
and available airflow. If the peak power exceeds the
programmed threshold for any device, the power-alarm
bit is set for that device. Each external bipolar has its
own register bit (PQ1SPQ6S bits of the IRQVEC3
register), which goes high on a rising edge of the
comparator output and remains high until the user
clears it. Each transistor power alarm bit is also
maskable by setting the PQ1EPQ6E bits in the
IRQEN3 register.
3.8.2. Si3200 Power Calculation
When using the Si3200, it is also possible to detect the
thermal conditions of the linefeed circuit by calculating
the total power dissipated within the Si3200. This case
is similar to the transistor power equations case, with
the exception that the total power from all transistor
devices is dissipated within the same package
enclosure, and the total power result is placed in the
PSUM RAM location. The power calculation is derived
using the following equations:
P

(|V

TIP

| + 0.75 V) x I

(|V

RING

| + 0.75 V) x I

(|V

BAT

|+ 0.75 V) x I

(|V

BAT

| + 0.75 V) x I

(|V

BAT

| |V

RING

|) x I

(|V

BAT

| |V

TIP

|) x I

PSUM = total dissipated power = P

+ P

Note: The Si3200 THERM pin must be connected to the

THERM a/b pin of the Si3220/Si3225 in order for the

Si3200 power calculation method to work correctly.

3.8.3. Power Filter and Alarms
The power calculated during each A/D sample period
must be filtered before being compared to a user-
programmable maximum power threshold. A simple
digital low-pass filter is used to approximate the
transient thermal behavior of the package, with the
output of the filter representing the effective peak power
within the package or, equivalently, the peak junction
temperature.
For Q1, Q2, Q3, and Q4 in SOT23 and Q5 and Q6 in
SOT223 packages, the settings for thermal low-pass
filter poles and power threshold settings are (for an
ambient temperature of 70 °C) calculated as follows: If
the thermal time constant of the package is

thermal

, the

decimal values of RAM locations PLPF12, PLPF34, and
PLPF56 are given by rounding to the next integer the
value given by the following equation:

Where 4096 is the maximum value of the 12-bit plus
sign RAM locations PLPF12, PLPF34, and PLPF56,
and 800 is the power calculation clock rate in Hz. The
equation is an excellent approximation of the exact
equation for

thermal

= 1.25 ms ... 5.12 s. With the

above equations in mind, example values of the RAM
locations, PTH12, PTH34, PTH56, PLPF12, PLPF34,
and PLPF56, are as follows:
PTH12 = power threshold for Q1, Q2 = 0.3 W (0x25A)
PTH34 = power threshold for Q3, Q4 = 0.22 W
(0x1B5E)
PTH56 = power threshold for Q5, Q6 = 1 W (0x7D8)
PLPF12 = Q1/Q2 thermal LPF pole = 0x0012
(for SOT89 package)
PLPF34 = Q3/Q4 thermal LPF pole = 0x008C
(for SOT23 package)
PLPF56 = Q5/Q6 thermal LPF pole = 0x000E
(for SOT223 package)
In the case where the Si3200 is used, thermal filtering
needs to be performed only on the total power reflected
in the PSUM RAM location. When the filter output
exceeds the total power threshold, an interrupt is
issued. The PTH12 RAM location is used to preset the
total power threshold for the Si3200, and the PLPF12
RAM location is used to preset the thermal low-pass
filter pole.

PLPFxx (decimal value)

4096

800

thermal

------------------------------------ 2

Si3220/25

Rev. 1.2

When the THERM pin is connected from the Si3220 or
Si3225 to the Si3200 (indicating the presence of an
Si3200), the resolution of the PTH12 and PSUM RAM
locations is modified from 498 µW/LSB to 1059.6 µW/
LSB. Additionally, the

THERMAL

value must be modified

to accommodate the Si3200. For the Si3200,

THERMAL

is typically 0.7 s, assuming the exposed pad is
connected to the recommended ground plane as stated
in Table 1 on page 4.

THERMAL

decreases if the PCB

layout does not provide sufficient thermal conduction.
See "AN58: Si3220/Si3225 Programmer's Guide" for
details.
Example calculations for PTH12 and PLPF12 in Si3200
mode are shown below:
PTH12 = Si3200 power threshold = 1 W (0x3B0)
PLPF12 = Si3200 thermal LPF pole = 2 (0x0010)
3.8.4. Automatic State Change Based on Power

Alarm

If either of the following situations occurs, the device
automatically transitions to the OPEN state:

Any of the transistor power alarm thresholds is
exceeded in the case of the discrete transistor
circuit.
The total power threshold is exceeded when using
the Si3200.

To provide optimal reliability, the device automatically
transitions into the open state until the user changes the
state manually, independent of whether or not the power
alarm interrupt has been masked. The PQ1EPQ6E
bits of the IRQEN3 register enable the interrupts for
each transistor power alarm, and the PQ1S to PQ6S
bits of the IRQVEC3 register are set when a power
alarm is triggered in the respective transistor. When
using the Si3200, the PQ1E bit enables the power alarm
interrupt, and the PQ1S bit is set when a Si3200 power
alarm is triggered.
3.8.5. Power Dissipation Considerations
The Dual ProSLIC devices rely on the Si3200 to power
the line from the battery supply. The PCB layout and
enclosure conditions should be designed to allow
sufficient thermal dissipation out of the Si3200, and a
programmable power alarm threshold ensures product
safety under all operating conditions. See "3.8. Power
Monitoring and Power Fault Detection" on page 36 for
more details on power alarm considerations.

The Si3200's thermally-enhanced SOIC-16 package
offers an exposed pad that improves thermal dissipation
out of the package when soldered to a topside PCB pad
connected to inner power planes. Using appropriate
layout practices, the Si3200 can provide thermal
performance of 55 °C/W. The exposed path should be
connected to a low-impedance ground plane via a
topside PCB pad directly under the part. See package
outlines for PCB pad dimensions. In addition, an
opposite-side PCB pad with multiple vias connecting it
to the topside pad directly under the exposed pad will
further improve the overall thermal performance of the
system. Refer to "AN55: Dual ProSLIC User Guide" for
optimal thermal dissipation layout guidelines.
The Dual ProSLIC chipset is designed with the ability to
source long loop lengths in excess of 18 kft but can also
accommodate short loop configurations. For example,
the Si3220 can operate from one of two battery supplies
depending on the operating state. When in the on-hook
state, the on-hook loop feed is generated from the
ringing battery supply, generally 70 V or more. Once
the SLIC transitions to the off-hook state, a lower off-
hook battery supply (typically 24 V) supplies the
required current to power the loop if the loop length is
sufficiently short to accommodate the lower battery
supply. This battery switching method allows the SLIC
chipset to dissipate less power than when operating
from a 70 V battery supply. See "3.9. Automatic Dual
Battery Switching" for more details.
In long loop applications, there is generally a single
battery supply (e.g., 48 V) available for powering the
loop in the off-hook state. When sourcing loop lengths
similar to the maximum specified service distance (e.g.,
18 kft.), most of the power is dissipated in the
impedance of the line. SLICs used in long-loop
applications must also be able to provide phone service
to customers who are located much closer to the line
card than the maximum loop length specified for the
system. This situation may cause substantial power to
be dissipated inside the SLIC chipset. A special power
offload circuit is recommended for single-battery
extended-loop applications. Refer to "AN91: Si3200
Power Off-load Circuit" for power offload circuit usage
guidelines.

Si3220/25

Rev. 1.2

Table 21. Register and RAM Locations Used for Power Monitoring and Power Fault Detection

Parameter

Register/

RAM

Mnemonic

Register/RAM

Bits

Measurement

Range

Resolution

Si3200 Total Power Output Monitor

PSUM

PSUM[15:0]

0 to 34.72 W

1059.6 µW

Si3200 Power Alarm Interrupt Pending

IRQVEC3

PQ1S

N/A

Si3200 Power Alarm Interrupt Enable

IRQEN3

PQ1E

N/A

Q1/Q2 Power Alarm Threshold (discrete)
Q1/Q2 Power Alarm Threshold (Si3200)

PTH12

PTH12[15:0]

0 to 16.319 W

0 to 34.72 W

498 µW

1059.6 µW

Q3/Q4 Power Alarm Threshold

PTH34

PTH34[15:0]

0 to 1.03 W

31.4 µW

Q5/Q6 Power Alarm Threshold

PTH56

PTH56[15:0]

0 to 16.319 W

498 µW

Q1/Q2 Thermal LPF Pole

PLPF12

PLPF12[15:3]

See "3.8.3. Power Filter and

Alarms"

Q3/Q4 Thermal LPF Pole

PLPF34

PLPF34[15:3]

See "3.8.3. Power Filter and

Alarms"

Q5/Q6 Thermal LPF Pole

PLPF56

PLPF56[15:3]

See "3.8.3. Power Filter and

Alarms"

Q1Q6 Power Alarm Interrupt Pending

IRQVEC3

PQ1SPQ6S

N/A

Q1Q6 Power Alarm Interrupt Enable

IRQEN3

PQ1EPQ6E

N/A

Si3220/25

Rev. 1.2

3.9. Automatic Dual Battery Switching

The Dual ProSLIC chipsets provide the ability to switch
between several user-provided battery supplies to aid
thermal management. Two specific scenarios where
this method may be required follow:

Ringing to off-hook state transition (Si3220):

During the on-hook operating state, the Dual
ProSLIC chipset must operate from the ringing
battery supply to provide the desired ringing signal
when required. Once an off-hook condition is
detected, the Dual ProSLIC chipset must transition
to the lower battery supply (typically 24 V) to
reduce power dissipation during the active state. The
low current consumed by the Dual ProSLIC chipset
during the on-hook state results in very little power
dissipation while being powered from the ringing
battery supply, which can have an amplitude as high
as 100 V depending on the desired ringing
amplitude.
On-hook to off-hook state, short loop feed
(Si3225):

When sourcing both long and short loop

lengths, the Dual ProSLIC chipset can automatically
switch from the typical 48 V off-hook battery supply
to a lower off-hook battery supply (e.g., 24 V) to
reduce the total off-hook power dissipation. The Dual
ProSLIC chipset continuously monitors the TIP-
RING voltage and selects the lowest battery voltage
required to power the loop when transitioning from
the on-hook to the off-hook state, thus assuring the
lowest power dissipation.

The BATSELa and BATSELb pins switch between the
two battery voltages based on the operating state and
the TIP-RING voltage. Figure 19 illustrates the chip
connections required to implement an automatic dual
battery switching scheme. When BATSEL is pulled
LOW, the desired channel is powered from the V

BLO

supply. When BATSEL is pulled HIGH, the V

BHI

source

supplies power to the desired channel.

The BATSEL pins for both channels are controlled using
the BATSEL bit of the RLYCON register and can be
programmed to automatically switch to the lower battery
supply (V

BLO

) when the off-hook TIP-RING voltage is

low enough to allow proper operation from the lower
supply. When using the Si3220, this mode should
always be enabled to allow seamless switching
between the ringing and off-hook states. The same
switching scheme is used with the Si3225 to reduce
power by switching to a lower off-hook battery when
sourcing a short loop.
Automatic battery selection should be disabled before
using the manual battery select control bit (BSEL bit,
Register 5--RLYCON, bit 5). Contact Silicon
Laboratories for information on how to disable
automatic battery selection.
Two thresholds are provided to enable battery switching
with hysteresis. The BATHTH RAM location specifies
the threshold at which the Dual ProSLIC device
switches from the low battery (V

BLO

) to the high battery

BHI

) due to an off-hook-to-on-hook transition. The

BATLTH RAM location specifies the threshold at which
the Si3220/Si3225 switches from V

BHI

to V

BLO

due to a

transition from the on-hook or ringing state to the off-
hook state or because the overhead during active Off-
Hook mode is sufficient to feed the subscriber loop
using a lower battery voltage.
The low-pass filter coefficient is calculated using the
following equation and is entered into the BATLPF RAM
location:
BATLPF = [(2

f x 4096)/800] x 2

Where f = the desired cutoff frequency of the filter
The programmable range of the filter is from 0h (blocks
all signals) to 4000h (unfiltered). A typical value of
10 Hz (0A10h) is sufficient to filter out any unwanted ac
artifacts while allowing the dc information to pass
through the filter.
Table 22 provides the register and RAM locations used
for programming the battery switching functions.

Si3220/25

Rev. 1.2

When generating a high-voltage ringing amplitude using
the Si3220, the power dissipated during the OHT state
typically increases due to operating from the ringing
battery supply in this mode. To reduce power, the
Si3220/Si3200 chipset provides the ability to
accommodate up to three separate battery supplies by
implementing a secondary battery switch using a few
low-cost external components as illustrated in Figure
22.
The Si3220's BATSEL pin is used to switch between the
V

BHI

(typically 48 V) and V

BLO

(typically 24 V) rails

using the switch internal to the Si3200. The Si3220's
GPO pin is used along with the external transistor circuit
to switch the V

BRING

rail (the ringing voltage battery rail)

onto the Si3200's V

BAT

pin when ringing is enabled. The

GPO signal is driven automatically by the ringing
cadence provided that the RRAIL bit of the RLYCON
register is set to 1 (signifying that a third battery rail is
present).

Figure 20. 3-Battery Switching with Si3220/Si3200

SVBAT

Si3200

VBAT

VBATH

VBATL

BATSEL

BRING

BLO

0.1

µF

0.1

µF

806 k

IN4003

R103

CXT5551

R102

CXT5401

R101

10 k

402 k

BHI

40.2 k

Si3220

Table 23. Three-Battery Switching Components

Component

Value

Comments

200 V, 200 mA

1N4003 or similar

100 V PNP

CXT5401 or

similar

100 V NPN

CXT5551 or

similar

R101

1/10 W, ± 5%

2.4 k

for V

=3.3 V

3.9 k

for V

=5 V

R102

10 k

,1/10 W, ± 5%

R103

402 k

,1/10 W,± 1%

Si3220/25

Rev. 1.2

3.10. Loop Closure Detection

Loop closure detection is required to accurately signal a
terminal device going off-hook during the Active, On-
Hook Transmission (forward or reverse polarity), and
ringing linefeed states. The functional blocks required to
implement a loop closure detector are shown in
Figure 21, and the register set for detecting a loop
closure event is provided in Table 24. The primary input
to the system is the loop current sense value from the
voltage/current/power monitoring circuitry and is
reported in the I

LOOP

RAM address.

The loop current (I

LOOP

) is computed by the input signal

processor (ISP) using the equations shown below.
Refer to Figure 18 on page 37 for the discrete bipolar
transistor references) used in the equation below (Q1,
Q2, Q5 and Q6 note that the Si3200 has
corresponding MOS transistors). The same I

LOOP

equation applies to the discrete bipolar linefeed as well
as the Si3200 linefeed device. The following equation is
conditioned by the CMH status bit in register LCRRTP
and by the linefeed state as indicated by the LFS field in
the LINEFEED register.

If the CMHITH (RAM 36) threshold is exceeded, the
CMH bit is 1, and I

is forced to zero in the

FORWARD-ACTIVE and TIP-OPEN states, or I

forced to zero in the REVERSE-ACTIVE and RING-
OPEN states. The other currents in the equation are
allowed to contribute normally to the I

LOOP

value.

The conditioning due to the CMH bit (LCRRTP Register)

and LFS field (LINEFEED Register) states can be
summarized as follows:

IQ1 = 0 if (CMH = 1 AND (LFS = 1 OR LFS = 3))
IQ2 = 0 if (CMH = 1 AND (LFS = 5 OR LFS = 7))

The output of the ISP is the input to a programmable
digital low-pass filter that removes unwanted ac signal
components before threshold detection.
The low-pass filter coefficient is calculated using the
following equation and is entered into the LCRLPF RAM
location:
LCRLPF = [(2

f x 4096)/800] x 2

Where f = the desired cutoff frequency of the filter.
The programmable range of the filter is from 0h (blocks
all signals) to 4000h (unfiltered). A typical value of 10
(0A10h) is sufficient to filter out any unwanted ac
artifacts while allowing the dc information to pass
through the filter.
The output of the low-pass filter is compared to a
programmable threshold, LCROFFHK. Hysteresis is
enabled by programming a second threshold,
LCRONHK, to detect the loop going to an open or on-
hook state. The threshold comparator output feeds a
programmable debounce filter. The output of the
debounce filter remains in its present state unless the
input remains in the opposite state for the entire period
of time programmed by the loop closure debounce
interval, LCRDBI. There is also a loop closure mask
interval, LCRMASK, that is used to mask transients
caused when an internal ringing burst (with no offset)
ends in the presence of a high REN load. If the
debounce interval has been satisfied, the LCR bit is set
to indicate that a valid loop closure has occurred.

Figure 21. Loop Closure Detection Circuitry

loop

in TIP-OPEN or RING-OPEN

+
2

---------------------------------------------------- in all other states

LFS

LCRLPF

LCROFFHK

Input

Signal

Processor

Digital

LPF

Loop Closure

Threshold

Debounce

Filter

LCR

LCRONHK

LOOPS

LOOPE

Interrupt

Logic

LCRDBI

Loop

Closure

Mask

LCRMASK

CMH

LOOP

Si3220/25

Rev. 1.2

3.11. Ground Key Detection

Ground key detection detects an alerting signal from the
terminal equipment during the tip open or ring open
linefeed states. The functional blocks required to
implement a ground key detector are shown in
Figure 22 on page 47, and the register set for detecting
a ground key event is provided in Table 27 on page 48.
The primary input to the system is the longitudinal
current sense value provided by the voltage/current/
power monitoring circuitry and reported in the ILONG
RAM address. The I

LONG

value is produced in the ISP

provided the LFS bits in the linefeed register indicate
the device is in the tip open or ring open state.
The longitudinal current (I

LONG

) is computed as shown

in the following equation. Refer to Figure 18 on page 37
for the transistor references used in the equation (Q1,
Q2, Q5, and Q6--note that the Si3200 has
corresponding MOS transistors). The same I

LONG

equation applies to the discrete bipolar linefeed as well
as the Si3200 linefeed device.

The output of the ISP (I

LONG

) is the input to a

programmable, digital low-pass filter, which removes
unwanted ac signal components before threshold
detection.
The low-pass filter coefficient is calculated using the
following equation and is entered into the LONGLPF
RAM location:

Table 24. Register and RAM Locations Used for Loop Closure Detection

Parameter

Register/RAM

Mnemonic

Register/RAM Bits

Programmable

Range

LSB Size

Effective

Resolution

Loop Closure Interrupt
Pending

IRQVEC2

LOOPS

Yes/No

N/A

Loop Closure Interrupt Enable

IRQEN2

LOOPE

Yes/No

N/A

Linefeed Shadow

LINEFEED

LFS[2:0]

Monitor only

N/A

Loop Closure Detect Status

LCRRTP

LCR

Monitor only

N/A

Loop Closure Detect Debounce
Interval

LCRDBI

LCRDBI[15:0]

0 to 40.96 s

1.25 ms

Loop Current Sense

ILOOP

ILOOP[15:0]

50.54 to

101.09 mA

3.097 µA

500 µA

Loop Closure Threshold
(on-hook to off-hook)

LCROFFHK

LCROFFHK[15:0]

0 to 101.09 mA

3.097 µA

396.4 µA

Loop Closure Threshold
(off-hook to on-hook)

LCRONHK

LCRONHK[15:0]

0 to 101.09 mA

3.097 µA

396.4 µA

Loop Closure Filter Coefficient

LCRLPF

LCRLPF[15:3]

0 to 4000h

N/A

Loop Closure Mask Interval

LCRMASK

LCRMASK[15:0]

0 to 40.96s

1.25 ms

Notes:

1. The effective I

LOOP

resolution is approximately 500

µA.

2. The usable range for LCRONHK and LCROFFHK is limited to 61 mA. Entering a value > 61 mA will disable threshold

detection.

LONG

----------------------------------------------------

LONGLPF

f 4096

(

)

800

---------------------------------

Si3220/25

Rev. 1.2

The output of the debounce filter remains in its present
state unless the input remains in the opposite state for
the entire period of time programmed by the loop
closure debounce interval, LONGDBI. If the debounce
interval is satisfied, the LONGHI bit is set to indicate
that a valid ground key event has occurred.
When the Si3220/25 detects a ground key event, the
linefeed automatically transitions from the TIP-OPEN
(or RING-OPEN) state to the FORWARD-ACTIVE (or
REVERSE-ACTIVE) state. However, this automatic
state transition is triggered by the LCR bit becoming
active (i.e., =1), and not by the LONGHI bit.
While I

LONG

is used to generate the LONGHI status bit,

a transition from TIP-OPEN to the FORWARD-ACTIVE
state (or from the RING-OPEN to the REVERSE-
ACTIVE state) occurs when the RING terminal (or TIP
terminal) is grounded and is based on the LCR bit and
implicitly on exceeding the LCROFFHK threshold.
As an example of ground key detection, suppose that
the Si3220/25 has been programmed with the current
values shown in Table 25.

With the settings of Table 25, the behavior of I

LOOP

LONG

, LCR, LONGHI, and CMHIGH is as shown in

Table 26. The entries under "Loop State" indicate the
condition of the loop, as determined by the equipment
terminating the loop. The entries under "LINEFEED
Setting" indicate the state initially selected by the host
CPU (e.g., TIP-OPEN) and the automatic transition to
the FORWARD-ACTIVE state due to a ground key
event (when RING is connected to GND). The transition
from state #2 to state #3 in Table 26 is the automatic
transition from TIP-OPEN to FWD-ACTIVE in response
to LCR = 1.

Table 25. Settings for Ground Key Example

ILIM

21 mA

LCROFFHK

14 mA

LCRONHK

10 mA

LONGHITH

7 mA

LONGLOTH

5 mA

Si3220/25

Rev. 1.2

3.12. Ringing Generation

The Si3220-based Dual ProSLIC

chipset provides a

balanced ringing waveform with or without dc offset.
The ringing frequency, cadence, waveshape, and dc
offset are register-programmable.
Using a balanced ringing scheme, the ringing signal is
applied to both the TIP and the RING lines using ringing
waveforms that are 180° out of phase with each other.
The resulting ringing signal seen across TIP-RING is
twice the amplitude of the ringing waveform on either
the TIP or the RING line, which allows the ringing
circuitry to withstand half the total ringing amplitude
seen across TIP-RING.

Figure 23. Balanced Ringing

An internal ringing scheme provides >40 Vrms into a 5
REN load at the terminal equipment using a user-
provided ringing battery supply. The specific ringing
supply voltage required depends on the desired ringing
voltage. The ringing amplitude at the terminal
equipment also depends on the loop impedance and
the load impedance in REN. The simplified circuit in
Figure 24 shows the relationship between loop
impedance and load impedance.

Figure 24. Simplified Loop Circuit During

Ringing

The following equation can be used to determine the
TIP-RING ringing amplitude required for a specific load
and loop condition:

where

and

When ringing longer loop lengths, adding a dc offset
voltage is necessary to reliably detect a ring trip
condition (off-hook phone). Adding dc offset to the
ringing signal decreases the maximum possible ringing
amplitude. Adding significant dc offset also increases
the power dissipation in the Si3200 and may require
additional airflow or modified PCB layout to maintain
acceptable operating temperatures in the line feed
circuitry. The Dual ProSLIC chipset automatically
applies and removes the ringing signal during V

crossing periods to reduce noise and crosstalk to
adjacent lines. Table 28 provides a list of registers
required for internal ringing generation

RING

TIP

RING

TIP

SLIC

OFF

GND

TIP

RING

BATH

OFF

LOOP

RING

LOAD

TERM

OUT

TERM

RING

LOAD

LOOP

OUT

(

)

---------------------------------------------------------------------

LOOP

0.09

per foot for 26AWG wire

(

)

OUT

320

LOAD

7000

#REN

--------------------

Si3220/25

Rev. 1.2

Table 28. Register and RAM Locations Used for Ringing Generation

Parameter

Register/RAM

Mnemonic

Register/RAM Bits

Programmable

Range

Resolution

(LSB Size)

Ringing Waveform

RINGCON

TRAP

Sinusoid/Trapezoid

N/A

Ringing Active Timer Enable

RINGCON

TAEN

Enabled/Disabled

N/A

Ringing Inactive Timer
Enable

RINGCON

TIEN

Enabled/Disabled

N/A

Ringing Oscillator Enable
Monitor

RINGCON

RINGEN

Enabled/Disabled

N/A

Ringing Oscillator Active
Timer

RINGTALO/

RINGTAHI

RINGTA[15:0]

0 to 8.19 s

125 µs

Ringing Oscillator Inactive
Timer

RINGTILO/

RINGTIHI

RINGTI[15:0]

0 to 8.19 s

125 µs

Linefeed Control
(Initiates Ringing State)

LINEFEED

LF[2:0]

000 to 111

N/A

On-Hook Line Voltage

VOC

VOC[15:0]

0 to 63.3 V

1.005 V (4.907 mV)

Ringing Voltage Offset

RINGOF

RINGOF[15:0]

0 to 63.3 V

1.005 V (4.907 mV)

Ringing Frequency

RINGFRHI/
RINGFRLO

RINGFRHI[14:3]/

RINGFRLO[14:3]

4 to 100 Hz

Ringing Amplitude

RINGAMP

RINGAMP[15:0]

0 to 160.173 V

628 mV (4.907 mV)

External Ringing Generator
Voltage Sense

VRNGNG

VRNGNG[15:0]

332.04 V

1.302 V

(10.172 mV)

External Ringing Generator
Current Sense

IRNGNG

IRNGNG[15:0]

662.83 mA

2.6 mA (20.3 µA)

Ringing Initial Phase
Sinusoidal
Trapezoid
External Ringing

RINGPHAS

RINGPHAS[15:0]

N/A

0 to 1.024 s

0 to 662.83 mA

N/A

31.25 µs

2.6 mA (20.3 µA)

Ringing Relay Driver Enable
(Si3225 only)

RELAYCON

RDOE

Enabled/Disabled

N/A

Ringing Overhead Voltage

VOVRING

VOVRING[15:0]

0 to 63.3 V

1.005 V (4.907 mV)

Ringing Speedup Timer

SPEEDUPR

SPEEDUPR[15:0]

0 to 40.96 s

1.25 ms

Si3220/25

Rev. 1.2

3.12.1. Internal Sinusoidal Ringing
A sinusoidal ringing waveform is generated by the on-
chip digital tone generator. The tone generator used to
generate ringing tones is a two-pole resonator with a
programmable frequency and amplitude. Since ringing
frequencies are low compared to the audio band
signaling frequencies, the sinusoid is generated at a
1 kHz rate. The ringing generator is programmed via the
RINGFREQ, RINGAMP, and RINGPHAS registers. The
equations are as follows:

For example, to generate a 60 V

rms

(87 V

), 20 Hz

ringing signal, the equations are as follows:

In addition to the variable frequency and amplitude, a
selectable dc offset (V

OFF

), which can be added to the

waveform, is included. The dc offset is defined in the
RINGOF RAM location.
As with the tone generators, the ringing generator has
two timers which function as described above. They
allow on/off cadence settings up to 8 s on/8 s off. In
addition to controlling ringing cadence, these timers
control the transition into and out of the ringing state.
To initiate ringing, the user must program the
RINGFREQ, RINGAMP, and RINGPHAS RAM
addresses as well as the RINGTA and RINGTI registers
and select the ringing waveshape and dc offset. After
this is done, TAEN and TIEN bits are set as desired.
The ringing state is invoked by a write to the linefeed
register. At the expiration of RINGTA, the Dual
ProSLIC

turns off the ringing waveform and goes to

the on-hook transmission state. At the expiration of
RINGTI, ringing is initiated again. This process
continues as long as the two timers are enabled and the
linefeed register remains in the ringing state.

3.12.2. Internal Trapezoidal Ringing
In addition to the traditional sinusoidal ringing
waveform, the Dual ProSLIC can generate a trapezoidal
ringing waveform similar to the one illustrated in
Figure 26. The RINGFREQ, RINGAMP, and
RINGPHAS RAM addresses are used for programming
the ringing wave shape as follows:
RINGPHAS = 4 x Period x 8000
RINGAMP = (Desired V/160.8 V) x (2

)

RINGFREQ = (2 x RINGAMP)/(t

RISE

x 8000)

RINGFREQ is a value that is added or subtracted from
the waveform to ramp the signal up or down in a linear
fashion. This value is a function of rise time, period, and
amplitude, where rise time and period are related
through the following equation for the crest factor of a
trapezoidal waveform.

where

So, for a 90 V

, 20 Hz trapezoidal waveform with a

crest factor of 1.3, the period is 0.05 s, and the rise time
requirement is 0.015 s.
RINGPHAS = 4 x 0.05 x 8000 = 1600 (0x0640)
RINGAMP = 90/160.8 x (2

) = 18340 (0x47A5)

RINGFREQ = (2 x RINGAMP)/(0.0153 x 8000) = 300
(0x012C)
The time registers and interrupts described in the
sinusoidal ring description also apply to the trapezoidal
ring waveform:

3.13. Internal Unbalanced Ringing

The Si3220 also provides the ability to generate a
traditional battery-backed unbalanced ringing waveform
for ringing terminating devices that require a high dc
content or for use in ground-start systems that cannot
tolerate a ringing waveform on both the TIP and RING
leads. The unbalanced ringing scheme applies the
ringing signal to the RING lead; the TIP lead remains at
the programmed VCM voltage that is very close to
ground. A programmable dc offset can be preset to
provide dc current for ring trip detection. Figure 25
illustrates the internal unbalanced ringing waveform.

coeff

1000Hz

---------------------

RINGFREQ = coeff 2

cos

RINGAMP

1
4

--- 1 coeff

1 coeff

------------------------

(

)

DesiredV

160.173V

---------------------------------

RINGPHAS

coeff

1000Hz

---------------------

0.9921

cos

RINGFREQ

0.9921

(

)

8322461

0x7EFD9D

RINGAMP

1
4

---

00789

1.99211

---------------------

(

)

160.173

---------------------

273

0x111

RISE

3
4

---T 1

-----------

Period

RING

--------------

desired crest factor

Si3220/25

Rev. 1.2

Figure 25. Internal Unbalanced Ringing

To enable unbalanced ringing, set the RINGUNB bit of
the RINGCON register. As with internal balanced
ringing, the unbalanced ringing waveform is generated
by using one of the two on-chip tone generators
provided in the Si3220. The tone generator used to
generate ringing tones is a two-pole resonator with
programmable frequency and amplitude. Since ringing
frequencies are low compared to the audio band
signaling frequencies, the ringing waveform is
generated at a 1 kHz rate.
The ringing generator is programmed via the RINGAMP,
RINGFREQ, and RINGPHAS registers. The RINGOF
register is used in to set the dc offset position around
which the RING lead will oscillate. Unbalanced ringing
is centered at 80 V instead of V

BAT

/ 2. Use the ring

offset register (RINGOF, indirect Register 56) to position
the dc offset as desired. The dc offset is set at a dc point
equal to VCM (80 V + VOFF), where VOFF is the
value that is input into the RINGOF RAM location.
Positive VOFF values will cause the dc offset point to
move closer to ground (lower dc offset), and negative
VOFF values will have the opposite effect. The dc offset
can be set to any value; however, the ringing signal will
be clipped digitally if the dc offset is set to a value that is
less than half the ringing amplitude. In general, the
following equation must hold true to ensure the battery
voltage is sufficient to provide the desired ringing
amplitude:
|V

BATR

| > |V

RING,PK

+ (80 V + V

OFF

) + V

OVRING

It is possible to create reverse polarity unbalanced
ringing waveforms (the TIP lead oscillates while the
RING lead stays constant) by setting the UNBPOLR bit
of the RINGCON register. In this mode, the polarity of
VOFF must also be reversed (in normal ringing polarity
VOFF is subtracted from 80 V, and in reverse polarity,
ringing VOFF is added to 80 V).

3.14. Ringing Coefficients

The ringing coefficients are calculated in decimals for
sinusoidal and trapezoidal waveforms. The RINGPHAS
and RINGAMP hex values are decimal to hex
conversions in 16-bit 2's complement representations
for their respective RAM locations.
To obtain sinusoidal RINGFREQ RAM values, the
RINGFREQ decimal number is converted to a 24-bit 2's
complement value. The lower 12 bits are placed in
RINGFRLO bits 14:3. RINGFRLO bits 15 and 2:0 are
cleared to 0. The upper 12 bits are set in a similar
manner in RINGFRHI, bits 13:3. RINGFRHI bit 14 is the
sign bit, and RINGFRHI bits 2:0 are cleared to 0.
For example, the register values for
RINGFREQ = 0x7EFD9D are as follows:
RINGFRHI = 0x3F78
RINGFRLO = 0x6CE8
To obtain trapezoidal RINGFREQ RAM values, the
RINGFREQ decimal number is converted to an 8-bit, 2's
complement value. This value is loaded into RINGFRHI.
RINGFRLO is not used.

Figure 26. Trapezoidal Ringing Waveform

3.14.1. Ringing DC Offset Voltage
A dc offset voltage can be added to the Si3220's ac
ringing waveform by programming the RINGOF RAM
location to the appropriate setting. The value of
RINGOF is calculated as follows:

RING

TIP

RING

Si3220

DC Offset

GND

TIP

RING

BATR

-80V

OVRING

DC Offset

OFF

TIP-RING

OFF

RISE

T = 1/freq

time

RINGOF

OFF

160.8

--------------- 2

Si3220/25

Rev. 1.2

3.14.2. External Unbalanced Ringing
The Si3225 supports centralized, battery-backed
unbalanced ringing schemes by providing a ringing
relay driver as well as inputs from an external ring trip
circuit. Using this scheme, line-card designers can use
the Dual ProSLIC chipset in existing system
architectures with minimal system changes.
3.14.3. Linefeed Overhead Voltage Considerations

During Ringing

The ringing mode output impedance allows ringing
operation without overhead voltage modification
(VOVR = 0). If an offset of the ringing signal from the
ring lead is desired, VOVR can be used for this
purpose.
3.14.4. Ringing Power Considerations
The total power consumption of the Si3220/Si3200
chipset using internal ringing generation is dependent
on the V

supply voltage, desired ringing amplitude,

total loop impedance, and ac load impedance (number
of REN). The following equations can be used to
approximate the total current required for each channel
during ringing mode:

where:

LOAD

= 7000/REN (for North America)

LOOP

= loop impedance

OUT

= ProSLIC output impedance = 320

DD,OH

= I

overhead current

= 22 mA for V

= 3.3 V

= 26 mA for V

= 5 V

3.15. Ring Trip Detection

A ring trip event signals that the terminal equipment has
transitioned to an off-hook state after ringing has
commenced, ensuring that the ringing signal is removed
before normal speech begins. The Dual ProSLIC is
designed to implement either an ac or dc-based internal
ring trip detection scheme or a combination of both
schemes.

The system design is flexible to address varying loop
lengths of different applications. An ac ring trip detection
scheme cannot reliably detect an off-hook condition
when sourcing longer loop lengths, as the 20 Hz ac
impedance of an off-hook long loop is indistinguishable
from a heavily-loaded (5 REN) short loop in the on-hook
state. Therefore, a dc ring trip detection scheme is
required when sourcing longer loop lengths.
The Si3220 can implement either an ac or dc-based ring
trip detection scheme depending on the application. The
Si3225 allows external dc ring trip detection when using
a battery-backed external ringing generator by
monitoring the ringing feed path through two sensing
inputs on each channel. By monitoring this path, the
Dual ProSLIC detects a dc current flowing in the loop
once the end equipment has gone off-hook. Table 29
provides recommended register and RAM settings for
various applications, and Table 30 lists the register and
RAM addresses that must be written or monitored to
correctly detect a ring trip condition.
Figure 27 illustrates the internal functional blocks that
correctly detect and process a ring trip event. The
primary input to the system is the loop current sense
(ILOOP) value provided by the loop monitoring circuitry
and reported in the ILOOP RAM location register. The
ILOOP RAM location value is processed by the ISP
block when the LFS bits in the linefeed register indicate
the device is in the ringing state. The output of the ISP
then feeds into a pair of programmable, digital low-pass
filters, one for the ac ring trip detection path and one for
the dc path. The ac path also includes a full-wave
rectifier block prior to the LPF block. The outputs of
each low-pass filter block are then passed on to a
programmable ring trip threshold (RTACTH for ac
detection and RTDCTH for dc detection). Each
threshold block output is then fed to a programmable
debounce filter to ensure a valid ring trip event. The
output of each debounce filter remains constant unless
the input remains in the opposite state for the entire
period of time set using the ac and dc ring trip debounce
interval registers, RTACDB and RTDCDB. The outputs
of both debounce filter blocks are then ORed together. If
either the ac or the dc ring trip circuits indicate that a
valid ring trip event has occurred, the RTP bit is set.
Either the ac or dc ring trip detection circuits are
disabled by setting the respective ring trip threshold
sufficiently high so that it does not trip under any
condition. A ring trip interrupt is also generated if the
RTRIPE bit is enabled.

DD,AVE

RING,PK

LOOP

----------------------- 2

---

DD,OH

BAT,AVE

RING,PK

LOOP

----------------------- 2

---

RING,PK

RING,RMS

LOOP

LOAD

OUT

Si3220/25

Rev. 1.2

3.15.1. Ringtrip Timeout Counter
The Dual ProSLIC incorporates a ringtrip timeout
counter, RTCOUNT, that will monitor the status of the
ringing control. When exiting ringing, the Dual ProSLIC
will allow the ringtrip timeout counter a sufficient amount
of time (RTCOUNT x 1.25 ms/LSB) for the mode to
switch to On-hook Transmission or Active. The mode
that is being exited to is governed by whether the
command to exit ringing is a ringing active timer
expiration (on-hook transmission) or ringtrip/manual

mode change (active mode). The ringtrip timeout
counter ensures ringing is exited within its time setting
(RTCOUNT x 1.25 ms/LSB, typically 200 ms).
3.15.2. Ringtrip Debounce Interval
The ac and dc ring trip debounce intervals can be
calculated based on the following equations:
RTACDB = t

debounce

(1600/RTPER)

RTDCDB = t

debounce

(1600/RTPER)

Figure 27. Ring Trip Detect Processing Circuitry

Input

Signal

Processor

Digital

LPF

AC Ring Trip

Threshold

RTPER

LFS

ILOOP

RTACTH

Debounce

Filter_AC

Interrupt

Logic

RTRIPS

RTP

RTRIPE

+
_

DC Ring Trip

Threshold

RTDCTH

Debounce

Filter_DC

RTACDB

RTDCDB

Digital

LPF

Full Wave

Rectifier

Si3220/25

Rev. 1.2

3.15.3. Loop Closure Mask
The Dual ProSLIC implements a loop closure mask to
ensure mode change between ringing and active or on-
hook transmission without causing an erroneous loop
closure detection. The loop closure mask register,
LCRMASK, should be set such that loop closure
detection is ignored for the time (LCRMASK 1.25 ms/
LSB). The programmed time is set to mask detection of
transitional currents that occur when exiting the ringing
mode while driving a reactive load (i.e., 5 REN). A
typical setting is 80 ms (LCRMASK = 0x40).

3.15.4. Si3220 Ring Trip Detection
The Si3220 provides the ability to process a ring trip
event using an ac-based detection scheme. Using this
scheme eliminates the need to add dc offset to the
ringing signal, which reduces the total power dissipation
during the ringing state and maximizes the available
ringing amplitude. This scheme is valid for shorter loop
lengths only since it cannot reliably detect a ring trip
event if the off-hook line impedance overlaps the on-
hook impedance at 20 Hz.

Table 29. Recommended Values for Ring Trip Registers and RAM Addresses

Ringing

Method

Ringing

Frequency

Offset

Added?

RTPER

RTACTH

RTDCTH

RTACDB/

RTDCDB

Internal

(Si3220)

1632 Hz

Yes

800/f

RING

221 x RTPER

0.577(RTPER x V

OFF

)

See Note 2

800/f

RING

1.59 x V

RING,PK

x RTPER

32767

3360 Hz

Yes

2(800/

RING

)

221 x RTPER

0.577(RTPER x V

OFF

)

2(800/

RING

)

1.59 x V

RING,PK

x RTPER

32767

External

(Si3225)

1632 Hz

Yes

800/f

RING

32767

0.067 x RTPER x V

OFF

3360 Hz

Yes

2(800/

RING

)

32767

0.067 x RTPER x V

OFF

Notes:

1. All calculated values should be rounded to the nearest integer.
2. Refer to Ring Trip Debounce Interval for RTACDB and RTDCDB equations.

Table 30. Register and RAM Locations Used for Ring Trip Detection

Parameter

Register/RAM

Mnemonic

Register/RAM

Bits

Programmable

Range

Resolution

Ring Trip Interrupt Pending

IRQVEC2

RTRIPS

Yes/No

N/A

Ring Trip Interrupt Enable

IRQEN2

RTRIPE

Enabled/Disabled

N/A

AC Ring Trip Threshold

RTACTH

RTACTH[15:0]

See Table 29

DC Ring Trip Threshold

RTDCTA

RTDCTH[15:0]

See Table 29

Ring Trip Sample Period

RTPER

RTPER[15:0]

See Table 29

Linefeed Shadow (monitor only)

LINEFEED

LFS[2:0]

N/A

Ring Trip Detect Status
(monitor only)

LCRRTP

RTP

N/A

AC Ring Trip Detect Debounce
Interval

RTACDB

RTACDB[15:0]

0 to 40.96 s

1.25 ms

DC Ring Trip Detect Debounce
Interval

RTDCDB

RTDCDB[15:0]

0 to 40.96 s

1.25 ms

Loop Current Sense
(monitor only)

ILOOP

ILOOP[15:0]

0 to 101.09 mA

See

Table 20

Si3220/25

Rev. 1.2

The Si3220 can also add a dc offset component to the
ringing signal and detect a ring trip event by monitoring
the dc loop current flowing once the terminal equipment
transitions to the off-hook state. Although adding dc
offset reduces the maximum available ringing amplitude
(using the same ringing supply), this method is required
to reliably detect a valid ring trip event when sourcing
longer loop lengths. The dc offset can be programmed
from 0 to 64.32 V in the RINGOF RAM address as
required to produce adequate dc loop current in the off-
hook state. Depending on the loop length and the ring
trip method, the ac or dc ring trip detection circuits are
disabled by setting their respective ring trip thresholds,
RTACTH or RTDCTH, sufficiently high so that they do
not trip under any condition.
3.15.5. Si3225 Ring Trip Detection
The Si3225 implements an external ring trip detection
scheme when using a standard battery-backed external
ringing generator. In this application, the centralized
ringing generator produces an unbalanced ringing
signal that is distributed to individual TIP/RING pairs. A
per-channel ringing relay is required to disconnect the
Si3225 from the TIP/RING pair and apply the ringing
signal. By monitoring the ringing feed path across a ring
feed sense resistor (R

RING

in Figure 31 on page 59) in

series with the ringing source, the Si3225 can detect the
dc current path created when the hook switch inside the
terminal equipment closes. The internal ring trip
detection circuitry is identical to that illustrated in
Figure 27. Figure 31 illustrates the typical external ring
trip circuitry required for the Si3225. Because of the
long loop nature of these applications, a dc ring trip
detection scheme is typically used. The user can
disable the ac ring trip detection circuitry by setting the
RTACTH threshold sufficiently high so it does not trip
under any condition.

3.16. Relay Driver Considerations

The Dual ProSLIC devices include up to three
dedicated relay drivers to drive external ringing and/or
test relays. Test relay drivers TRD1a, TRD1b, TRD2a,
and TRD2b are provided in all product versions, and
ringing relay drivers RRDa and RRDb are included for
the Si3225 only. In most applications, the relay can be
driven directly from the Dual ProSLIC with no external
relay drive circuitry required. Figure 28 illustrates the
internal relay driver circuitry using a 3 V or 5 V relay.

Figure 28. Dual ProSLIC Internal Relay Drive

Circuitry

The internal driver logic and drive circuitry are powered
by the same V

supply as the chip's main V

supply

DD1

DD4

pins). When operating external relays from

a V

supply equal to the chip's V

supply, an internal

diode network provides protection against overvoltage
conditions from flyback spikes when the relay is
opened. Either 3 V or 5 V relays can be used in the
configuration shown in Figure 28, and either polarized
or non-polarized relays are acceptable if the V

and

supplies are identical. The input impedance, R

, of

the relay driver pins is a constant 11

while sinking

less than the maximum rated 85 mA into the pin.
If the operating voltage of the relay (V

) is higher than

the Dual ProSLIC V

supply voltage, an external drive

circuit is required to eliminate leakage from V

to V

through the internal protection diode. In this
configuration, a polarized relay will provide optimal
overvoltage protection and minimal external
components. Figure 29 illustrates the required external
drive circuit, and Table 31 provides recommended
values for R

DRV

for typical relay characteristics and V

supplies. The output impedance, R

OUT

, of the relay

driver pins is a constant 63

while sourcing less than

the maximum rated 28 mA out of the pin.

Si3220/

Si3225

Relay

Driver

Logic

GDD

RRDa/b

TRD1a/b
TRD2a/b

3 V/5 V Relay

(polarized or

non-polarized)

Si3220/25

Rev. 1.2

Figure 31. Si3225 External Ring Trip Circuitry

3.16.1. Ringing Relay Activation During Zero

Crossings

The Si3225 is for applications that use a centralized
ringing generator and a per-channel ringing relay to
connect the ringing signal to the TIP/RING pair. The
Si3225 has one relay driver output per channel (RRDa
and RRDb) that can drive a mechanical or solid-state
DPDT relay. To reduce impulse noise that can couple
into adjacent lines, the relay should be closed when
there is zero voltage across the relay contacts and
opened during periods when there is zero current
through the contacts.
3.16.2. Closing the Relay at Zero Voltage
Internal voltage monitoring circuitry closes the relay at
zero voltage with respect to the line voltage. By
observing the phase of the ringing signal and constantly
monitoring the open-circuit T-R voltage, V

, the

Si3225 can detect the next time when there is zero
voltage across the relay contacts.
3.16.3. Opening the Relay at Zero Current
Opening the ringing relay at zero current also is
accomplished using the internal monitoring circuitry and
prevents arcing from excess current flow when the relay
contacts are opened. The current flowing through the
ringing relay is continuously monitored in the IRNGNG
RAM address, and two internal counters (COUNTER0
and COUNTER1) detect time elapsed since the last two
zero current crossings based on the ringing period and
predict when the next zero crossing occurs. The ringing
relay current and internal counters are both updated at
an 8 kHz rate. To account for the mechanical delay of
the relay, a programmable advance firing timer allows
the user to initiate relay opening up to 10 ms prior to the
zero current crossing event. Figure 30 illustrates the

timing sequence for a typical ringing relay control
application.
During a typical ringing sequence, the Si3225 monitors
both the ringing relay current (IRNGNG) and the
RINGEN bit of the RINGCON register. The RINGEN bit
toggles because of pre-programmed ringing cadence or
a change in operating state. COUNTER0 and
COUNTER1 are restarted at each alternating zero
current crossing event, and the delay period,
ZERDELAY, equal to the ringing frequency period less
the desired advance firing time, D, is entered by the
user. If either counter reaches the same value as
ZERDELAY, the relay control signal is enabled when the
RINGEN bit transition has already occurred. During
typical ringing bursts, the LFS bits of the linefeed
register toggle between the RINGING and OHT states
based on the pre-programmed ringing cadence. The
transition from OHT to RINGING is synchronized with
the RRD state transitions, so the ringing burst starts
immediately. The transition from RINGING to OHT is
gated by a user-programmed delay period, LFSDELAY,
which ensures the ringing burst has ceased before
going to the OHT state or to the ACTIVE state in
response to a linefeed state change.

3.17. Polarity Reversal

The Dual ProSLIC devices support polarity reversal for
message-waiting functionality and various signaling
modes. The ramp rate can be programmed for a smooth
transition or an abrupt transition to accommodate
different application requirements. A wink function is
provided for special equipment that responds to a
smooth ramp to V

= 0 V. Table 32 illustrates the

RING

OFF

806 k

510

Si3200

RING

TIP

Protection

Si3225

k
R

I
N

RTRP

Relay

Hook

Switch

Phone

VDD

RRD

Si3220/25

Rev. 1.2

Setting the linefeed register to the opposite polarity
immediately reverses (hard reversal) the line polarity.
For example, to transition from Forward Active mode to
Reverse Active mode changes LF[2:0] from 001 to 101.
Polarity reversal is accommodated in the OHT and
ground start modes. The POLREV bit is a read-only bit
that reflects if the device is in polarity reversal mode.
For smooth polarity reversal, set the PREN bit to 1 and
the RAMP bit to 0 or 1 depending on the desired ramp
rate (see Table 32). Polarity reversal is then
accomplished by toggling the linefeed register from
forward to reverse modes as desired.

A wink function slowly ramps down the TIP-RING
voltage (V

) to 1 followed by a return to the original

VOC value (set in the VOC RAM location). This scheme
lights a message-waiting lamp in certain handsets. No
change to the linefeed register is necessary to enable
this function. Instead, the user sets the VOCZERO bit to
1 so that the TIP-RING voltage collapses to 0 V at the
rate programmed by the RAMP bit. Setting the
VOCZERO bit back to 0 returns the TIP-RING voltage
to its normal setting. With a software timer, the user can
automate the cadence of the wink function. Figure 32
illustrates the wink function.

Figure 32. Wink Function with Programmable Ramp Rate

Table 32. Register and RAM Locations used for Polarity Reversal

Parameter

Programmable Range

Register/RAM

Bits

Register/RAM

Mnemonic

Linefeed See

Table 17

LF[2:0]

LINEFEED

Polarity Reversal Status

Read only

POLREV

Wink Function
(Smooth transition to Voc=0V)

1 = Ramp to 0 V
0 = Return to previous V

VOCZERO

POLREV

Smooth Polarity Reversal Enable

0 = Disabled
1 = Enabled

PREN

POLREV

Smooth Polarity Reversal Ramp
Rate

0 = 1 V/125 µs
1 = 2 V/125 µs

RAMP

POLREV

TIP/RING

(V)

-10

-20

-30

-40

-50

Time (ms)

2 V/125 µs slope

set by RAMP bit

Set VOCZERO bit to 1

Set VOCZERO bit to 0

TIP

BAT

RING

Si3220/25

Rev. 1.2

3.18. Two-Wire Impedance Synthesis

Two-wire impedance synthesis is performed on-chip to
optimally match the output impedance of the Dual
ProSLIC to the impedance of the subscriber loop thus
minimizing the receive path signal reflected back onto
the transmit path. The Dual ProSLIC chipset provides
on-chip, digitally-programmable, two-wire impedance
synthesis to meet return loss requirements against
virtually any global two-wire impedance requirement.
Real and complex two-wire impedances are realized by
a programmable digital filter block. (See Z

and Z

blocks in Figure 11 on page 24.)

Figure 33. Two-Wire Impedance Synthesis

Configuration

The two-wire impedance is programmed by loading the
desired real or complex impedance value into the
Si322X coefficient generator software in the format R

||C

, as shown in Figure 33. The software calculates

the appropriate hex coefficients and loads them into the
appropriate control registers (registers 3352). The two-
wire impedance can be set to any real or complex value
within the boundaries set in Table 33. The actual
impedance presented to the subscriber loop varies with
series impedance from protection devices placed
between the Dual ProSLIC chipset outputs and the TIP/
RING pair according to the following equation:

Where:

is the termination impedance presented to the

TIP/RING pair
R

PROT

is the series resistance caused by protection

devices
R

is the series portion of the synthesized

impedance
R

||C

is the parallel portion of the synthesized

impedance

The user must enter the value of R

PROT

into the

software so the equalizer block can compensate for
additional series impedance. (See Figure 11 on page
24.) Figure 34 illustrates the simplified two-wire
impedance circuit including external protection
resistors, where Z

is the actual line impedance for the

specific geographical region. The Dual ProSLIC devices
can accomodate up to 50

of series protection

impedance per leg.
The ac impedance generation scheme is comprised of
analog and DSP-based coefficients. To turn off the
analog coefficients (RS, ZP, and ZZ bits in the ZRS and
ZZ registers), the user can simply set the ZSDIS bit of
the ZZ register to 0. To turn off the DSP coefficients
(ZA1H1 through ZB3LO registers), each register must
be loaded with 0x00.

Figure 34. Two-Wire Impedance Simplified

Circuit

3.18.1. Impedance Synthesis Initialization

and Control

The Si322x utilizes a digital IIR filter to implement SLIC
impedance synthesis. Under normal operation, the
Si322x state machine controls the clocks to this filter
automatically such that the filter clocks are turned OFF
during those times when the filter is not required. During
pulse dialing, for example, the clocks are shut OFF
during the break period and turned back ON during the
make period.
When the clocks are shut OFF, the IIR filter holds the
last sample values in its storage elements. When the

Table 33. Two-Wire Impedance

Synthesis Limitations

Desired
Configuration

Programmable Limits

only

1001000

+ C

x C

> 0.5 ms

+ R

||C

/(R

+ R

) > 0.1

PROT

(

)

Dual

ProSLIC

PROT

Si3

200

TIP

RING

Si3220/25

Rev. 1.2

clocks are turned back ON, the IIR filter experiences a
discontinuity in the input signal.
By writing power-down register 124 (decimal) with
0xC0, the clocks to the digital synthesis filter are forced
to be continuously ON at all times, and the TX audio
path is also kept ON so that the IIR filter continues to
run and receive continuous signal samples from the TX
channel no matter what state the SLIC is in.
Register 124 is a protected register, which must be
unlocked, then written, then locked again to prevent
unintended modification of its contents. The sequence
to write register 124 is as follows:
1. 0x2, 0x6, 0xC, 0x0 -> Reg.87 (decimal)

\\unlock protected registers

2. 0xC0 -> Reg.124 (decimal)

\\force HSP (high-speed processing) clocks to ON

3. 0x2, 0x6, 0xC, 0x0 -> Reg.87 (decimal)

\\lock protected registers

To ensure proper device operation, the digital
impedance synthesis coefficients (registers 33-52,
decimal) should be programmed while the LINEFEED
state is set to zero (OPEN) and register 124 is set to
0x80. After loading the digital impedance synthesis
coefficients, register 124 should be set to 0xC0. The
following sequence should always be used to program
the digital impedance synthesis coefficients:
Channel A
1. 0x2, 0x6, 0xC, 0x0

Reg. 87 (decimal) ;unlock

protected registers

2. 0x80

Reg. 124 (decimal) ;disable clock

Channel B
3. 0x80

Reg. 124 (decimal) ;disable clock

Both channels
4. Write registers 33152 with the digital impedance

synthesis coefficients

Channel A
5. 0xC0

Reg. 124 (decimal) ;enable clock

Channel B
6. 0xC0

Reg. 124 (decimal) ;enable clock

7. 0x2, 0x6, 0xC, 0x0

Reg. 87 (decimal) ;lock

protected registers

During device initialization, steps 1, 5, 6, and 7 should
always be performed even if the digital impedance
synthesis coefficients are not programmed.

3.19. Transhybrid Balance Filter

The Dual ProSLIC devices provide a transhybrid
balance function via a digitally-programmable balance
filter block. (See "H" block in Figure 11.) The Dual
ProSLIC devices implement an 8-tap FIR filter and a
second-order IIR filter, both running at a 16 kHz sample
rate. These two filters combine to form a digital replica
of the reflected signal (echo) from the transmit path
inputs. The user can filter settings on a per-line basis by
loading the desired impedance cancellation coefficients
into the appropriate registers. The Si322x Coefficient
Generator software interface is provided for calculating
the appropriate coefficients for the FIR and IIR filter
blocks.
The transhybrid balance filters can be disabled to
implement loopback diagnostic modes. To disable the
transhybrid balance filter (zero cancellation), set the
HYBDIS bit in the DIGCON register to 1.

Note: The user must enter values into each register location

to ensure correct operation when the hybrid balance
block is enabled.

3.20. Tone Generators

Dual ProSLIC devices have two digital tone generators
that allow a wide variety of single or dual tone frequency
and amplitude combinations that spare the user the
effort of generating the required POTS signaling tones
on the PCM highway. DTMF, FSK (caller ID), call
progress, and other tones can all be generated on-chip.
The tones are sent to the receive or transmit paths.
(See Figure 11 on page 24.)
3.20.1. Tone Generator Architecture
A simplified diagram of the tone generator architecture
is shown in Figure 35. The oscillator, active/inactive
timers, interrupt block, and signal routing block are
connected for flexibility in creating audio signals.
Control and status register bits are placed in the figure
to indicate their association with the tone generator
architecture. The register set for tone generation is
summarized in Table 34.

Si3220/25

Rev. 1.2

Figure 35. Tone Generator Diagram

3.20.2. Oscillator Frequency and Amplitude
Each of the two tone generators contains a two-pole
resonant oscillator circuit with a programmable
frequency and amplitude, which are programmed via
RAM addresses OSC1FREQ, OSC1AMP, OSC1PHAS,
OSC2FREQ, OSC2AMP, and OSC2PHAS. The sample
rate for the two oscillators is 8000 Hz. The equations
are as follows:

coeff

= cos(2

/8000 Hz),

where f

is the frequency to be generated;

OSCnFREQ = coeff

x (2

);

where Desired Vrms is the amplitude to be generated;

OSCnPHAS = 0,

n = 1 or 2 for oscillator 1 or oscillator 2, respectively.
For example, to generate a DTMF digit of 8, the two
required tones are 852 Hz and 1336 Hz. Assuming we
want to generate half-scale values (ignoring twist), the
following values are calculated:

OSC1PHAS = 0
coeff

= cos (2

1336 / 8000) = 0.49819

OSC2FREQ = 0.49819 (2

) = 8162 = 0x1FE2

OSC2PHAS = 0
The preceding computed values are written to the
corresponding registers to initialize the oscillators. Once
the oscillators are initialized, the oscillator control
registers can be accessed to enable the oscillators and
direct their outputs.
FSK frequency coefficients, FSKFREQ0/1 and
FSKAMP0/1, are calculated from the oscillator
equations and changing the sample rate from 8000 Hz
to 24000 Hz.
3.20.3. Tone Generator Cadence Programming
Each of the two tone generators contains two timers,
one for setting the active period and one for setting the
inactive period. The oscillator signal is generated during
the active period and suspended during the inactive
period. Both the active and inactive periods can be
programmed from 0 to 8 seconds in 125 µs steps. The
active period time interval is set using OSC1TA for tone
generator 1 and OSC2TA for tone generator 2.

ZEROENn

ENSYNCn

*Tone Generator 1 Only

n = "1" or "2" for Tone Generator 1 and 2, respectively

Two-Pole

Resonant

Oscillator

16-Bit

Modulo

Counter

OSCnTA

OSCnTI

OSCnTIEN

OSCnTAEN

OSCnFREQ

OSCnPHAS

OSCnAMP

Load

Logic

Zero

Cross

Logic

Signal

Routing

ROUTn

to TX Path

to RX Path

INT

Logic

OSnTIS

OSnTIE

INT

Logic

OSnTAS

OSnTAE

REL*

Load

Enable

8 kHz
Clock

Zero Cross

OSCnEN

OSCnTA

Expire

OSCnTI

Expire

8 kHz
Clock

OSCnAMP

1
4

--- 1 coeff

1 coeff

------------------------

(

)

Desired Vrms

1.11 Vrms

----------------------------------------

coeff

852

8000

-----------------

cos

0.78434

OSC1FREQ

0.78434 2

(

)

12851

0x3233

OSC1AMP

1
4

--- 0.21556

1.78434

---------------------

(

)

0.5

1424

0x590

OSC2AMP

1
4

--- 0.50181

1.49819

---------------------

(

)

0.5

2370

0x942

Si3220/25

Rev. 1.2

To enable automatic cadence for tone generator 1,
define the OSC1TA and OSC1TI registers and set the
OSC1TAEN and OSC1TIEN bits. This enables each of
the timers to control the state of the oscillator enable bit,
OSC1EN. The 16-bit counter counts until the active
timer expires, at which time the 16-bit counter resets to
zero and begins counting until the inactive timer
expires. The cadence continues until the user clears the
OSC1TA and OSC1TIEN control bits. Setting the
ZEROEN1 bit implements the zero crossing detect
feature. This ensures that each oscillator pulse ends
without a dc component. The timing diagram in

Figure 36 is an example of an output cadence that uses
the zero crossing feature.
One-shot oscillation is possible with OSC1EN and
OSC1TAEN. Direct control over the cadence is
achieved by setting the OSC1EN bit directly if
OSC1TAEN and OSC1TIEN are disabled.
The operation of tone generator 2 is identical to that of
tone generator 1 using its respective control registers.

Note: Tone Generator 2 should not be enabled simulta-

neously with the ringing oscillator because of resource
sharing within the hardware.

Table 34. Register and RAM Locations Used for Tone Generation

Tone Generator 1

Parameter

Register/RAM

Mnemonics

Register/RAM Bits

Description/Range

(LSB Size)

Oscillator 1 Frequency
Coefficient

OSC1FREQ

OSC1FREQ[15:3]

Sets oscillator frequency

Oscillator 1 Amplitude Coeffi-
cient

OSC1AMP

OSC1AMP[15:0]

Sets oscillator amplitude

Oscillator 1 Initial Phase
Coefficient

OSC1PHAS

OSC1PHAS[15:0]

Sets initial phase

(default = 0)

Oscillator 1 Active Timer

O1TALO/O1TAHI

OSC1TA[15:0]

0 to 8.19 s (125 µs)

Oscillator 1 Inactive Timer

O1TILO/O1TIHI

OSC1TI[15:0]

0 to 8.19 s (125 µs)

Oscillator 1 Control

OMODE, OCON

FSKSSEN, OSC1FSK,

ZEROEN1, ROUT1,

ENSYNC1, OSC1TAEN,

OSC1TIEN, OSC1EN

Enables all Oscillator 1

parameters

Oscillator 1 Interrupts

IRQVEC1, IRQEN1 OS1TAS, OS1TIS, OS1TAE,

OS1TIE

Interrupt enable/status

Tone Generator 2

Parameter

Location

Register/RAM Address

Description/Range

Oscillator 2 Frequency
Coefficient

OSC2FREQ

OSC2FREQ[15:3]

Sets oscillator frequency

Oscillator 2 Amplitude Coeffi-
cient

OSC2AMP

OSC2AMP[15:0]

Sets oscillator amplitude

Oscillator 2 Initial Phase
Coefficient

OSC2PHAS

OSC2PHAS[15:0]

Sets initial phase

(default = 0)

Oscillator 2 Active Timer

O2TALO/O2TAHI

OSC2TA[15:0]

0 to 8.19 s (125 µs)

Oscillator 2 Inactive Timer

O2TILO/O2TIHI

OSC2TI[15:0]

0 to 8.19 s (125 µs)

Oscillator 2 Control

OMODE, OCON

ZEROEN2, ROUT2,

ENSYNC2, OSC2TAEN,

OSC2TIEN, OSC2EN

Enables all Oscillator 2

parameters

Oscillator 2 Interrupts

IRQVEC1, IRQEN1

OS2TAS, OS2TIS,

OS2TAE, OS2TIE

Interrupt enable/status

Si3220/25

Rev. 1.2

3.20.4. Tone Generator Interrupts
Both the active and inactive timers can generate an
interrupt to signal "on/off" transitions to the software.
The timer interrupts for tone generator 1 can be
individually enabled by setting the OS1TAE and OS1TIE
bits. Timer interrupts for tone generator 2 are OS2TAE
and OS2TIE. A pending interrupt for each of the timers
is determined by reading the OS1TAS, OS1TIS,
OS2TAS, and OS2TIS bits in the IRQVEC1 register.

3.21. Caller ID Generation

The Dual ProSLIC devices generate caller ID signals in
compliance with various Bellcore and ITU specifications
as described in Table 35 by providing continuous phase
binary frequency shift keying (FSK) modulation.
Oscillator 1 is required because it preserves phase
continuity during frequency shifts whereas Oscillator 2
does not. Figure 37 illustrates a typical caller ID
transmission sequence in accordance with Bellcore

requirements.
The register and RAM locations for caller ID generation
are listed in Table 36. Caller ID data is entered into the
8-bit FSKDAT register. The data byte is double buffered
so that the Dual ProSLIC can generate an interrupt
indicating the next data byte can be written when
processing begins on the current data byte. The caller
ID data can be transmitted in one of two modes
controlled by the O1FSK8 register bit. When
O1FSK8 = 0 (default case), the 8-bit caller ID data is
transmitted with a start bit and stop bit to create a 10-bit
data sequence. If O1FSK8 = 1, the caller ID data is
transmitted as a raw 8-bit sequence with no start or stop
bits. The value programmed into the OSC1TA register
determines the bit rate, and the interrupt rate is equal to
the bit rate divided by the data sequence length (8 or 10
bits).

Table 35. FSK Modulation Requirements

Parameter

ITU-T V.23 Bellcore GR-30-CORE

Mark Frequency (logic 1)

1300 Hz

1200 Hz

Space Frequency (logic 0)

2100 Hz

2200 Hz

Transmission Rate

1200 baud

Table 36. Register and RAM Locations used for Caller ID Generation

Parameter

Register/RAM

Mnemonic

Register/RAM Bits

Description/Range (LSB Size)

FSK Start & Stop Bit Enable

OMODE

O1FSK8

Enable/disable

Oscillator 1 Active Timer

O1TALO/O1TAHI

OSC1TA[15:0]

0 to 2.73 s (41.66 µs)*

FSK Data Byte

FSKDAT

FSKDAT[7:0]

Caller ID data

FSK Frequency for Space

FSKFREQ0

FSKFREQ0[15:3]

Audio range

FSK Frequency for Mark

FSKFREQ1

FSKFREQ1[15:3]

Audio range

FSK Amplitude for Space

FSKAMP0

FSKAMP0[15:3]

FSK Amplitude for Mark

FSKAMP1

FSKAMP1[15:3]

FSK 0-1 Transition Freq, High

FSK01HI

FSK01HI[15:3]

FSK 0-1 Transition Freq, Low

FSK01LO

FSK01LO[15:3]

FSK 1-0 Transition Freq, High

FSK10HI

FSK10HI[15:3]

FSK 1-0 Transition Freq, Low

FSK10LO

FSK10LO[15:3]

*Note: Oscillator 1 active timer range and LSB stage valid only for FSK mode.

Si3220/25

Rev. 1.2

3.22. Pulse Metering Generation

The Si3220 offers an additional tone generator to
generate tones above the audio frequency band. This
oscillator generates billing tones that are typically
12 kHz or 16 kHz. The generator follows the same
algorithm as described in "3.20.1. Tone Generator
Architecture" on page 62 with the exception that the
sample rate for computation is 64 kHz instead of 8 kHz.
The equation is as follows:

where Full Scale V

= 0.5 V.

The pulse metering oscillator has a volume envelope
(linear ramp) on the on/off transitions of the oscillator.
The ramp is controlled by the value in the PMRAMP
RAM address, and the sinusoidal generator output is
multiplied by this volume before it is sent to the pulse
metering DAC. The volume value is incremented by the
value in PMRAMP at an 8 kHz rate. The volume will
ramp from 0 to 7FFF in increments of PMRAMP to allow
the value of PMRAMP to set the slope of the ramp. The
clip detector stops the ramp once the signal seen at the
transmit path exceeds the amplitude threshold set by
PMAMPTH, which provides an automatic gain control
(AGC) function to prevent the audio signal from clipping.
When the pulse metering signal is turned off, the
volume ramps down to 0 by decrementing according to
the value of PMRAMP. Figure 38 illustrates the
functional blocks involved in pulse metering generation,
and Table 37 presents the required register and RAM
locations that must be set to generate pulse metering
signals.

Coeff

64000 Hz

--------------------------

cos

PMFREQ

coeff

(

)

PMAMPL

1
4

--- 1 coeff

1 coeff

------------------------

(

)

Desired V

FullScale V

----------------------------------------

Table 37. Register and RAM Locations Used for Pulse Metering Generation

Parameter

Register/RAM

Mnemonic

Register/RAM

Bits

Description/Range

(LSB Size)

Pulse Metering Frequency
Coefficient

PMFREQ

PMFREQ[15:3]

Sets oscillator frequency

Pulse Metering Amplitude
Coefficient

PMAMPL

PMAMPL[15:0]

Sets oscillator amplitude

Pulse Metering Attack/Decay
Ramp Rate

PMRAMP

PMRAMP[15:0]

0 to PMAMPL

(full amplitude)

Pulse Metering Active Timer

PMTALO/PMTAHI

PULSETA[15:0]

0 to 8.19 s (125 µs)

Pulse Metering Inactive Timer

PMTILO/PMTIHI

PULSETI[15:0]

0 to 8.19 s (125 µs)

Pulse Metering, Control
Interrupt

IRQVEC1, IRQEN1

PULSTAE,

PULSTIE,

PULSTAS,

PULSTIS

Interrupt Status and control

registers

Pulse Metering AGC
Amplitude Threshold

PMAMPTH

PMAMPTH[15:0]

0 to 500 mV

PM Waveform Present

PMCON

ENSYNC

Indicates signal present

PM Active Timer Enable

PMCON

TAEN

Enable/disable

PM Inactive Timer Enable

PMCON

TIEN

Enable/disable

Pulse Metering Enable

PMCON

PULSE1

Enable/disable

Si3220/25

Rev. 1.2

Figure 38. Pulse Metering Generation Block Diagram

3.23. DTMF Detection

On-chip DTMF detection, also known as touch tone, is
available in the Si3220 and Si3225.
It is an in-band signaling system that replaces the pulse-
dial signaling standard. In DTMF, two tones generate a
DTMF digit. One tone is chosen from the four possible
row tones, and one tone is chosen from the four
possible column tones. The sum of these tones
constitutes one of 16 possible DTMF digits. The row
and column tones and corresponding digits are shown
in Table 38.
DTMF detection is performed using a modified Goertzel
algorithm to compute the DFT for each of the eight
DTMF frequencies and their second harmonics. At the
end of the DFT computation, the squared magnitudes of
the DFT results for the 8 DTMF fundamental tones are
computed. The row results are sorted to determine the
strongest row frequency, and the column frequencies
are sorted as well. Upon completion of this process,
checks are made to determine if the strongest row and
column tones constitute a DTMF digit.

The detection process occurs twice within the 45 ms
minimum tone time. A digit must be detected on two
consecutive tests after a pause to be recognized as a
new digit. If all tests pass, an interrupt is generated, and
the DTMF digit value is loaded into the DTMF register
according to Table 38. If tones occur at the maximum
rate of 100 ms per digit, the interrupt must be serviced
within 85 ms so that the current digit is not overwritten
by a new one. There is no buffering of the digit
information.

Decimation

Filter

ADC

DAC

Pulse

Metering

DAC

Pulse

Metering

Oscillator

Volume

PMRAMP

Peak Detector

PMAMPTH

BUF

8 kHz

7FFF

or 0

Clip

Logic

12/16 kHz
Bandpass

Table 38. DTMF Row/Column Tones

697 Hz

770 Hz

852 Hz

941 Hz

1209 Hz

1336 Hz

1477 Hz

1633 Hz

Si3220/25

Rev. 1.2

Table 39 outlines the hex codes corresponding to the
detected DTMF digits.

3.24. Modem Tone Detection

The Dual ProSLIC devices are capable of detecting a
2100 Hz modem tone as described in ITU-T
Recommendation V.8. The detection scheme can be
implemented in both transmit and receive paths and is
enabled by programming the appropriate register bit.
The detection scheme should be disabled for power
conservation after the modem tone window has passed.
Once a valid modem tone is detected, a register bit is
set accordingly, and the user can check the results by
reading the register value. A programmable debounce
interval is provided to eliminate false detection and can
be programmed in increments of 67 ms by writing to the
appropriate register.
The outputs of the 2100 Hz modem tone detectors are
located at RAM addresses 410 and 413 for the TX and
RX paths, respectively.
The contents of registers 410 and 413 indicate the
presence or absence of 2100 Hz energy. Table 40
indicates the relationship between the contents of these
RAM addresses and the level of the 2100 Hz energy
present in the corresponding signal path (TX or RX).

The threshold for declaring the presence or absence of
2100 Hz energy should be based on Table 40. A
suitable threshold for most applications is >0x20,
corresponding to a level of 15 dBm.

The following steps are used to access RAM address
410 and 413:
1. Write 0x02, 0x06, 0x0C, 0x00 to Reg. 87 (un-protect

test registers/bits)

2. Write 0x40 to Reg. 4 (access upper RAM space)
3. Write 0x02, 0x06, 0x0C, 0x00 to Reg. 87 (protect

test registers/bits)

4. For TX path use RAMAddress = 154 for the RX path

use RAMAddress = 157:
if (readRAM(RAMAddress) > 0x20)
Tone2100 Hz = 1;
else Tone2100 Hz = 0;
endif

3.25. Audio Path Processing

Unlike traditional SLICs, the Dual ProSLIC devices
integrate the codec function into the same IC. The on-
chip 16-bit codec offers programmable gain/attenuation
blocks and multiple loopback modes for self testing. The
signal path block diagram is shown in Figure 11 on page
24.
3.25.1. Transmit Path
In the transmit path, the analog signal fed by the
external ac coupling capacitors is passed through an
anti-aliasing filter before being processed by the A/D
converter. An analog mute function is provided directly
prior to the A/D converter input. The output of the A/D
converter is an 8 kHz, 16-bit wide, linear PCM data
stream. The standard requirements for transmit path

Table 39. DTMF Hex Codes

Digit

Hex code

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

0x0

Table 40. 2100 Hz Level vs. RAM Hex Value

TIP and RING

Level

Across 600 W

(dBm)

TX Path: RAM 410 (154)

RX Path: RAM 413 (157)

(Hex)

0x838

0x420

0x20a

0x107

0x83

0x41

0x20

Si3220/25

Rev. 1.2

attenuation for signals above 3.4 kHz are part of the
combined decimation filter characteristic of the A/D
converter. One more digital filter, THPF, is available in
the transmit path. THPF implements the high-pass
attenuation requirements for signals below 65 Hz. An
equalizer block then equalizes the transmit signal path
to compensate for series protection resistance, R

PROT

outside of the ac-sensing inputs. The linear PCM data
stream output from the equalizer block is amplified by
the transmit-path programmable gain amplifier, TPGA,
which can be programmed from

to 6 dB. The DTMF

decoder receives the linear PCM data stream and
performs the digit extraction if enabled by the user. The
final step in the transmit path signal processing is the
A-law or µ-law compression, which can reduce the data
stream word width to 8 bits. Depending on the PCM
mode select register selection, every 8-bit compressed
serial data word occupies one time slot on the PCM
highway, or every 16-bit uncompressed serial data
word occupies two time slots on the PCM highway.
3.25.2. Receive Path
In the receive path, the optionally-compressed 8-bit
data is first expanded to 16-bit words. The PCMF
register bit can bypass the expansion process so that
two 8-bit words are assembled into one 16-bit word.
RPGA is the receive path programmable gain amplifier,
which can be programmed from

dB to 6 dB. An

8 kHz, 16-bit signal is then provided to a D/A converter.
An analog mute function is provided directly after the
D/A converter. When not muted, the resulting analog
signal is applied at the input of the transconductance
amplifier, Gm, which drives the off-chip current buffer,
I

BUF

3.25.3. TPGA/RPGA Gain/Attenuation Blocks
The TPGA and RPGA blocks are essentially linear
multipliers with the structure illustrated in Figure 39.
Both blocks can be independently programmed from

to +6 dB (0 to 2 linear scale). The TXGAIN and RXGAIN
RAM locations are used to program each block. A
setting of 0000h mutes all audio signals; a setting of
4000h passes the audio signal with no gain or
attenuation (0 dB), and a setting of 7FFFh provides the
maximum 6 dB of gain to the incoming audio signal. The
device signal scaling assumes that dBm is always
referenced to 600

. To compensate for this, the correct

RXGAIN and TXGAIN settings are given in the
coefficient generator software. The DTXMUTE and
DRXMUTE bits in the DIGCON register are also
available to allow muting of the transmit and receive
paths without requiring modifications to the TXGAIN or
RXGAIN settings.

3.25.4. TXEQ/RXEQ Equalizer Blocks
The TXEQ and RXEQ blocks (see Figure 11 on page
24) represent 4-tap filters that can be used to equalize
the transmit and receive paths, respectively. The
transmit path equalizer is controlled by the TXEQCO0-
TXEQCO3 RAM locations, and the receive path
equalizer is controlled by the RXEQCO0-RXEQCO3
RAM locations. The Si322x Coefficient Generator
software uses these filters in calculating the ac
impedance coefficients for optimal ac performance.
Refer to "AN63: Si322x Coefficient Generator User's
Guide" for detailed information regarding the calculation
of ac impedance coefficients.

Figure 39. TPGA and RPGA structure

3.25.5. Audio Characteristics
The dominant source of distortion and noise in both the
transmit and receive paths is the quantization noise
introduced by the µ-law or the A-law compression
process. Figure 5 on page 20 specifies the minimum
Signal-to-Noise and Distortion Ratio for either path for a
sine wave input of 200 Hz to 3400 Hz.
Both the µ-law and the A-law speech encoding allow the
audio codec to transfer and process audio signals larger
than 0 dBm0 without clipping. The maximum PCM code
is generated for a µ-law encoded sine wave of
3.17 dBm0 or an A-law encoded sine wave of
3.14 dBm0. The device overload clipping limits are
driven by the PCM encoding process. Figure 6 on page
21 shows the acceptable limits for the analog-to-analog
fundamental power transfer-function, which bounds the
behavior of the device.
The transmit path gain distortion versus frequency is
shown in Figure 7 on page 21. The same figure also
presents the minimum required attenuation for out-of-
band analog signals applied on the line. The presence
of a high-pass filter transfer function ensures at least
30 dB of attenuation for signals below 65 Hz. The low-
pass filter transfer function attenuates signals above
3.4 kHz. It is implemented as part of the A-to-D
converter.

TPGA or RPGA

PCM

Out

where M = {0, 1/16384, 2/16384,...32767/16384}

Si3220/25

Rev. 1.2

The receive path transfer function requirement, shown
in Figure 8 on page 22, is very similar to the transmit
path transfer function. The PCM data rate is 8 kHz; so,
no frequencies greater than 4 kHz are digitally-encoded
in the data stream. At frequencies greater than 4 kHz,
the plot in Figure 8 is interpreted as the maximum
allowable magnitude of spurious signals that are
generated when a PCM data stream representing a sine
wave signal in the range of 300 Hz to 3.4 kHz at a level
of 0 dBm0 is applied at the digital input.
The group delay distortion in either path is limited to no
more than the levels indicated in Figure 9 on page 23.
The reference in Figure 9 is the smallest group delay for
a sine wave in the range of 500 Hz to 2500 Hz at
0 dBm0.
The block diagram for the voice-band signal processing
paths is shown in Figure 11 on page 24. Both the
receive and the transmit paths employ the optimal
combination of analog and digital signal processing for
maximum performance while maintaining sufficient
flexibility for users to optimize their particular application
of the device. The two-wire (TIP/RING) voice-band
interface to the device is implemented with a small
number of external components. The receive path
interface consists of a unity-gain current buffer, I

BUF

while the transmit path interface is an ac coupling
capacitor. Signal paths, although implemented
differentially, are shown as single-ended for simplicity.

3.26. System Clock Generation

The Dual ProSLIC devices generate the internal clock
frequencies from the PCLK input. PCLK must be
synchronous to the 8 kHz FSYNC clock and run at one
of the following rates: 256 kHz, 512 kHz, 786 kHz,
1.024 MHz, 1.536 MHz, 1.544 MHz, 2.048 MHz,
4.096 MHz, or 8.192 MHz. The ratio of the PCLK rate to
the FSYNC rate is determined by a counter clocked by
PCLK. The three-bit ratio information is transferred into
an internal register, PLL_MULT, after a device reset.
The PLL_MULT controls the internal PLL, which
multiplies PCLK to generate the rate required to run the
internal filters and other circuitry.
The PLL clock synthesizer settles quickly after power-
up or update of the PLL-MULT register. The PLL lock
process begins immediately after the RESET pin is
pulled high and takes approximately 5 ms to achieve
lock after RESET is released with stable PCLK and
FSYNC. However, the settling time depends on the
PCLK frequency and can be predicted based on the
following equation:

Note: Therefore, the RESET pin must be held low during

powerup and should only be released when both
PCLK and FSYNC signals are known to be stable.

Figure 40. PLL Frequency Synthesizer

settle

PCLK

---------------

PFD

DIV M

PLL_MULT

VCO

÷2

RESET

28.672 MHz

PCLK

Si3220/25

Rev. 1.2

3.27. Interrupt Logic

The Dual ProSLIC devices are capable of generating
interrupts for the following events:

Loop current/ring ground detected
Ring trip detected
Ground Key detected
Power alarm
DTMF digit detected
Active timer 1 expired
Inactive timer 1 expired
Active timer 2 expired
Inactive timer 2 expired
Ringing active timer expired
Ringing inactive timer expired
Pulse metering active timer expired
Pulse metering inactive timer expired
RAM address access complete
Receive path modem tone detected
Transmit path modem tone detected

The interface to the interrupt logic consists of six
registers. Four interrupt status registers (IRQ0IRQ3)
contain 1 bit for each of the above interrupt functions.
These bits are set when an interrupt is pending for the
associated resource. Three interrupt mask registers
(IRQEN1IRQEN3) also contain 1 bit for each interrupt
function. For interrupt mask registers, the bits are active
high. Refer to the appropriate functional description text
for operational details of the interrupt functions.
When a resource reaches an interrupt condition, it
signals an interrupt to the interrupt control block. The
interrupt control block sets the associated bit in the
interrupt status register if the mask bit for that interrupt
is set. The INT pin is a NOR of the bits of the interrupt
status registers. Therefore, if a bit in the interrupt status
registers is asserted, IRQ asserts low. Upon receiving
the interrupt, the interrupt handler should read interrupt
status registers to determine which resource requests
service. All interrupt bits in the interrupt status registers
IRQ0IRQ3 are cleared following a register read
operation. If the interrupt status registers are non-zero,
the INT pin remains asserted.

3.28. SPI Control Interface

The control interface to the Dual ProSLIC devices is a
4-wire SPI bus modeled after microcontroller and serial
peripheral devices. The interface consists of a clock,
SCLK, chip select, CS, serial data input, SDI, and serial
data output, SDO. In addition, the Dual ProSLIC devices
include a serial data through output (SDI_THRU) to
support daisy-chain operation of up to eight devices (up
to sixteen channels). Figure 41 illustrates the daisy-
chain connections. Note that the SDITHRU pin of the
last device in the chain must not be connected to
ground (SDITHRU = 0 indicated GCI mode). The device
operates with both 8-bit and 16-bit SPI controllers.
Each SPI operation consists of a control byte, an
address byte (of which only the seven LSBs are used
internally), and either one or two data bytes depending
on the width of the controller and whether the access is
to an 8-bit register or 16-bit RAM address. Bytes are
always transmitted MSB first. The variations of usage
on this four-wire interface are as follows:

Continuous clocking

. During continuous clocking,

the data transfers are controlled by the assertion of
the CS pin. CS must be asserted before the falling
edge of SCLK on which the first bit of data is
expected during a read cycle and must remain low
for the duration of the 8-bit transfer (command/
address or data), going high after the last rising of
SCLK after the transfer.
Clock during transfer only

. In this mode, the clock

is cycling only during the actual byte transfers. Each
byte transfer consists of eight clock cycles in a return
to "1" format.
SDI/SDO wired operation

. Independent of the

clocking options described, SDI and SDO can be
treated as two separate lines or wired together if the
master is capable of tri-stating its output during the
data byte transfer of a read operation.
Soft reset

. The SPI state machine resets whenever

CS asserts during an operation on an SCLK cycle
that is not a multiple of eight. This is a mechanism
for the controller to force the state machine to a
known state when the controller and the device are
out of synchronization.

As shown in the application schematics in Figure 12 on
page 25 and Figure 13 on page 26, a pulldown resistor
is required on the SDO pin to ensure proper operation.
A pullup resistor is not allowed on the SDO pin.

Si3220/25

Rev. 1.2

The control byte has the following structure and is presented on the SDI pin MSB first:

See Table 41 for bit definitions.

BRDCST R/W REG/RAM Reserved CID[0] CID[1] CID[2] CID[3]

Table 41. SPI Control Interface

BRDCST Indicates a broadcast operation that is intended for all devices in the daisy chain. This is

only valid for write operations since it would cause contention on the SDO pin during a
read.

R/W

Read/Write Bit.
0 = Write operation.
1 = Read operation.

REG/RAM Register/RAM Access Bit.

0 = RAM access.
1 = Register access.

Reserved

3:0

CID[3:0]

Indicates the channel that is targeted by the operation. Note that the 4-bit channel value is
provided LSB first. The devices reside on the daisy chain such that device 0 is nearest to
the controller, and device 15 is furthest down the SDI/SDU_THRU chain. (See Figure 41.)
As the CID information propagates down the daisy chain, each channel decrements the
CID by 1. The SDI nodes between devices reflect a decrement of 2 per device since each
device contains two channels. The device receiving a value of 0 in the CID field responds
to the SPI transaction. (See Figure 42.) If a broadcast to all devices connected to the chain
is requested, the CID does not decrement. In this case, the same 8-bit or 16-bit data is pre-
sented to all channels regardless of the CID values.

Si3220/25

Rev. 1.2

In Figure 42, the CID field is zero. As this field is
decremented (in LSB to MSB order), the value
decrements for each SDI down the line. The BRDCST,
R/W, and REG/RAM bits remain unchanged as the
control word passes through the entire chain. The odd
SDIs are internal to the device and represent the SDI to
SDI_THRU connection between channels of the same
device. A unique CID is presented to each channel, and
the channel receiving a CID value of zero is the target of
the operation (channel 0 in this case). The last line of
Figure 42 illustrates that in Broadcast mode, all bits

pass through the chain without permutation.
Figures 43 and 44 illustrate WRITE and READ
operations to register addresses via an 8-bit SPI
controller. These operations are performed as a 3-byte
transfer. CS is asserted between each byte, which is
required for CS to be asserted before the first falling
edge of SCLK after the DATA byte to indicate to the
state machine that one byte

only

should be transferred.

The state of SDI is a "don't care" during the DATA byte
of a read operation.

Figure 42. Sample SPI Control Word to Address Channel 0

Figure 43. Register Write Operation via an 8-Bit SPI Port

Figure 44. Register Read Operation via an 8-Bit SPI Port

SPI Control Word

BRDCST

R/W

REG/RAM

Reserved

CID[0]

CID[1]

CID[2]

CID[3]

SDI0

SDI1 (Internal)

SDI2

SDI3 (Internal)

SDI 14

SDI15 (Internal)

SDI0-15

CONTROL

ADDRESS

DATA [7:0]

SCLK

SDI

SDO

Hi-Z

CONTROL

ADDRESS

X X X X X X X X

SCLK

SDI

SDO

Data [7:0]

Si3220/25

Rev. 1.2

Figures 45 and 46 illustrate WRITE and READ
operations to register addresses via a 16-bit SPI
controller. These operations require a 4-byte transfer
arranged as two 16-bit words. The absence of CS going
high after the eighth bit of data indicates to the SPI state
machine that eight more SCLK pulses follow to
complete the operation. For a WRITE operation, the last
eight bits are ignored. For a read operation, the 8-bit
data value repeats so that the data is captured during
the last half of a data transfer if required by the
controller.
During register accesses, the CONTROL, ADDRESS,
and DATA are captured in the SPI module. At the
completion of the ADDRESS byte of a READ access,
the contents of the addressed register move into the
data register of the SPI data register. At the completion
of the DATA byte of a WRITE access, the data is
transferred from the SPI to the addressed register.
Figures 4750 illustrate the various cycles for accessing
RAM addresses. RAM addresses are 16-bit entities;
therefore, the accesses always require four bytes.
During RAM address accesses, the CONTROL,
ADDRESS, and DATA are captured in the SPI module.
At the completion of the ADDRESS byte of a READ
access, the contents of the channel-based data buffer

move into the data register in the SPI for shifting out
during the DATA portion of the SPI transfer. This is the
data loaded into the data buffer in response to the
previous RAM address read request. Therefore, there is
a one-deep pipeline nature to RAM address READ
operations. At the completion of the DATA portion of the
READ cycle, the ADDRESS is transferred to the
channel-based address buffer register, and a RAM
address is logged for that channel. The RAMSTAT bit in
each channel is polled to monitor the status of RAM
address accesses that are serviced twice per sample
period at dedicated windows in the DSP algorithm.
A RAM access interrupt in each channel indicates that
the pending RAM access request is serviced. For a
RAM access, the ADDRESS and DATA is transferred
from the SPI registers to the address and data buffers in
the appropriate channel. The RAM WRITE request is
logged. As for READ operations, the status of the
pending request is monitored by either polling the
RAMSTAT bit for the channel or enabling the RAM
access interrupt for the channel. By keeping the
address, data buffers, and RAMSTAT register on a per-
channel basis, RAM address accesses can be
scheduled for both channels without interface.

Figure 45. Register Write Operation via a 16-Bit SPI Port

Figure 46. Register Read Operation via a 16-Bit SPI Port

X X X X X X X X

SCLK

SDI

SDO

CONTROL

ADDRESS

Data [7:0]

Hi - Z

X X X X X X X X

SCLK

SDI

SDO

Data [7:0]

CONTROL

ADDRESS

X X X X X X X X

Data [7:0]

Same byte repeated twice.

Si3220/25

Rev. 1.2

3.29. PCM Interface

The Dual ProSLIC devices contain a flexible
programmable interface for the transmission and
reception of digital PCM samples. PCM data transfer is
controlled by the PCLK and FSYNC inputs, PCM Mode
Select, PCM Transmit Start Count (PCMTXHI/
PCMTXLO), and PCM Receive Start Count (PCMRXHI/
PCMRXLO) registers. The interface can be configured
to support from 4 to 128 8-bit timeslots in each frame.
This corresponds to PCLK frequencies of 256 kHz to
8.192 MHz in power-of-2 increments. (768 kHz,
1.536 MHz, and 1.544 MHz are also available for T1
and E1 support.) Timeslots for data transmission and
reception are independently configured with the
PCMTXHI, PCMTXLO, PCMRXHI, and PCMRXLO.
Special consideration must be given to the PCM
Receive Start Count (PCMRXHI / PCMRXLO) registers.
Changing the PCMRXHI (Reg. 57), PCMRXLO (Reg.
56) on-the-fly while the Si3220/25 is actively passing
audio can cause the digital impedance synthesis block
to perform improperly producing an audible loud white
noise signal across TIP and RING.
To ensure proper device operation, the RX timeslot
registers (PCMRXHI and PCMRXLO, registers 5657)
should be set during the initialization procedure
immediately after power-up and prior to both enabling
the PCM bus and setting the linefeed to the active state.
The TX timeslot registers (PCMTXHI and PCMTXLO,
registers 5455) may be changed at any time to
establish audio connections on the PCM bus.
Setting the correct starting point of the data configures
the part to support long FSYNC and short FSYNC
variants, IDL2 8-bit, 10-bit, and B1 and B2 channel time

slots. DTX data is high-impedance except for the
duration of the 8-bit PCM transmit. DTX returns to high-
impedance on the negative edge of PCLK during the
LSB or on the positive edge of PCLK following the LSB.
This is based on the setting of the PCMTRI bit of the
PCM Mode Select register. Tristating on the negative
edge allows the transmission of data by multiple
sources in adjacent timeslots without the risk of driver
contention. In addition to 8-bit data modes, a 16-bit
mode is provided for testing. This mode can be
activated via the PCMF bits of the PCM Mode Select
register. Setting the PCMTXHI/PCMTXLO or
PCMRXHI/PCMRXLO register greater than the number
of PCLK cycles in a sample period stops data
transmission because neither PCMTXHI/PCMTXLO nor
PCMRXHI/PCMRXLO equal the PCLK count. Figures
5154 illustrate the usage of the PCM highway interface
to adapt to common PCM standards.
As shown in the application schematics in Figures 12
and 13, a pulldown resistor is required on the DTX pin.
A pullup resistor is not allowed on the DTX pin.
Additionally, the PCLK frequency should be chosen
such that there is at least one empty timeslot (hi-Z
timeslot) per 8 kHz frame. If a PCLK is chosen such that
DTX has valid data during the entire frame, choose the
next higher valid PCLK frequency to ensure one or
more empty timeslots in each frame. If an application
requires heavy capacitive loading on the DTX pin, or
more than eight Si322x devices connected to the same
PCM bus, consult your local Silicon Laboratories sales
representative to determine what value of pulldown
resistor should be used.

Figure 51. Example, Timeslot 1, Short FSYNC (TXS/RXS = 1)

MSB

LSB

MSB

LSB

HI-Z

PCLK

FSYNC

PCLK_CNT

DRX

DTX

Si3220/25

Rev. 1.2

Figure 52. Example, Timeslot 1, Long FSYNC (TXS/RXS = 0)

Figure 53. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS = 10)

3.30. PCM Companding

The Dual ProSLIC devices support both µ-255 Law (µ-
Law) and A-Law companding formats in addition to
Linear Data mode. The data format is selected via the
PCMF bits of the PCM Mode Select register. µ-Law
mode is more commonly used in North America and
Japan, and A-Law is primarily used in Europe and other
countries. These 8-bit companding schemes follow a
segmented curve formatted as a sign bit (MSB) followed
by three chord bits and four step bits. A-Law typically
uses a scheme of inverting all even bits while µ-Law
does not. Dual ProSLIC devices also support A-Law
with inversion of even bits, inversion of all bits, or no bit
inversion by programming the ALAW bits of the PCM
Mode Select register to the appropriate setting.

Table 42 on page 81 and Table 43 on page 82 define
the µ-Law and A-Law encoding formats.
The Dual ProSLIC devices also support a 16-bit linear
data format with no companding. This Linear mode is
typically used in systems that convert to another
companding format, such as adaptive differential PCM
(ADPCM) or systems that perform all companding in an
external DSP. The data format is 2s complement with
MSB first (sign bit). Transmitting and receiving data via
Linear mode requires two continuous time slots. An 8-bit
Linear mode enables 8-bit transmission without
companding.

MSB

LSB

MSB

LSB

HI-Z

PCLK

FSYNC

PCLK_CNT

DRX

DTX

MSB

LSB

MSB

LSB

HI-Z

PCLK

FSYNC

PCLK_CNT

DRX

DTX

Si3220/25

Rev. 1.2

3.31. General Circuit Interface

The Dual ProSLIC devices also contain an alternate
communication interface to the SPI and PCM control
and data interface. The general circuit interface (GCI) is
used for the transmission and reception of both control
and data information onto a GCI bus. The PCM and GCI
interfaces are both four-wire interfaces and share the
same pins. The SPI control interface is not used as a
communication interface in the GCI mode but rather as
hard-wired channel selector pins. The selection
between PCM and GCI modes is performed out of reset
using the SDITHRU pin. Tables 44 and 45 illustrate how
to select the communication mode and how the pins are
used in each mode.

If GCI mode is selected, the following pins must be tied
to the correct state to select one of eight subframe
timeslots in the GCI frame (described below). These
pins must remain in this state while the Dual ProSLIC is
operating. Selecting a particular subframe causes that
individual Dual ProSLIC device to transmit and receive
on the appropriate subframe in the GCI frame, which is
initiated by an FSYNC pulse. No further register settings
are needed to select which subframe a device uses,
and the subframe for a particular device cannot be
changed while in operation.

In GCI mode, the PCLK input requires either a
2.048 MHz or a 4.096 MHz clock signal, and the
FSYNC input requires an 8 kHz frame sync signal. The
overall unit of data used to communicate on the GCI
highway is a frame 125 µs in length. Each frame is
initiated by a pulse on the FSYNC pin whose rising
edge signifies the beginning of the next frame. In 2x
PCLK mode, the user sees twice as many PCLK cycles
during each 125 µs frame versus 1x PCLK mode. Each
frame consists of eight fixed timeslot subframes that are
assigned by the subframe select pins as described
above (SDI, SDO, and CS). Within each subframe are
four channels (bytes) of data including two voice data
channels, B1 and B2, one Monitor channel, M, used for
initialization and setup of the device, and one Signaling
and Control channel, SC, used for communicating the
status of the device and initiating commands. Within the
SC channel are six Command/Indicate (C/I) bits and two

Table 44. PCM or GCI Mode Selection

SDITHRU SCLK

Mode Selected

GCI Mode--1x PCLK (2.048 MHz)

GCI Mode--2x PCLK (4.096 MHz)

PCM Mode

Note:

Values shown are the states of the pins at the rising
edge of RESET.

Table 45. Pin Functionality in PCM or GCI Mode

Pin Name

PCM Mode

GCI Mode

SPI Chip Select

Channel Selector,

bit 0

SCLK

SPI Clock Input

PCLK Rate

Selector

SDI

SPI Serial Data Input

Channel Selector,

bit 2

SDO

SPI Serial Data

Output

Channel Selector,

bit 1

SDITHRU

SPI Data Throughput

pin for Daisy Chaining

Operation (Connects

to the SDI pin of the

subsequent device in

the daisy chain)

PCM/GCI Mode

Selector

FSYNC

PCM Frame Sync

Input

GCI Frame Sync

Input

PCLK

PCM Input Clock

GCI Input Clock

DTX

PCM Data Transmit

GCI Data Transmit

DRX

PCM Data Receive

GCI Data Receive

Note:

This table denotes pin functionality after the rising
edge of RESET and mode selection.

Table 46. GCI Mode Subframe Selection

SDI

SDO

GCI Subframe 0 Selected
(Voice channels 12)

GCI Subframe 1 Selected
(Voice channels 34)

GCI Subframe 2 Selected
(Voice channels 56)

GCI Subframe 3 Selected
(Voice channels 78)

GCI Subframe 4 Selected
(Voice channels 910)

GCI Subframe 5 Selected
(Voice channels 1112)

GCI Subframe 6 Selected
(Voice channels 1314)

GCI Subframe 7 Selected
(Voice channels 1516)

Si3220/25

Rev. 1.2

handshaking bits, MR and MX. The C/I bits indicate
status and command communication while the
handshaking bits Monitor Receive, MR, and Monitor
Transmit, MX, exchange data in the Monitor channel.
Figure 55 illustrates the contents of a GCI highway
frame.
3.31.1. 16-Bit GCI Mode
In addition to the standard 8-bit GCI mode, the Dual
ProSLIC devices also offer a 16-bit GCI mode for
passing 16-bit voice data to the upstream host
processor. This mode can be used for testing purposes
or for passing non-companded voice data to an
upstream DSP for further processing.
In 16-bit GCI mode, both of the 8-bit voice data
channels (B1 and B2 in Figure 56) of each subframe are
required to pass the 16-bit voice data to the host. Each
125 µs frame can, therefore, accommodate up to eight
voice channels (the Dual ProSLIC can accommodate up
to sixteen voice channels in 8-bit GCI mode). Table 47
describes the GCI mode subframe selection for 16-bit
GCI mode.

3.31.2. Monitor Channel
The Monitor channel is used for initialization and setup
of the Dual ProSLIC devices. It is also used for general
communication with the Dual ProSLIC by allowing read
and write access to the Dual ProSLIC devices registers.
Use of the monitor channel requires manipulation of the

Figure 55. Time-Multiplexed GCI Highway Frame Structure

Table 47. Subframe Selection 16-Bit GCI Mode

SDI

SDO

GCI Subframe 0 Selected
(Voice channels 01)

GCI Subframe 1 Selected
(Voice channels 23)

GCI Subframe 2 Selected
(Voice channels 45)

GCI Subframe 3 Selected
(Voice channels 67)

SF0

SF1

SF7

SF6

SF5

SF4

SF3

SF2

Channel

Sub-Frame

C/I

MR MX

125

µs = 1 Frame

Si3220/25

Rev. 1.2

The Idle state is achieved by the MX and MR bits being
held inactive for two or more frames. When a
transmission is initiated by a host device, an active state
is seen on the downstream MX bit. This signals the Dual
ProSLIC that a transmission has begun on the Monitor
channel and it should begin accepting data from it. After
reading the data on the monitor channel, the Dual
ProSLIC acknowledges the initial transmission by
placing the upstream MR bit in an active state. The data
is received, and the upstream MR becomes active in the
frame immediately following the downstream MX
activation. The upstream MR then remains active until
either the next byte is received or an end of message is
detected (signaled by the downstream MX being held
inactive for two or more consecutive frames). Upon
receiving acknowledgement from the Dual ProSLIC that
the initial data was received (signaled by the upstream
MR bit transitioning from an active to an inactive state),
the host device places the downstream MX bit in the
inactive state for one frame and then either transmits
another byte by placing the downstream MX bit in an
active state again or signals an end of message by
leaving the downstream MX bit inactive for a second
frame.
When the host is performing a write command, the host
only manipulates the downstream MX bit, and the Dual
ProSLIC only manipulates the upstream MR bit. If a
read command is performed, the host initially
manipulates the downstream MX bit to communicate
the command but then manipulates the downstream MR
bit in response to the Dual ProSLIC responding with the
requested data. Similarly, the Dual ProSLIC initially
manipulates its upstream MR bit to receive the read
command and then manipulates its upstream MX bit to
respond with the requested data. If the host is
transmitting data, the Dual ProSLIC always transmits a
$FF value on its Monitor data byte. While the Dual
ProSLIC is transmitting data, the host should always
transmit a $FF value on its Monitor byte. If the Dual
ProSLIC is transmitting data and detects a value other
than a $FF on the downstream Monitor byte, the Dual
ProSLIC signals an abort.
For read and write commands, an initial address must
be specified. The Dual ProSLIC responds to a read or a
write command at this address and then subsequently
increments this address after every register access. In
this manner, multiple consecutive registers can be read
or written in one transmission sequence.

By correctly manipulating the MX and MR bits, a
transmission sequence can continue from the beginning
specified address until an invalid memory location is
reached. To end a transmission sequence, the host
processor must signal an End-of-Message (EOM) by
placing the downstream MX and MR bits inactive for two
consecutive frames. The transmission can also be
stopped by the Dual ProSLIC by signaling an abort. This
is signaled by placing the upstream MR bit inactive for
at least two consecutive cycles in response to the
downstream MX bit going active. An abort is signaled by
the Dual ProSLIC for the following reasons:

A read or write to an invalid memory address is
attempted.
An invalid command sequence is received.
A data byte was not received for at least two
consecutive frames.
A collision occurs on the Monitor data bytes while
the Dual ProSLIC is transmitting data.
Downstream monitor byte not $FF while upstream
monitor byte is transmitting.
MR/MX protocol violation.

Whenever the Dual ProSLIC aborts due to an invalid
command sequence, the state of the Dual ProSLIC
does not change. If a read or write to an invalid memory
address is attempted, all previous reads or writes in that
transmission sequence are valid up to the read or write
to the invalid memory address. If an end-of-message is
detected before a valid command sequence is
communicated, the Dual ProSLIC returns to the idle
state and remains unchanged.
The data presented to the Dual ProSLIC in the
downstream Monitor bits must be present for two
consecutive frames to be considered valid data. The
Dual ProSLIC is designed to ensure it has received the
same data in two consecutive frames. If it does not, it
does not acknowledge receipt of the data byte and waits
until it does receive two consecutive identical data bytes
before acknowledging to the transmitter that it has
received the data. If the transmitter attempts to signal
transmission of a subsequent data byte by placing the
downstream MX bit in an inactive state while the Dual
ProSLIC is still waiting to receive a valid data byte
transmission of two consecutive identical data bytes,
the Dual ProSLIC signals an abort and ends the
transmission. Figure 58 shows a state diagram for the
Receiver Monitor channel for the Dual ProSLIC.
Figure 59 shows a state diagram for the Transmitter
Monitor channel for the Dual ProSLIC.

Si3220/25

Rev. 1.2

Figures 60 and 61 are example timing diagrams of a register read and a register write to the Dual ProSLIC using
the GCI. As noted in Figure 59, the transmitter should always anticipate the acknowledgement of the receiver for
correct communication with the Dual ProSLIC. Devices that do not accept this "best case" timing scenario will
not be able to communicate with the Dual ProSLIC.

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Si3220/25

Rev. 1.2

3.31.3. Programming the Dual ProSLIC Using the

Monitor Channel

The Dual ProSLIC devices use the monitor channel to
Transfer status or operating mode information to and
from the host processor. Communication with the Dual
ProSLIC should be in the following format:
Byte 1: Device Address Byte
Byte 2: Command Byte
Byte 3: Register Address Byte
Bytes 4-n: Data Bytes
Bytes n+1, N+2: EOM
3.31.4. Device Address Byte
The device address byte identifies which device
receives the particular message. This address must be
the first byte sent to the Dual ProSLIC at the beginning
of each transmission sequence. The device address
byte has the following structure:

A = 1:

Channel A receives the command.

A = 0:

Channel A does not receive the command.

B = 1:

Channel B receives the command.

B = 0:

Channel B does not receive the command.

C = 1:

Normal command follows.

C = 0:

Channel identification command.

When C = 1, bits A and B are channel enable bits.
When these bits are set to 1, the corresponding
channels receive the command in the next command
byte. The channels with corresponding bits set to 0
ignore the subsequent command byte.
3.31.5. Channel Identification (CID) Command
The lowest programmable bit of the device address
byte, C, enables a special channel identification
command to identify itself by software. When C = 0, the
structure of this command is as follows:
A = 1: Channel A is the destination
A = 0: Channel B is the destination

Immediately after the last bit of the CID command is
received, the Dual ProSLIC responds with a fixed two-
byte identification code as follows:

A = 1: Channel A is the source
A = 0: Channel B is the source
Upon sending the two-byte CID command, the Dual
ProSLIC sends an EOM signal (MR = MX = 1) for two
consecutive frames. When C = 0, B must be 0, or the
Dual ProSLIC signals an abort due to an invalid
command. In this mode, only bit C is programmable.
3.31.6. Command Byte
The command byte has the following structure:

RW = 1: A Read operation is performed from the Dual
ProSLIC
RW = 0: A Write operation is performed to the Dual
ProSLIC
CMD[6:0] = 0000001: Read or Write from the Dual
ProSLIC
CMD[6:0] = 0000010-1111111: Reserved
3.31.7. Register Address Byte
The register address byte has the following structure:

This byte contains the actual 8-bit address of the
register to be read or written.
3.31.8. SC Channel
The downstream and upstream SC channels are
continuously carrying I/O information to and from the
Dual ProSLIC during every frame. The upstream
processor has immediate access to the receive
(downstream) and transmit (upstream) data present on
the Dual ProSLIC digital I/O port when used in GCI
mode. The SC channel consists of six C/I bits and two
handshaking bits as described in the tables below. The
functionality of the handshaking bits is defined in the

MSB

LSB

MSB

LSB

Bit

6 5 4 3 2 1

Address Byte

0 0 A 0 0 0

Command Byte

0 0 0 0 0 0

MSB

LSB

Bit

6 5 4 3 2 1

Address Byte

0 0 A 0 0 0

Command Byte

0 1 1 1 1 1

MSB

LSB

CMD[6:0]

MSB

LSB

ADDRESS[7:0]

Si3220/25

Rev. 1.2

monitor channel section. This section defines the
functionality of the six C/I bits whether they are being
transmitted to the GCI bus via the DTX pin (upstream)
or received from the GCI bus via the DRX pin
(downstream). The structure of the SC channel is
shown in Figure 62.

Figure 62. SC Channel Structure

3.31.9. Downstream (Receive) SC Channel Byte
The first six bits in the downstream SC channel control
both channels of the Dual ProSLIC where the C/I bits
are defined as follows:

Figure 63 illustrates the transmission protocol for the C/I
bits within the downstream SC channel. New data
received by either channel must be present and match
for two consecutive frames to be considered valid.
When a new command is communicated via the
downstream C/I bits, this data must be sent for at least
two consecutive frames to be recognized by the Dual
ProSLIC.
The current state of the C/I bits is stored in a primary
register, P. If the received C/I bits are identical to the
current state, no action is taken. If the received C/I bits
differ from those in register P, the new set of C/I bits is
loaded into secondary register S, and a latch is set.
When the next set of C/I bits is received during the
frame that immediately follows, the following rules
apply:

If the received C/I bits are identical to the contents of
register S, the stored C/I bits are loaded into register
P, and a valid C/I bit transition is recognized. The
latch is reset, and the Dual ProSLIC responds
accordingly to the command represented by the new
C/I bits.
If the received C/I bits differ from both the contents of
register S and the contents of register P, the newly-
received C/I bits are loaded into register S, and the
latch remains set. This cycle continues as long as
any new set of C/I bits differs from the contents of
registers S and P.
If the newly-received C/I bits are identical to the
contents of register P, the contents of register P
remain unchanged, and the latch is reset.

MSB

LSB

CI2A

CI1A

CI0A

CI2B

CI1B

CI0B

CI2A, CI1A, CI0A Used to select operating mode for

channel A

CI2B, CI1B, CI0B Used to select operating mode for

channel B

MR, MX

Monitor channel handshake bits

Table 48. Programming Operating Modes Using

Downstream SC Channel C/I Bits

Channel Specific C/I bits

Dual ProSLIC Operating
Mode

CI2x

CI1x

CI0x

Open (high impedence,
no line monitoring)

Forward Active

Forward On-Hook Trans-
mission

Ground Start (Tip Open)

Ringing

Reverse Active

Reverse On-Hook Trans-
mission

Ground Start (Ring
Open)

Note:

x = A or B, corresponding to Channel A or
Channel B.

Si3220/25

Rev. 1.2

Figure 63. Protocol for Receiving C/I Bits in the Dual ProSLIC

When the Dual ProSLIC is set to GCI mode at
initialization, the default setting ignores the downstream
SC channel byte and allows linefeed state commands to
be directed through the monitor channel. This default
configuration is enabled by initializing the GCILINE bit
of the PCMMODE register to 0, which prevents the Dual
ProSLIC from transitioning between linefeed operating
states due to invalid data that may exist within the
downstream SC channel byte. To transfer direct linefeed
control to the downstream SC channel, the user must
set the GCILINE bit to 1. Once the GCILINE bit has
been set, the Dual ProSLIC follows the commands that
are contained in the downstream SC channel byte as
described in Figure 62.
The Dual ProSLIC architecture also enables automatic
transitions between linefeed operating states to reduce
the amount of interaction required between the host
processor and the Dual ProSLIC. When a GCI bus is
implemented, the user must ensure that these
automatic linefeed state transitions are consistent with
the linefeed commands contained within the
downstream SC channel byte.
In normal operation, these automatic linefeed state
transitions are accompanied by the setting of a
threshold detection flag and an interrupt bit, if enabled.
To allow the Dual ProSLIC to automatically detect the

appropriate thresholds and control the linefeed
transitions, the downstream SC channel byte should be
updated accordingly once the interrupt bit is read from
the upstream SC channel byte. To disable the automatic
transitions, the user must set the GCILINE bit. Enabling
this manual mode requires the host processor to read
the upstream SC channel information and provide the
appropriate downstream SC channel byte command to
program the correct linefeed state.
Table 49 presents the automatic linefeed state
transitions and their associated registers that cause the
transition.
The transition to the OPEN state stemming from power
alarm detection is intended to protect the Dual ProSLIC
circuit in the event that too much power is dissipated in
the Si3200 LFIC. This alarm is typically due to a fault in
the application circuit or on the subscriber loop but can
be caused by intermittent power spikes depending on
the threshold to which the alarm is set. The user can re-
initialize the linefeed operating state that was in effect
just prior to the power alarm by toggling the downstream
SC channel byte to the OPEN state for two consecutive
cycles and then resetting the downstream SC channel
byte to the intended linefeed state for two consecutive
cycles. If the Dual ProSLIC continues to automatically
transition to the OPEN state, the power alarm threshold

Receive New

C/I Code

Store in S

Receive New

C/I Code

= P?

= S?

Load C/I Register
With New C/I Bits

Yes

P: C/I Primary Register Contents

S: C/I Secondary Register Contents

Si3220/25

Rev. 1.2

might be set incorrectly. If this problem persists after the
power alarm settings are verified, a system fault is
probable, and the user should take measures to
diagnose the problem.
3.31.10. Upstream (Transmit) SC Channel Byte
The upstream SC channel byte looks similar to the
downstream SC channel byte except that the
information quickly transfers the most time-critical
information from the Dual ProSLIC to the GCI bus. Each
upstream SC channel byte transfer from the Dual
ProSLIC lasts for at least two consecutive frames to

represent a valid transfer. The upstream C/I bits are
defined as follows:

CI2A, CI1A, CI0A

Monitors status data for channel A

CI2B, CI1B, CI0B

Monitors status data for channel B

MR, MX

Monitor channel handshake bits

(see Monitor Channel section)

Table 49. Automatic Linefeed State Transitions

Initiating Action

Automatic Linefeed State

Transition

Detection/Control Bits

Interrupt Enable/Status

Bits

Loop closure detected On-hook active

off-hook active,

Off-hook active

on-hook active

LCR (Register 9)

LOOPE, LOOPS

(Register 16/19)

Ring trip detected

Ringing

off-hook active

RTP (Register 9)

RTRIPE, RTRIPS

(Register 16/19)

Ringing burst
cadence

Ringing

on-hook transmission

On-hook transmission

ringing

T1EN, T2EN

(Register 23)

RINGT1E, RINGT2E,

RINGT1S, RINGT2S

(Register 15/18)

Power alarm detected

Any state

open

PQ1DL (RAM 50)

PQ1E, PQ1S

(Registers 17/20)

Table 50. Monitored Data via Upstream SC Channel C/I Bits

C/I Bit

Information Provided

Mirrored Register Bits

Context

CI2A

Interrupt information on

channel A

IRQ0[0]+
IRQ0[1]+

IRQ0[2]

CI2A = 0: No interrupt on channel A
CI2A = 1: Interrupt present on channel A

CI1A

Hook status information

on channel A

LCRRTP[0]

(LCR bit)

CI1A = 0: Channel A is on-hook
CI1A = 1: Channel A is off-hook

CI0A

Ground key information

on channel A

LCRRTP[2]

(LONGHI bit)

CI0A = 0: No longitudinal current detected
CI0A = 1: Longitudinal current detected in chan-
nel A

CI2B

Interrupt information on

channel B

IRQ0[4]+
IRQ0[5]+

IRQ0[6]

CI2A = 0: No interrupt on channel B
CI2A = 1: Interrupt present on channel B

CI1B

Hook status information

on channel B

LCRRTP[0]

(LCR bit)

CI1A = 0: Channel B is on-hook
CI1A = 1: Channel B is off-hook

CI0B

Ground key information

on channel B

LCRRTP[2]

(LONGHI bit)

CI0A = 0: No longitudinal current detected
CI0A = 1: Longitudinal current detected in chan-
nel B

Si3220/25

Rev. 1.2

The interrupt information for channels A and B is a
single bit that indicates that one or more interrupts might
exist on the respective channel. Each of the individual
interrupt flags (see registers 1820) can be individually
masked by writing the appropriate bit in registers 2123
to ignore specific interrupts. When using the GCI mode,
the user should verify that each of the desired interrupt
bits are set so the upstream SC channel byte includes
the required interrupt functions.

3.32. System Testing

The Dual ProSLIC devices include a complete suite of
test tools to test the functionality of the line card and
detect fault conditions present on the TIP/RING pair.
Using one of the loopback test modes with the signal
generation and measurement tools eliminates the need
for per-line test relays and centralized test equipment.
3.32.1. Loopback Modes
Three loopback test options are available for the Dual
ProSLIC devices:

The codec loopback path encompasses almost
entirely the electronics of both the transmit and
receive paths. The analog signal at the output of the
receive path is fed back to the input of the transmit
path through a feedback path on the analog side of
the audio codec. Both the impedance synthesis and
transhybrid balance functions are disabled in this
mode. (See DLM3 path in Figure 11 on page 24.)
The signal path starts with 8-bit PCM data input to
the receive path and ends with 8-bit PCM data at the
output of the transmit path. The user can bypass the
companding process and interface directly to the 16-
bit data.
A second digital loopback takes the receive path
digital stream and routes it back to the transmit path
via the transhybrid feedback path. (See DLM2 path
through block H in Figure 11.) This mode
characterizes the transhybrid filter response. The
transhybrid block can also be disabled (set to unity
gain) in this mode for diagnosing the digital gain
blocks and filter stages in both transmit and receive
paths. The signal path starts with 8-bit PCM data
input to the receive path and ends with 8-bit PCM
data at the output of the transmit path. The user can
bypass the companding process and interface
directly to the 16-bit data.

A third digital loopback takes the digital stream at the
output of the µ-Law/A-Law expander and feeds it
back to the input of the µ-Law/A-Law compressor.
(See DLM1 path in Figure 11.) This path verifies that
the host is connected correctly with the Dual
ProSLIC through the PCM interface and that the
PCLK and FSYNC signals are correctly set. This
mode also can test the µ-Law/A-Law companding
process. The signal path starts with 8-bit PCM data
input to the receive path and ends with 8-bit PCM
data at the output of the transmit path. The user can
also connect directly to the 16-bit data to eliminate
the µ-Law/A-Law companding process when testing
the PCM interface.

3.32.2. Line Test and Diagnostics
The Dual ProSLIC devices provide a variety of signal
generation and measurement tools that facilitate fault
detection and parametric diagnostics on the TIP/RING
pair and line card functionality verification. The Dual
ProSLIC generates test signals, measures the
appropriate voltage/current/signal levels, and processes
the results to provide a meaningful result to the user.
Interaction is required from the host microprocessor to
load the test parameters into the appropriate registers,
initiate the test(s), and read the results from the
registers. In some cases, the host processor might also
be required to perform some simple mathematics to
achieve the results. Software modules are available to
simplify integration of the diagnostics functions into the
system. The need for test relays and a separate test
head is eliminated in most applications. To address
legacy applications, all versions of the Dual ProSLIC
include test-in and test-out relay drivers to switch in a
centralized test card.
The Dual ProSLIC line test and diagnostics capabilities
are categorized into three sections: signal generation
tools, measurement tools, and diagnostics capabilities.
Using these signal generation and measurement tools,
a variety of other diagnostic functions can be performed
to meet the unique requirements of specific
applications. Table 51 summarizes the ranges and
capabilities of the signal generation and measurement
tools.

Si3220/25

Rev. 1.2

3.32.3. Signal Generation Tools

TIP/RING dc signal generation.

The Dual ProSLIC

line feed D/A converter can program a constant
current linefeed from 1845 mA in 0.87 mA steps
with a ±10% total accuracy. In addition, the open-
circuit TIP/RING voltage can be programmed from 0
to 63 V in 1 V steps. The linefeed circuitry can also
generate a controlled polarity reversal.
Tone generation.

The Dual ProSLIC devices can

generate single or dual tones over the entire audio
band and can direct them into either the transmit or
receive path depending on the diagnostic
requirements. Ringing signals from 4100 Hz can
also be generated.

Diagnostics mode ringing generation.

The Dual

ProSLIC devices can generate an internal low-level
ringing signal to test for the presence of REN without
causing the terminal equipment to ring audibly. This
ringing signal can be either balanced or unbalanced
depending on the state of the RINGUNB bit of the
RINGCON register. This feature is also available
with the Si3225 provided that sufficient battery
voltage is present.

Table 51. Summary of Signal Generation and Measurement Tools

Function

Range

Accuracy/Resolution

Comments

Signal Generation Tools

DC Current Generation

18 to 45 mA

0.875 mA

DC Voltage Generation

0 to 63.3 V

1.005 V

Audio Tone Generation

200 to 3400 Hz

Ringing Signal Generation

4 to 15 Hz

16 to 100 Hz

±5%
±1%

Measurement Tools

8-Bit dc/Low-Frequency
Monitor A/D Converter

High Range:

0 to 160.173 V

0 to 101.09 mA

628 mV

396.4 µA

800 Hz update rate

rms

, ac

, and dc

post-processing blocks

Low Range: 0 to 64.07 V

0 to 50.54 mA

251 mV

198.2 µA

Programmable Timer

0 to 8.19 s

125 µs

AC Low-Pass Filter

3 to 400 Hz

16-Bit Audio A/D Converter

0 to 2.5 V

38 µV

Transmit Path Notch Filter

300 to 3400 Hz

Single or dual notch,

90 dB attenuation

Transmit Path Bandpass Filter

300 to 3400 Hz

Si3220/25

Rev. 1.2

Figure 64. SLIC Diagnostic Filter Structure

3.32.4. Measurement Tools

8-Bit monitor A/D converter.

This 8-bit A/D

converter monitors all dc and low-frequency voltage
and current data from TIP to ground and RING to
ground. Two additional values, TIP RING and
TIP + RING, are calculated and stored in on-chip
registers to analyze metallic and longitudinal effects.
The A/D operates at an 800 Hz update rate to allow
measurement bandwidth from dc to 400 Hz. A dual-
range capability allows high-voltage/high-current
measurement in the high range but can also
measure lower voltages and currents with a tighter
resolution.
Programmable bandpass filter.

A bandpass filter

discriminates certain frequency ranges, such as
ringing frequencies and 50 Hz/60 Hz induction, from
nearby or crossed power leads.
SLIC diagnostics filter.

Several post-processing

filter blocks monitor peak dc and ac characteristics of
the Monitor A/D converter outputs and values
derived from these outputs. Setting the SDIAG bit in
the DIAG register enables the filters. There are
separate filters for each channel, and their control is
independent. These filters require DSP processing,
which is available only when voice band processing
is not being performed. If an off-hook or ring trip
condition is detected while the SDIAG bit is set, the
bit is cleared, and the diagnostic information is not
processed.
The following parameters can be selected as inputs
to the diagnostic block by setting the SDIAG bits in
the DIAG register to values 07 corresponding to the
order below:

TIP

= voltage on the TIP lead

RI NG

= voltage on the RING lead

LOOP

= V

TIP

-V

RING

= metallic (loop) voltage

LONG

= (V

TIP

RING

)/2 = longitudinal voltage

LOOP

= I

TIP

-I

RING

= metallic (loop) current

LONG

= (I

TIP

RING

)/2 = longitudinal current

RING, EXT

= ringing voltage when using an external

ringing source (Si3225 only)

RING,EXT

= ringing current when using an external

ringing source (Si3225 only)

The SLIC diagnostic capability consists of a peak detect
block and two filter blocks, one for dc and one for ac.
The topology is illustrated in Figure 64.
The peak detect filter block reports the magnitude of the
largest positive or negative value without sign. The dc
filter block consists of a single pole IIR low-pass filter
with a coefficient held in the DIAGDCCO RAM location.
The filter output is read from the DIAGDC RAM location.
The ac filter block consists of a full-wave rectifier
followed by a single-pole IIR low-pass filter with a
coefficient held in the DIAGACCO RAM location. The
peak value is read from the DIAGPK RAM location. The
peak value is cleared and the filters are flushed on the
0-1 transition of the SDIAG bit and when the input
source changes. The user can write 0 to the DIAGPK
RAM location to get peak information for a specific time
interval.

16-bit audio A/D converter.

The A/D converter

portion of the audio codec is made available for
processing test data received back through the
transmit audio path. The audio path offers a 2.5 V
peak voltage measurement capability and a coarse
attenuation stage for scenarios where the incoming
signal amplitude must be attenuated by as much as
3 dB to bring it into the allowable input range without
clipping.

VTIP

VRING

VLOOP

VLONG

ILOOP

ILONG

VRING,EXT
IRING,EXT

LPF

PEAK

DETECT

FULL WAVE

RECTIFY

LPF

DIAGAC

DIAGDC

DIAGPK

DIAGACCO

DIAGDCCO

Si3220/25

Rev. 1.2

Programmable timer.

The Dual ProSLIC devices

incorporate several digital oscillator circuits to
program the on and off times of the ringing and
pulse-metering signals. The tone generation
oscillator can be used to program a time period for
averaging specific measured test parameters.
Transmit audio path diagnostics filter.

Transmit

path audio diagnostics are facilitated by
implementing a sixth-order IIR filter followed by peak
detection and power estimation blocks. This filter
can be programmed to eliminate or amplify specific
signals for the purpose of measuring the peak
amplitude and power content of individual
components in the audio spectrum. Figure 11 on
page 24 illustrates the location of the diagnostics
filter block.
The sixth order IIR filter operates at an 8 kHz sample
rate and is implemented as three second-order filter
stages in cascade. Each second-order filter offers
five fully-programmable coefficients (a1, a2, b0, b1,
and b2) with 25-bit precision by providing several
user-accessible registers. Each filter stage is
implemented with the following format:

If any of the second-order filter stages are not
required, they can be programmed to H(z) = 1 by
setting a1 = 0, a2 = 0, b0 = 1, b1 = 0, and b2 = 0.
This flexible filter block can be programmed with the
following characteristics:

Single notch.

Used for measuring noise/distortion in

the presence of a single tone. 90 dB attenuation is
provided at the notched frequency. Implemented by
placing two 0s on the unit circle at the notch frequency
and two poles inside the unit circle at the notch
frequency.

Dual notch.

Used for measuring noise/distortion in the

presence of dual tones.

Single notch/single peak.

Used for measuring a

particular harmonic in the presence of a single tone.

Dual notch/single peak.

Used to measure a particular

intermodulation product in the presence of dual tones.

Because each second-order filter stage is fully-
programmable, there are many other possible filter
implementations.
The IIR filter output is measured for power and peak
post-processing. The peak measurement window
duration is programmable by entering a value into the
TESTWLN RAM address. The peak value (TESTPKO)
is updated at the end of each window period. Power
measurement is performed by using a single-pole IIR
filter to average the output of the sixth-order IIR filter.

The power averaging filter time constant is absolute
value programmable, and the average power result is
read from the TESTAVO RAM location.
3.32.5. Diagnostics Capabilities

Foreign voltages test.

The Dual ProSLIC devices

can detect the presence of foreign voltages
according to GR-909 requirements of ac voltages >
10 V and dc voltages > 6 V from T-G or R-G. This
test is performed when it has been determined that a
hazardous voltage is not present on the line.
Resistive faults (leakage current) test.

Resistive

fault conditions are measured from T-G, R-G, or T-R
for dc resistance per GR-909 specifications. If the dc
resistance is < 150 k

, it is considered a resistive

fault. To perform this test, program the Dual ProSLIC
chipset to generate a constant open-circuit voltage,
and measure the resulting current. The resistance is
then calculated.
Receiver off-hook test.

Uses a similar procedure

as described in the resistive faults test above but is
measured across T-R only. In addition, two
measurements must be performed at different open-
circuit voltages to verify the resistive linearity. If the
calculated resistance has more than 15%
nonlinearity between the two calculated points and
the voltage/current origin, it is determined to be a
resistive fault.
Ringers (REN) test.

Verifies the presence of REN at

the end of the TIP/RING pair per GR-909
specifications. It can be implemented by generating
a 20 Hz ringing signal between 7 V

rms

and 17 V

rms

and measuring the 20 Hz ac current using the 8-bit
monitor ADC. The resistance (REN) can then be
calculated using the software module. The
acceptable REN range is >0.175 REN (<40 k

) or

<5 REN (>1400

). A returned value of <1400 is

determined to be a resistive fault from T-R, and a
returned value >40 k

is determined to be a loop

with no handset attached.
AC line impedance measurement.

Determines the

ac loop impedence across T-R. It can be
implemented by sending out multiple discrete tones,
one at a time, and measuring the returned amplitude
with the hybrid balance filter disabled. By calculating
the voltage difference between the initial amplitude
and the received amplitude and dividing the result by
the audio current, the line impedance can then be
calculated.

H z

( )

b0 b1z

b2z

(

)

1 a1z

a2z

(

)

--------------------------------------------------------

Si3220/25

Rev. 1.2

Line capacitance measurement.

Implemented like

the ac line impedance measurement test above, but
the frequency band of interest is between 1 kHz and
3.4 kHz. Knowing the synthesized two-wire
impedance of the Dual ProSLIC, the roll-off effect
can be used to calculate the ac line capacitance.
Ringing voltage verification.

Verifies that the

desired ringing signal is correctly applied to the TIP/
RING pair and can be measured in the 8-bit monitor
ADC, which senses low-frequency signals directly
across T-R.
Idle channel noise measurement.

Given any

transmission mode with no tone generated and the
hybrid balance filter turned off, the voice band
energy can be measured through the normal audio
path and read through the appropriate register.
Harmonic distortion measurement.

Detects the

power content of a particular harmonic. It can be
implemented by programming two of the IIR
diagnostics filter stages to provide a notch at the
fundamental frequency and a peak at the harmonic
of interest. Performing this procedure on all relevant
harmonics individually and summing the results
provides the total harmonic distortion.
Intermodulation distortion measurement (two-
tone method).

Measures the intermodulation

distortion product in the presence of two tones. It can
be implemented by programming the three IIR
diagnostic filter stages to provide two notches at the
two tone frequencies and a peak at the frequency of
interest.

Si3220/25

100

Rev. 1.2

4. Pin Descriptions: Si3220/25

Pin Number(s)

Symbol

Input/

Output

Description

Si3220

Si3225

1, 16

SVBATa,

SVBATb

Battery Sensing Input.
Analog current input used to sense battery voltage.

2,15

RPOa, RPOb

Transconductance Amplifier External Resistor Connec-
tion.

3, 14

RPIa,

RPIb

Transconductance Amplifier External Resistor Connec-
tion.

4, 13

RNIa,

RNIb

Transconductance Amplifier Resistor Connection.

5, 12

RNOa, RNOb

Transconductance Amplifier Resistor Connection.

6, 11

CAPPa,

CAPPb

Differential Capacitor.
Capacitor used in low-pass filter to stabilize SLIC feedback
loops.

7, 10

CAPMa,

CAPMb

Common Mode Capacitor.
Capacitor used in low-pass filter to stabilize SLIC feedback
loops.

QGND

Component Reference Ground.
Return path for differential and common-mode capacitors. Do
not connect to system ground.

RPOa

SVBATa

RPIa

RNIa

RNOa

CAPPa

CAPMa

QGND

IREF

CAPMb

CAPPb

RNOb

RNIb

RPIb

RPOb

SVBATb

IPAC

IPD

I
N

I
P

I
N

INGPb

RTR

1
b

2
b

RRD

ELb

RRDa

SDITHRU

SDI

SDO

SCLK

VDD4

GND4

INT

PCLK

GND3

VDD3

DTX

DRX

RESET

FSYNC

I
P

I
N

IPNa

IRIN

IPPa

IRIN

THE

TRD

1
a

TRD

2
a

Si3225

64-Lead TQFP

(epad)

RPOa

SVBATa

RPIa

RNIa

RNOa

CAPPa

CAPMa

QGND

IREF

CAPMb

CAPPb

RNOb

RNIb

RPIb

RPOb

SVBATb

I
PAC

I
P

SRI

I
N

VDD

TRD

SELb

GPOa

SDITHRU

SDI

SDO

SCLK

VDD4

GND4

INT

PCLK

GND3

VDD3

DTX

DRX

RESET

FSYNC

STI

ACa

STI

I
N

I
P

I
N

I
T

I
PPa

I
N

D1a

SELa

D2a

Si3220

64-Lead TQFP

(epad)

Si3220/25

Rev. 1.2

101

IREF

IREF Current Reference.
Connects to an external resistor to provide a highly-accurate
reference current. Return path for IREF resistor should be
routed to QGND pin.

17, 64

STIPDCb,

STIPDCa

TIP Sense.
Analog current input senses dc voltage on TIP side of sub-
scriber loop.

18, 63

STIPACb, STI-

PACa

TIP Transmit Input.
Analog input senses ac voltage on TIP side of subscriber loop.

19, 62

SRINGACb,

SRINGACa

RING Transmit Input.
Analog input senses ac voltage on RING side of subscriber
loop.

20, 61

SRINGDCb,

SRINGDCa

RING Sense.
Analog current input senses dc voltage on RING side of sub-
scriber loop.

21, 60

ITIPNb,

ITIPNa

Negative TIP Current Control.
Analog current output provides dc current return path to V

BAT

from TIP side of the loop.

22, 59

IRINGNb,

IRINGNa

Negative RING Current Control.
Analog current output provides dc current return path to V

BAT

from RING side of the loop.

23, 58

ITIPPb,

ITIPPa

Positive TIP Current Control.
Analog current output drives dc current onto TIP side of sub-
scriber loop in normal polarity. Also modulates ac current onto
TIP side of loop.

24, 37,

42, 57

24, 37,

42, 57

DD2

DD3

DD4

DD1

Supply Voltage.
Power supply for internal analog and digital circuitry. Connect
all V

pins to the same supply and decouple to adjacent GND

pin as close to the pins as possible.

25, 38,

41, 56

25, 38,

41, 56

GND2,GND3,

GND4,GND1

Ground.
Ground connection for internal analog and digital circuitry.
Connect all pins to low-impedance ground plane.

26, 55

IRINGPb,

IRINGPa

Positive RING Current Control.
Analog current output drives dc current onto RING side of sub-
scriber loop in reverse polarity. Also modulates ac current onto
RING side of loop.

27,54

THERMb,

THERMa

Temperature Sensor.
Senses Internal temperature of Si3200. Connect to THERM pin
of Si3200 or to V

when using discrete linefeed circuit.

29, 51

TRD1b,

TRD1a

Test Relay Driver Output.
Drives test relays for connecting loop test equipment.

Pin Number(s)

Symbol

Input/

Output

Description

Si3220

Si3225

Si3220/25

102

Rev. 1.2

28, 52,

No Internal Connection.
Leave unconnected or connect to ground plane.

28, 52

RTRPb,

RTRPa

External Ring Trip Sensing Input.
Used to sense ring-trip condition when using centralized ring
generator. Connect to low side of ring sense resistor.

30, 50

TRD2b,

TRD2a

Test Relay Driver Output.
Drives test relays for connecting loop test equipment.

31, 48

RRDb, RRDa

Ring Relay Driver Output.
Connects an external centralized ring generator to the sub-
scriber loop.

31, 48

GPOb, GPOa

General Purpose Output Driver.
Used as a relay driver or as a second battery select pin when
using a third battery supply.

32, 49

BATSELb,

BATSELa

Battery Voltage Select Pin.
Switches between high and low external battery supplies.

DRX

Receive PCM Data.
Input data from PCM/GCI bus.

DTX

Transmit PCM Data.
Output data to PCM/GCI bus.

PCLK

PCM Bus Clock.
Clock input for PCM/GCI bus timing.

RESET

Reset.
Active low. Hardware reset used to place all control registers in
a known state. An internal pulldown resistor asserts this pin low
when not driven externally.

FSYNC

Frame Sync.
8 kHz frame synchronization signal for PCM/GCI bus. May be
short or long pulse format.

INT

Interrupt.
Maskable interrupt output. Open drain output for wire-ORed
operation.

SCLK

Serial Port Bit Clock Input.
Controls serial data on SDO and latches data on SDI.

SDO

Serial Port Data Out.
Serial port control data output.

SDI

Serial Port Data In.
Serial port control data input.

Pin Number(s)

Symbol

Input/

Output

Description

Si3220

Si3225

Si3220/25

104

Rev. 1.2

5. Pin Descriptions: Si3200

Pin #(s)

Symbol

Input/

Output

Description

TIP

I/O

TIP Output.
Connect to the TIP lead of the subscriber loop.

2, 10, 11

No Internal Connection.
Do not connect to any electrical signal.

RING

I/O

RING Output.
Connect to the RING lead of the subscriber loop.

VBAT

Operating Battery Voltage.
Si3200 internal system battery supply. Connect SVBATa/b pin from Si3220/
25 and decouple with a 0.1 µF/100 V filter capacitor.

BATH

High Battery Voltage.
Connect to the system ringing battery supply. Decouple with a 0.1 µF/100 V
filter capacitor.

BATL

Low Battery Voltage.
Connect to lowest system battery supply for off-hook operation driving short
loops. An internal diode prevents leakage current when operating from
V

BATH

GND

Ground.
Connect to a low-impedance ground plane.

VDD

Supply Voltage.
Main power supply for all internal circuitry. Connect to a 3.3 V or 5 V supply.
Decouple locally with a 0.1 µF/10 V capacitor.

BATSEL

Battery Voltage Select.
Connect to the BATSEL pin of the Si3220 or Si3225 through an external
resistor to enable automatic battery switching. No connection is required
when used with the Si3225 in a single battery system configuration.

Si3200

16-Lead SOIC

(epad)

ITIPP

THERM
IRINGP
IRINGN

NC
NC
BATSEL

ITIPN

TIP

RING

VBATH

GND

VBATL

VDD

VBAT

Si3220/25

Rev. 1.2

109

9. Dual ProSLIC Selection Guide

Part Number

Description

On-Chip

Ringing

External

Ringing

Support

Pulse

Metering

Lead-Free/

RoHS

Compliant

Temp

Range

Package

Si3200-X-FS

Linefeed interface

0 to 70

SOIC-16

Si3200-X-GS

Linefeed interface

40 to 85

SOIC-16

Si3220-X-FQ

Dual ProSLIC

0 to 70

TQFP-64

Si3220-X-GQ

Dual ProSLIC

40 to 85

TQFP-64

Si3225-X-FQ

Dual ProSLIC

0 to 70

TQFP-64

Si3225-X-GQ

Dual ProSLIC

40 to 85

TQFP-64

Notes:

"X" denotes product revision.

Add an "R" at the end of the device to denote tape and reel option; 2500 quantity per reel.

Table 54. Evaluation Kit Ordering Guide

Item

Supported Dual

ProSLIC

Description

Linefeed Interface

Si3220PPTX-EVB

Si3220

Eval Board, Daughter Card

Discrete

Si3220PPT0-EVB

Si3220

Eval Board, Daughter Card

Si3200

Si3220DCX-EVB

Si3220

Daughter Card Only

Discrete

Si3220DC0-EVB

Si3220

Daughter Card Only

Si3200

Si3225PPTX-EVB

Si3225

Eval Board, Daughter Card

Discrete

Si3225PPT0-EVB

Si3225

Eval Board, Daughter Card

Si3200

Si3225DCX-EVB

Si3225

Daughter Card Only

Discrete

Si3225DC0-EVB

Si3225

Daughter Card Only

Si3200

Si3220/25

112

Rev. 1.2

ONTACT

NFORMATION

Silicon Laboratories Inc.
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Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: ProSLICinfo@silabs.com
Internet: www.silabs.com

Silicon Laboratories, Silicon Labs, ISOmodem, and ProSLIC are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SI3220PPTX-EVB

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SI3220PPTX-EVB