Document Outline

• SS1102C Integrated MCU with Spread-Spectrum Transceiver (SST) External Specification
  • 1. Description
  • 2. Features
  • 3. SS1102C Block Diagram
    • Figure 1. SS1102C Block Diagram
  • 4. Pin Description
    • TABLE 1. Pin Description
      • Figure 2. SS1102C Pinout
  • 5. CPU
  • 6. Memory organization
    • 6.1. Data memory
      • Figure 3. The SS1102C Data Memory
    • 6.2. Program memory
      • Figure 4. The SS1102C Program Memory
  • 7. Special function registers
    • TABLE 2. Special Function Registers Description
    • 7.1. Stack Pointer (SP)
    • 7.2. Data Pointer (DPTR)
    • 7.3. Program Status Word (PSW)
      • TABLE 3. Register bank select bits
    • 7.4. Accumulator (ACC)
    • 7.5. B Register (B)
    • 7.6. Memory Size Register (MSIZ)
    • 7.7. Interrupts
  • 8. Time Base Timer
    • 8.1. Overview
      • Figure 5. Time Base Timer
    • 8.2. Time Base Timer Control Register (TBCR)
      • TABLE 4. Definition of TBCR
      • TABLE 5. Description of TBCR
    • 8.3. TB-Timer Counter Register (TBCNT)
      • TABLE 6. Definition of TBCNT
      • TABLE 7. Description of TBCNT
    • 8.4. TB-Timer Data Register (TBDAT)
      • TABLE 8. Definition of TBDAT
      • TABLE 9. Description of TBDAT
  • 9. Capture Timers 1/2
    • 9.1. Overview
      • Figure 6. Capture Timer in Auto-Reload Mode
    • 9.2. Auto-Reload Mode
    • 9.3. Up Down-Count Mode
      • Figure 7. Capture Timer 1 in Up-Down Count Mode
    • 9.4. Capture Mode
      • Figure 8. Capture Timer in Capture Mode
    • 9.5. Capture Timer Control Registers (CT1CR/CT2CR)
      • TABLE 10. Definition of CT1CR/CT2CR
      • TABLE 11. The Description of CT1CR/CT2CR
    • 9.6. Capture Timer-1 Status Registers (CT1SR)
      • TABLE 12. Definition of CT1SR
      • TABLE 13. Description of CT1SR
    • 9.7. C-Timer Counter Registers (CT1CNTH & CT1CNTL / CT2CNTH& CT2CNTL)
      • TABLE 14. Definition of CTnCNTH (n = 1 or 2)
      • TABLE 15. Definition of CTnCNTL (n = 1 or 2)
      • TABLE 16. The Description of CTnCNTH & CTnCNTL
    • 9.8. C-Timer Data Register (CT1DATH & CT1DATL / CT2DATH & CT2DATL)
      • TABLE 17. Definition of CTnDATH (n = 1 or 2)
      • TABLE 18. Definition of CTnDATL (n = 1 or 2)
      • TABLE 19. The Description of CTnDATH & CTnDATL
  • 10. WatchDog Timer
    • 10.1. Overview
      • Figure 9. Watch Dog Timer
    • 10.2. WatchDog Timer Control Register (WDCR)
      • TABLE 20. Definition of WDCR
      • TABLE 21. The Description of WDCR bit-7 to 4
      • TABLE 22. The Description of WDCR bit-3 to 0
    • 10.3. WatchDog Timer Register (WDCNT)
      • TABLE 23. Definition of WDCNT
    • 10.4. Operation
  • 11. SPI (Serial Peripheral Interface)
    • 11.1. Overview
    • 11.2. SPI Pin and Timing Description
    • 11.3. SPI Timing Description
      • Figure 10. SPI Timing Diagram
    • 11.4. SPI Operation
      • Figure 11. SPI Block Diagram
      • Figure 12. SPI Master-Slave Interconnection
    • 11.5. SPI Control Register (SPICR)
      • TABLE 24. Definition of SPICR
      • TABLE 25. Description of SPICR
    • 11.6. SPI Status Register (SPI1SR)
      • TABLE 26. SPI Status Register (SPI1SR)
      • TABLE 27. Description of SPI Status Register (SPI1SR)
    • 11.7. SPI Shift Register (SPIDAT)
      • TABLE 28. Definition of SPIDAT
  • 12. Direct Sequence Spread Spectrum Baseband Modem (SSTM)
    • 12.1. Receiver
    • 12.2. Transmitter
    • 12.3. TDD Controller
    • 12.4. FIFOs
    • 12.5. Master Clock Generator
    • 12.6. Full-Duplex Operation
      • (EQ 1)
      • (EQ 2)
    • 12.7. TDD Protocol
      • Figure 13. Burst Frame Structures
      • Figure 14. Receiver Lock State Machine
    • 12.8. System Delay
      • (EQ 3)
        • Figure 15. System Delay
    • 12.9. Timing Information
      • 12.9.1 Full Duplex Operations
        • Figure 16. Full-Duplex Data Interface Timing
      • 12.9.2 Threshold Value Calculation
    • 12.10. Half-duplex Operation
      • (EQ 4)
        • Figure 17. Typical Communication Link Start-Up
        • Figure 18. Timing for half-duplex Operation
    • 12.11. Reading the Signaling Word and S/N Data
    • 12.12. Control Registers
      • TABLE 29. Table: Definition of SSTMCR
    • 12.13. SSTM Control Registers
      • TABLE 30. Control Registers
    • 12.14. Configuration Information Bits
      • CI_l[0] Should be set to LO.
      • CI_l[3:2] PLSL. Sets the width of the ESD window. CI_l[2] is LSB, CI_l[3] is MSB. See Application...
      • CI_l[4] CNTLR. Sets the width of the �Central Region�. (NOTE: CNTLR size must be PLSL size).See A...
      • CI_l[5] ACC1RES. DPLL Accumulator 1 reset. See Application Section.
      • CI_l[7:6] WSL. Sets the width of the �Detection Window�. CI_l[6] is LSB, CI_l[7] is MSB. See Appl...
      • CI_h[0] M/SB. Set the SSTM to be a Master (HI) or Slave (LO). Note: must be set to LO in half-dup...
      • CI_h[3:1] T. Number of errors allowed in the UW. CI_h[1]is LSB, CI_h[3] is MSB.
      • CI_h[4] LockSMon. Enables the Locking State Machine when set to HI (see Figure 14. for Locking St...
    • 12.15. RF/IF Analog Interface
      • Figure 19. RFPWR Timing
      • Figure 20. PLLSW Timing (Full-Duplex Mode)
    • 12.16. Programming the SSTM
    • 12.17. PN Sequence and UW Selection
    • 12.18. PN Sequence Selection
      • 1. The four PN sequences should be orthogonal to each other. Two PN sequences A and B are orthogo...
      • (EQ 5)
        • 2. The PN sequences should be even, i.e., each sequence should have the same number of zeros and ...
        • 3. The PN sequences should not have more than four consecutive identical bits.
        • 4. The auto-correlation side lobes of the PN sequences should be less than the auto-correlation o...
        • 5. The cross-correlation of PN sequences between sets (one set being the four orthogonal PN seque...
    • 12.19. UW Selection
      • (EQ 6)
      • (EQ 7)
      • (EQ 8)
    • 12.20. Generating the PN and UW sequences
      • 1. Generate the M and Gold sequences of order N where
      • (EQ 9)
        • 2. Because M and Gold sequences are only bits long, it is necessary to append an additional bit t...
        • 3. Apply the criteria outlined in the previous sections to pick out the good set of PN and UW seq...
  • 13. Power-Saving Modes
    • 13.1. Overview
      • Figure 21. Power Saving Modes & Transitions
    • 13.2. Mode Definition and Transition
      • TABLE 31. Clocking Power-Saving Mode Definition and PSCR
      • TABLE 32. Clocking Power-Saving Mode Definition and PSCR
    • 13.3. FastAll mode (a Clocking Mode)
    • 13.4. SlowAll mode (a Clocking Mode)
    • 13.5. StopAll mode (a Clocking Mode)
    • 13.6. FastPeri mode (a Clocking Mode)
    • 13.7. SlowPeri mode (a Clocking Mode)
    • 13.8. NorPin mode (a Pin State Mode)
    • 13.9. HIZ mode (a Pin State Mode)
      • TABLE 33. Device States in Power-Saving Modes
    • 13.10. Power-Saving Control Register (PSCR)
      • TABLE 34. Summary of PSCR
        • Figure 22. Clock System & Power-saving Control
      • TABLE 35. The Definition of Each PSCR bit
    • 13.11. Stop Release Register (SREL)
      • TABLE 36. Summary of SREL
      • TABLE 37. The Definition of Each SREL bit
  • 14. Port Definitions
    • 14.1. Overview
      • TABLE 38. Port 1 and Port 3 Functions
    • 14.2. Read-Modify-Write Feature
      • TABLE 39. Read-Modify-Write Instructions
    • 14.3. PCR (Port Control Register)
      • TABLE 40. Definition of PCR
        • Figure 23. Pcr & Port Direction Control: Port-0 To 3
    • 14.4. ZCR (Hi-Z Control Register)
      • TABLE 41. Definition of ZCR
    • 14.5. PAD Cell
      • Figure 24. Pad Cell
    • 14.6. P0 (Port-0)
      • Figure 25. PORT-0
      • TABLE 42. Definition of P0
      • TABLE 43. Definition of P0IO
      • TABLE 44. Definition of P0RD
      • TABLE 45. Definition of P0NOPN
    • 14.7. P2 (Port-2)
      • Figure 26. PORT-2
      • TABLE 46. Definition of P2
      • TABLE 47. Definition of P2IO
      • TABLE 48. Definition of P2RD
      • TABLE 49. Definition of P2NOPN
    • 14.8. P1 (Port-1)
      • TABLE 50. Definition of P1
      • TABLE 51. Definition of P1IO
      • TABLE 52. Definition of P1RD
      • TABLE 53. Definition of P1NOPN
    • 14.9. P3 (Port-3)
      • Figure 27. Port 3
      • TABLE 54. Definition of P3
      • TABLE 55. Definition of P3IO
      • TABLE 56. Definition of P3RD
      • TABLE 57. Definition of P3NOPN
    • 14.10. Port-4
      • Figure 28. Port 4
      • TABLE 58. Definition of P4
      • TABLE 59. Definition of P4IO
      • TABLE 60. Definition of P4RD
      • TABLE 61. Definition of P4NOPN
  • 15. External Interrupts
    • 15.1. Overview
      • TABLE 62. IRQi (i = 0 to 5) Mode Selection
    • 15.2. Interrupt Control Block
      • Figure 29. Block Diagram of Interrupt Group-A
      • Figure 30. Block Diagram of Interrupt Group-B
      • Figure 31. Block Diagram of Interrupt Group-C
      • Figure 32. Block Diagram of Interrupt Group-D
      • Figure 33. Block Diagram of Interrupt Group-E
      • Figure 34. Interrupt Control Block Diagram
    • 15.3. Interrupt Request Registers (INT0, INT1, INT2)
      • TABLE 63. Definition of INT0
      • TABLE 64. Definition of INT1
      • TABLE 65. Definition of INT2
      • 15.3.1 Interrupt Source Enable Registers (ISE0, ISE1, ISE2)
        • TABLE 66. Definition of ISE0
        • TABLE 67. Definition of ISE1
        • TABLE 68. Definition of ISE2
      • 15.3.2 Interrupt Group Enable Register (IE)
        • TABLE 69. Definition of IE
      • 15.3.3 Interrupt Priority Register (IP)
        • TABLE 70. Internal Priority and Vector Address
        • TABLE 71. Definition of IP
      • 15.3.4 Interrupt Processing
  • 16. SS1102C Special Modes
    • 16.1. TEST ROM (Using Auxiliary RAM)
    • 16.2. EMULATION MODE
      • TABLE 72. Extra Pins Function
        • Figure 35. Emulation Instruction Fetch From Program Memory
        • Figure 36. Emulation Data Memory Read
        • Figure 37. Emulation Data Memory Write
    • 16.3. MULTICHIP PROGRAM MEMORY INTERFACE
      • TABLE 73. External Memory Interface Pin Description
        • Figure 38. External Instruction Fetch From Program Memory
    • 16.4. EXTERNAL MEMORY MODE
      • TABLE 74. External Memory Pins Description
  • 17. Comparator module
    • 17.1. General Information
    • 17.2. Functional Description
      • TABLE 75. Comparator Main Features
    • 17.3. Block Diagram
      • Figure 39. Comparator Module Block Diagram
    • 17.4. Comparator Control Register
      • TABLE 76. Definition of CMPRCR
    • 17.5. Comparator I/O plot
      • Figure 40. Comparator Output Plot
  • 18. Power-On Reset (POR)
    • 18.1. General
    • 18.2. Operation
    • 18.3. Crystal Oscillator Start-Up Time
      • Figure 41. External Reset Asserted
      • Figure 42. Internal Reset Asserted (Nreset tied to Vcc)
      • Figure 43. Power On Reset functional diagram
  • 19. Low Battery Detect (LBD) - Low Voltage Reset
    • 19.1. General Information
    • 19.2. Functional Description
      • Figure 44. Low Battery Detect Block Diagram
    • 19.3. Low Battery Detect, Low Voltage Reset Control Register
      • TABLE 77. Definition of LBDCR
      • TABLE 78. Description of LBDCR
    • 19.4. TIMING DIAGRAMS
      • Figure 45. Low battery detect interrupt timing
      • Figure 46. Low voltage detect reset timing
  • 20. DC PARAMETRICS
    • 20.1. I/O Characteristics
    • 20.2. Power Characteristics
  • 21. AC Specifications
    • TABLE 79. TIMING TABLE
    • 21.1. TIMING WAVEFORMS
      • Figure 47. Clock Input Waveforms XFIN, XSIN
      • Figure 48. Reset Timing
      • Figure 49. Interrupt Timing
  • 22. Oscillator Pad Characteristics
  • 23. SS1102C I/O PAD Information
    • 23.1. I/O Type 1 and Type 3
      • TABLE 80. I/O-Type 1 and Type 3 Specifications
    • 23.2. I/O Type 2
      • TABLE 81. I/O-Type 2 Specification
    • 23.3. I/O Type 4: Input with static Pullup
      • TABLE 82. I/O-Type 4 Specification
    • 23.4. Oscillator-Pads with Enable-signal
      • TABLE 83. Oscillator Pads Specification
  • 24. PAD ASSIGNMENT TABLES
    • TABLE 84. Standard 52 Pin Device Chip
    • TABLE 85. Special Function Pins/Pads for Bond-out Chip (Development Version)
  • 25. Package
  • 26. Operating temperature:
  • 27. 100-pin Chip.