September 2003
1
Document Control # ML0023 rev 0.1
PIN CONFIGURATIONS
PIN NAMES
A
0
- A
16
Address Inputs
W
Write Enable
DQ
0
- DQ
7
Data In/Out
E
Chip Enable
G
Output Enable
V
CC
Power (+ 3V)
V
SS
Ground
STK16CA8
128K x 8 AutoStorePlusTM nvSRAM
QuantumTrapTM CMOS
Nonvolatile Static RAM
Preliminary
FEATURES
25ns, 35ns and 45ns Access Times
Directly Replaces 128K x 8 Static RAM, Bat-
tery-Backed RAM or EEPROM
Transparent Data Save on Power Down
STORE to QuantumTrapTM Nonvolatile Ele-
ments is Initiated by Software or AutoStore-
PlusTMon Power Down
RECALL to SRAM Initiated by Software or
Power Restore
5mA Typical I
CC
at 200ns Cycle Time
Unlimited READ and WRITE Cycles to SRAM
100-Year Data Retention to Quantum Trap
Single 3V +20%, -10% Operation
Commercial and Industrial Temperatures
32-Pin DIP Package
DESCRIPTION
The Simtek STK16CA8 is a fast static
RAM
with a
nonvolatile element in each static memory cell. The
embedded nonvolatile elements incorporate
Simtek's QuantumTrapTM technology producing the
world's most reliable nonvolatile memory. The
SRAM
provides unlimited read and write cycles, while inde-
pendent, nonvolatile data resides in the nonvolatile
elements. Data transfers from the
SRAM
to the non-
volatile elements (the
STORE
operation) can take
place automatically on power down or under soft-
ware control. An internal capacitor guarantees the
STORE
operation, even under extreme power-down
slew rates or loss of power from "hot swapping".
Transfers from the nonvolatile elements to the
SRAM
(the
RECALL
operation) take place automatically on
restoration of power. Initiation of
STORE
and
RECALL
cycles can also be controlled by entering control
sequences on the
SRAM
inputs. The STK16CA8 is
pin-compatible with 128k x 8
SRAMs
and battery-
backed
SRAMs
, allowing direct substitution while
providing superior performance.
BLOCK DIAGRAM
COLUMN I/O
COLUMN DEC
STATIC RAM
ARRAY
1024 x 1024
ROW DECODER
I
N
PU
T BU
F
F
ER
S
Quantum Trap
1024 x 1024
STORE/
RECALL
CONTROL
STORE
RECALL
POWER
CONTROL
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
SOFTWARE
DETECT
G
E
W
V
CC
A
0
- A
15
A
16
A
0
A
1
A
2
A
3
A
4
A
10
A
11
A
13
A
8
A
9
A
11
NC
A
16
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
V
CC
A
15
W
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
14
V
CC
A
15
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
NC
STK16CA8
September 2003
2
Document Control # ML0023 rev 0.1
ABSOLUTE MAXIMUM RATINGS
a
Power Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 0.5V to +3.9V
Voltage on Input Relative to V
SS
. . . . . . . . . .0.5V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
. . . . . . . . . . . . . . . . . . . . . .0.5V to (V
CC
+ 0.5V)
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .55
C to 125
C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .65
C to 150
C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Note a: Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con-
ditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
DC CHARACTERISTICS
(V
CC
= 3.0V
+
20%, -10%)
Note b: I
CC1
and I
CC3
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: I
CC2
is the average current required for the duration of the
STORE
cycle (t
STORE
) .
Note d: E
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
SYMBOL
PARAMETER
COMMERCIAL
INDUSTRIAL
UNITS
NOTES
MIN
MAX
MIN
MAX
I
CC1
b
Average V
CC
Current
50
40
35
55
45
35
mA
mA
mA
t
AVAV
= 25ns
t
AVAV
= 35ns
t
AVAV
= 45ns
I
CC2
c
Average V
CC
Current during STORE
1.5
1.5
mA
All Inputs Don't Care, V
CC
= max
I
CC3
b
Average V
CC
Current at t
AVAV
= 200ns
3V, 25C, Typical
5
5
mA
W
(V
CC
0.2V)
All Others Cycling, CMOS Levels
I
SB
d
V
CC
Standby Current
(Standby, Stable CMOS Input Levels)
1
1
mA
E
(V
CC
0.2V)
All Others V
IN
0.2V or
(V
CC
0.2V)
I
ILK
Input Leakage Current
1
1
A
V
CC
= max
V
IN
= V
SS
to V
CC
I
OLK
Off-State Output Leakage Current
1
1
A
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
V
IH
V
IH
Input Logic "1" Voltage
2.0
V
CC
+ .3
2.0
V
CC
+ .3
V
All Inputs
V
IL
Input Logic "0" Voltage
V
SS
.5
0.8
V
SS
.5
0.8
V
All Inputs
V
OH
Output Logic "1" Voltage
2.4
2.4
V
I
OUT
= 2mA
V
OL
Output Logic "0" Voltage
0.4
0.4
V
I
OUT
= 4mA
T
A
Operating Temperature
0
70
40
85
C
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V
Input Rise and Fall Times
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
CAPACITANCE
e
(T
A
= 25
C, f = 1.0MHz)
Note e: These parameters are guaranteed but not tested.
SYMBOL
PARAMETER
MAX
UNITS
CONDITIONS
C
IN
Input Capacitance
5
pF
V = 0 to 3V
C
OUT
Output Capacitance
7
pF
V = 0 to 3V
Figure 1
:
AC Output Loading
577 Ohms
30 pF
789 Ohms
3.0V
INCLUDING
SCOPE AND
OUTPUT
FIXTURE
STK16CA8
September 2003
3
Document Control # ML0023 rev 0.1
SRAM READ CYCLES #1 & #2
(V
CC
= 3.0V +20%, -10%)
Note f:
W must be high during SRAM READ cycles.
Note g: Device is continuously selected with E and G both low.
Note h: Measured
200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlled
f,
g
SRAM READ CYCLE #2: E Controlled
f
NO.
SYMBOLS
PARAMETER
STK16CA8-25
STK16CA8-35
STK16CA8-45
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1
t
ELQV
t
ACS
Chip Enable Access Time
25
35
45
ns
2
t
AVAV
f
t
RC
Read Cycle Time
25
35
45
ns
3
t
AVQV
g
t
AA
Address Access Time
25
35
45
ns
4
t
GLQV
t
OE
Output Enable to Data Valid
10
15
20
ns
5
t
AXQX
g
t
OH
Output Hold after Address Change
3
3
3
ns
6
t
ELQX
t
LZ
Chip Enable to Output Active
3
3
3
ns
7
t
EHQZ
h
t
HZ
Chip Disable to Output Inactive
10
13
15
ns
8
t
GLQX
t
OLZ
Output Enable to Output Active
0
0
0
ns
9
t
GHQZ
h
t
OHZ
Output Disable to Output Inactive
10
13
15
ns
10
t
ELICCH
e
t
PA
Chip Enable to Power Active
0
0
0
ns
11
t
EHICCL
e
t
PS
Chip Disable to Power Standby
25
35
45
ns
DATA VALID
5
t
AXQX
3
t
AVQV
DQ (DATA OUT)
ADDRESS
2
t
AVAV
6
t
ELQX
STANDBY
DATA VALID
4
t
GLQV
DQ (DATA OUT)
E
ADDRESS
2
t
AVAV
G
I
CC
ACTIVE
10
t
ELICCH
11
t
EHICCL
7
t
EHQZ
8
t
GLQX
1
t
ELQV
9
t
GHQZ
STK16CA8
September 2003
4
Document Control # ML0023 rev 0.1
SRAM WRITE CYCLES #1 & #2
(V
CC
= 3.0V
+
20%, -10%)
Note i:
If W is low when E goes low, the outputs remain in the high-impedance state.
Note j:
E or W must be
V
IH
during address transitions.
SRAM WRITE CYCLE #1: W Controlled
j
SRAM WRITE CYCLE #2: E Controlled
j
NO.
SYMBOLS
PARAMETER
STK16CA8-25
STK16CA8-35
STK16CA8-45
UNITS
#1
#2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
12
t
AVAV
t
AVAV
t
WC
Write Cycle Time
25
35
45
ns
13
t
WLWH
t
WLEH
t
WP
Write Pulse Width
20
25
30
ns
14
t
ELWH
t
ELEH
t
CW
Chip Enable to End of Write
20
25
30
ns
15
t
DVWH
t
DVEH
t
DW
Data Set-up to End of Write
10
12
15
ns
16
t
WHDX
t
EHDX
t
DH
Data Hold after End of Write
0
0
0
ns
17
t
AVWH
t
AVEH
t
AW
Address Set-up to End of Write
20
25
30
ns
18
t
AVWL
t
AVEL
t
AS
Address Set-up to Start of Write
0
0
0
ns
19
t
WHAX
t
EHAX
t
WR
Address Hold after End of Write
0
0
0
ns
20
t
WLQZ
h, i
t
WZ
Write Enable to Output Disable
10
13
15
ns
21
t
WHQX
t
OW
Output Active after End of Write
3
3
3
ns
PREVIOUS DATA
DATA OUT
E
ADDRESS
12
t
AVAV
W
16
t
WHDX
DATA IN
19
t
WHAX
13
t
WLWH
18
t
AVWL
17
t
AVWH
DATA VALID
20
t
WLQZ
15
t
DVWH
HIGH IMPEDANCE
21
t
WHQX
14
t
ELWH
DATA IN
12
t
AVAV
16
t
EHDX
13
t
WLEH
19
t
EHAX
18
t
AVEL
17
t
AVEH
DATA VALID
15
t
DVEH
HIGH IMPEDANCE
14
t
ELEH
DATA OUT
E
ADDRESS
W
DATA IN
STK16CA8
September 2003
5
Document Control # ML0023 rev 0.1
MODE SELECTION
Note k: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note l:
While there are 17 addresses on the STK16CA8, only the lower 16 are used to control software modes.
Note m: I/O state depends on the state of G. The I/O table shown assumes G low.
E
W
G
A
15
- A
0
(hex)
MODE
I/O
POWER
NOTES
H
X
X
X
Not Selected
Output High Z
Standby
L
H
L
X
Read SRAM
Output Data
Active
L
L
X
X
Write SRAM
Input Data
Active
L
H
L
4E38
B1C7
83E0
7C1F
703F
8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Autostore Inhibit
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
k, l, m
L
H
L
4E38
B1C7
83E0
7C1F
703F
4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Autostore inhibit off
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
k, l, m
L
H
L
4E38
B1C7
83E0
7C1F
703F
8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
l
CC2
k, l, m
L
H
L
4E38
B1C7
83E0
7C1F
703F
4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l, m
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