3
DESCRIPTION...
The HS574A/SP674A Series are complete 12bit successiveapproximation A/D converters
integrated on a single die with tri-state output latches, an internal reference, clock and a sample
hold. They feature 12bit linearity over temperature, low power dissipation and fast conversion
time. They are available in commercial and military temperature ranges.
s
Complete 12bit A/D Converters with Sample
Hold, Reference, Clock and Tristate Outputs
s
Low Power Dissipation -- 110mW Maximum
s
12Bit Linearity Over Temperature
s
Fast Conversion time:
25
s Max (HS574A)
15
s Max (SP674A)
s
Monolithic Construction
HS574A/SP674A
12Bit Sampling A/D Converters
1
14
13
12
11
10
9
8
7
6
5
4
3
2
28
15
16
17
18
19
20
21
22
23
24
25
26
27
STS
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DGND
VLOGIC 12/8
CS
A0
R/C
CE
VCC
REF
OUT
AGND
REF
IN
VEE
BIP
OFF
10V
IN
20V
IN
NIBBLE A
NIBBLE B
NIBBLE C
THREESTATE BUFFERS AND CONTROL
N/C
7.5K
15K
15K
7.5K
7.5K
OFFSET/GAIN
TRIM
12BIT
CAPACITANCE
DAC
COMP
REF
CONTROL LOGIC
12BIT SAR
OSC
4
ABSOLUTE MAXIMUM RATINGS
V
CC
to Digital Common .................................................. 0 to +16.5V
V
LOGIC
to Digital Common ................................................... 0 to +7V
Analog Common to Digital Common .........................................
1V
Control Inputs to Digital Common ................. 0.5V to V
LOGIC
+0.5V
(CE, CS, A
0
, 12/8, R/C)
Analog Inputs to Analog Common ......................................
16.5V
(REF IN, BIP OFF, 10V
IN
)
20V
IN
to Analog Common ........................................................
24V
REF OUT ............................................... Indefinite short to common
Momentary short to V
CC
Power Dissipation ............................................................. 1000mW
Lead Temperature, Soldering ................................... 300C, 10Sec
J/C ................................................................................... 45C/W
MTBF25C Ground Base ................................ 2.915 million hours
MTBF125C Missile Launch ...................... 10.16 thousand hours
Inputs exceeding +30% or 30% of FS will cause erratic performance.
CAUTION:
ESD (ElectroStatic Discharge) sensitive
device. Permanent damage may occur on
unconnected devices subject to high energy
electrostatic fields. Unused devices must be
stored in conductive foam or shunts.
Personnel should be properly grounded prior
to handling this device. The protective foam
should be discharged to the destination
socket before devices are removed.
SPECIFICATIONS
(Typical @ 25
C with V
CC
= +15V, V
EE
= 0V, V
LOGIC
= +5V unless otherwise noted)
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONDITIONS
RESOLUTION
All models
12
Bits
ANALOG INPUTS
Input Ranges
Bipolar
5,
10
V
Unipolar
0 to +10, 0 to +20
V
Input Impedance
10 Volt Input
3.75
6.25
K
20 Volt Input
15
25
K
DIGITAL INPUTS
Logic Inputs CE, CS R/C, A
O
, 12/8
Logic 1
+2.4
+5.5
V
Logic 0
0.3
+0.8
V
Current
0.1
50
A
0V to +5.5V Input
Capacitance
5
pF
12/8 Control Input
Hardwire to V
LOGIC
or DIGITAL COMMON (SP574A only)
DIGITAL OUTPUTS
Logic Outputs DB
11
DB
0
, STS
Logic 1
+2.4
V
I
SOURCE
500
A
Logic 0
+0.4
V
I
SINK
1.6mA
Leakage (High Z State)
40
A
Data bits only
Capacitance
5
pF
Parallel Data Output Codes
Unipolar
Positive true binary
Bipolar
Positive true offset binary
REFERENCE
Internal
10.00
0.1
V
Output Current
2
mA
Note 1
CONVERSION TIME
HS574A
12Bit Conversion
13
25
s
8Bit Conversion
10
19
s
SP674A
12Bit Conversion
9
15
s
8Bit Conversion
6
11.25
s
5
SPECIFICATIONS
(continued)
(Typical @ 25
C with V
CC
= +15V, V
EE
= 0V, V
LOGIC
= +5V unless otherwise noted)
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONDITIONS
ACCURACY
Linearity Error @ 25
C
J, S
1.0
LSB
@ 25
C and T
MIN
to T
MAX
K, L, T, U
0.5
LSB
@ 25
C and T
MIN
to T
MAX
Differential Linearity Error
Note 2
J, S
11
Bits
@ 25
C
11
Bits
T
MIN
to T
MAX
K, L, T, U
12
Bits
@ 25
C
12
Bits
T
MIN
to T
MAX
Offset
Note3
Unipolar
2
LSB
Bipolar
J, S
10
LSB
K, L, T, U
4
LSB
Full Scale (Gain) Error
% of full scale; T
MIN
to T
MAX
0.3
%FS
Note 4
J
0.5
%FS
No adjustment @ 25
C
0.22
%FS
With adjustment @ 25
C
K
0.4
%FS
No adjustment @ 25
C
0.12
%FS
With adjustment @ 25
C
L
0.35
%FS
No adjustment @ 25
C
0.05
%FS
With adjustment @ 25
C
S
0.8
%FS
No adjustment @ 25
C
0.5
%FS
With adjustment @ 25
C
T
0.6
%FS
No adjustment @ 25
C
0.25
%FS
With adjustment @ 25
C
U
0.4
%FS
No adjustment @ 25
C
0.12
%FS
With adjustment @ 25
C
STABILITY
Unipolar Offset
J
10
ppm/
C
T
MIN
to T
MAX
K, L, S
5
ppm/
C
T
MIN
to T
MAX
T, U
2.5
ppm/
C
T
MIN
to T
MAX
Bipolar Offset
J, S
10
ppm/
C
T
MIN
to T
MAX
K, L, T
5
ppm/
C
T
MIN
to T
MAX
U
2.5
ppm/
C
T
MIN
to T
MAX
Gain (Scale Factor)
J, S
50
ppm/
C
T
MIN
to T
MAX
K, T
25
ppm/
C
T
MIN
to T
MAX
L, U
10
ppm/
C
T
MIN
to T
MAX
PSRR
V
LOGIC
0.5
LSB
+4.5V
V
LOGIC
+5.5V
V
CC
Note 5
J, S
2
LSB
K, L, T, U
1
LSB
POWER REQUIREMENTS
V
LOGIC
+4.5
+5.5
V
I
LOGIC
HS574A
1
3
mA
SP674A
1
3
mA
V
CC
+11.4
+16.5
V
I
CC
HS574A
7
9
mA
SP674A
7
9
mA
6
SPECIFICATIONS
(continued)
(Typical @ 25
C with V
CC
= +15V, V
EE
= 0V, V
LOGIC
= +5V unless otherwise noted)
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONDITIONS
Power Dissipation
HS574A
110
150
mW
SP674A
110
150
mW
ENVIRONMENTAL
Operating Temperature Range
J, K, L
0
+70
C
S, T, U
55
+125
C
Storage Temperature Range
J, K, L
40
+85
C
A, S, T, U
65
+150
C
Notes:
1.
Available for external loads. External load should not change during conversion. When supplying an
external load and operating on a +12V supply, a buffer amplifier must be provided for the reference
output.
2.
Minimum resolution for which no missing codes are guaranteed.
3.
Externally adjustable to zero. See
Calibration information.
4.
Fixed 50
resistor between REF OUT and REF IN.
5.
+13.5V
V
CC
+16.5V or +11.4V
V
CC
+12.6V.
6.
Specifications are identical for all models unless otherwise noted.
PIN ASSIGNMENTS...
PIN
FUNCTION
PIN
FUNCTION
1
V
LOGIC
28
STS
2
12/8
27
DB
11
(MSB)
3
CS
26
DB
10
4
A
0
25
DB
9
5
R/C
24
DB
8
6
CE
23
DB
7
7
V
CC
22
DB
6
8
REF OUT
21
DB
5
9
ANA GND(AC)
20
DB
4
10
REF IN
19
DB
3
11
N/C*
18
DB
2
12
BIP OFF
17
DB
1
13
10V
IN
16
DB
0
(LSB)
14
20V
IN
15
DIG. GND
*HS574A This pin is not connected to the device; it
can be tied to 15V, ground, or left floating.
*SP674A This pin is not connected to the device; V
EE
is generated internally.
7
FEATURES...
The HS574A/SP674A feature standard bipolar
and unipolar input ranges of 10V and 20V. Input
ranges are controlled by a bipolar offset pin and
laser-trimmed for specified linearity, gain and
offset accuracy. Power requirements are +5V
and +12V to +15V with a maximum dissipation
of 150mW at the specified voltages. Conversion
times of 8
s, 10
s, 15
s and 25
s are available,
as are units with 10, 25 or 50ppm/
C temperature
coefficients for flexible matching to specific
application requirements.
The HS574A/SP674A are available in six prod-
uct grades for each conversion time. The J, K
and L models are specified over 0C to + 70C
commercial temperature range; the S, T and
U models are specified over the 55C to +125C
military temperature range. Processing in accor-
dance with MILSTD883C is also available.
The HS574A/SP674A are packaged in a 28pin
CerDIP. Please consult the factory for other
packaging options.
the LSB at the beginning of the conversion cycle
to provide an output voltage from the CDAC that
is equal to the input signal voltage (which is
divided by the input voltage divider network).
The comparator determines whether the addition
of each successivelyweighted bit voltage causes
the CDAC output voltage summation to be greater
or less than the input voltage; if the sum is less,
the bit is left on; if more, the bit is turned off.
After testing all the bits, the SAR contains a 12
bit binary code which accurately represents the
input signal to within
1
/
2
LSB.
The internal reference provides the voltage refer-
ence to the CDAC with excellent stability over
temperature and time. The reference is trimmed
to 10.00 Volts
1% and can supply up to 2mA to
an external load in addition to that required to
drive the reference input resistor (1mA) and
offset resistor (1mA) when operating with
15V
supplies. If the HS574A/SP674A is used with
12V supplies, or if external current must be
supplied over the full temperature range, an
external buffer amplifier is recommended. Any
external load on the HS574A/SP674A reference
must remain constant during conversion.
The sample and hold is a default function by
virtue of the CDAC architecture. Therefore the
majority of the S/H specifications are included
within the A/D specifications.
SampleandHold Function
Although there is no sample-and-hold circuit in
the classical sense, the sampling nature of the
capacitive DAC makes the HS574A/SP674A
appear to have a built in sample and hold. This
sample and hold action substantially increases
the usefulness of the HS574A/SP674A over that
of similar competing devices.
Note that even though the user may use an
external sample and hold for very high fre-
quency inputs, the internal sample and hold still
provides a very useful isolation function. Once
the internal sample is taken by the CDAC capaci-
tance, the input of the HS574A/SP674A is dis-
connected from the input. This prevents tran-
sients occurring during conversion from being
inflicted upon the attached buffer. All other 574/
674 circuits will cause a transient load current on
CIRCUIT OPERATION...
The HS574A/SP674A are complete 12bit ana-
log-to-digital converters with integral voltage
reference, comparator, successiveapproxima-
tion register (SAR), sampleandhold, clock,
output buffers and control circuitry. The high
level of integration of the HS574A/SP674A
means they require few external components.
When the control section of the HS574A/SP674A
initiates a conversion command, the clock is
enabled and the successiveapproximation reg-
ister is reset to all zeros. Once the conversion
cycle begins, it can not be stopped or restarted
and data is not available from the output buffers.
The SAR, timed by the clock, sequences through
the conversion cycle and returns an endof
convert flag to the control section of the ADC.
The clock is then disabled by the control section,
the output status goes low, and the control sec-
tion is enabled to allow the data to be read by
external command.
The internal HS574A/SP674A 12bit CDAC is
sequenced by the SAR starting from the MSB to
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