1
Rev. 6/25/03
SP3203
Copyright 2003 Sipex Corporation
3V RS-232 Serial Transceiver with Logic Selector
The SP3203 provides a RS-232 transceiver solution for portable and hand-held applications
such as palmtops, PDA's and cell phones. The SP3203 uses an internal high-efficiency,
charge-pump that requires only 0.1
F capacitors during 3.3V operation. This charge pump
and Sipex's driver architecture allow the SP3203 to deliver compliant RS-232 performance
from a single power supply ranging from +3.0V to +5.5V.
The SP3203 is a 3-driver/2-receiver device, with a unique V
L
pin to program the TTL input
and output logic levels to allow interoperation in mixed-logic voltage systems such as PDA's
and cell phones. Receiver outputs will not exceed V
L
for V
OH
and transmitter input logic levels
are scaled by the magnitude of the V
L
input.
3 Driver/ 2 Receiver Architecture
Logic selector function (V
L
) sets TTL
input/output levels for mixed logic
systems
Meets true EIA/TIA-232-F Standards
from a +3.0V to +5.5V power supply
Interoperable with EIA/TIA-232 and
adheres to EIA/TIA-562 down to a
+2.7V power source
Minimum 250Kbps data rate under load
Regulated Charge Pump Yields Stable
RS-232 Outputs Regardless of V
CC
Variations
ESD Specifications:
+2kV Human Body Model
DESCRIPTION
Applications
Palmtops
Cell phone Data Cables
PDA's
SP3203
Rev. 6/25/03
SP3203
Copyright 2003 Sipex Corporation
2
NOTE 1: V
+
and V
-
can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V.
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the
device at these ratings or any other above those indicated
in the operation sections of the specifications below is not
implied. Exposure to absolute maximum rating conditions
for extended periods of time may affect reliability and cause
permanent damage to the device.
V
CC
..................................................................-0.3V to +6.0V
V
+
(NOTE 1)..................................................-0.3V to +7.0V
V
-
(NOTE 1)...................................................+0.3V to -7.0V
V
+
+ |V
-
| (NOTE 1).........................................................+13V
I
CC
(DC V
CC
or current)...........................................+100mA
Input Voltages
TxIN, SHUTDOWN = GND..........................-0.3V to +6.0V
RxIN...............................................................................+25V
(V
CC
= V
L
= +3V to +5.5V, C1-C4 = 0.1
F, tested at +3.3V +10%, C1 = 0.047
F, C2-C4 = 0.33
F, tested at +5.0V +10%, T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at V
CC
= V
L
+3.3V, T
A
= +25
C.)
SPECIFICATIONS
Output Voltages
TxOUT.............................................................+13.2V
RxOUT..............................................-0.3V to (V
L
+ 0.3V)
Short-Circuit Duration
TxOUT................................................................Continuous
Storage Temperature...............................-65
C to +150
C
Power Dissipation per Packages
20-Pin TSSOP
(derate 7.0mW/
C above+70
C)............................560mW
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3
Rev. 6/25/03
SP3203
Copyright 2003 Sipex Corporation
SPECIFICATIONS (continued)
(V
CC
= V
L
= +3V to +5.5V, C1-C4 = 0.1
F, tested at +3.3V +10%, C1 = 0.047
F, C2-C4 = 0.33
F, tested at +5.0V +10%, T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at V
CC
= V
L
+3.3V, T
A
= +25
C.)
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Note 2. Transmitter skew is measured at the transmitter zero crosspoint.
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Rev. 6/25/03
SP3203
Copyright 2003 Sipex Corporation
4
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5
Rev. 6/25/03
SP3203
Copyright 2003 Sipex Corporation
Figure 7. SP3203 Pinout Configuration
T
1
IN
1
2
3
4
17
18
19
20
5
6
7
16
15
14
SHUTDOWN
V+
C1+
GND
V
CC
8
9
10
11
12
13
T
3
IN
R
2
OUT
T
2
IN
R
1
OUT
V
L
SP3203
C
1
-
C
2
+
C
2
-
V-
T
1
OUT
T
2
OUT
T
3
OUT
R
1
IN
R
2
IN
Rev. 6/25/03
SP3203
Copyright 2003 Sipex Corporation
6
Figure 8. SP3203 Typical Operating Circuit
SP3203
1
3
5
4
2
6
19
GND
T
1
IN
T
2
IN
C1+
C1-
C2+
C2-
V+
V-
V
CC
7
8
0.1
F
0.1
F
0.1
F
+
C2
C5
C1
+
+
C3
C4
+
+
0.1
F
0.1
F
17
16
RS-232
OUTPUTS
RS-232
INPUTS
TTL/CMOS
INPUTS
+3V to +5.5V
18
5K
R
1
OUT
11
14
5K
R
2
IN
R
2
OUT
10
13
TTL/CMOS
OUTPUTS
R
1
IN
T
2
OUT
T
1
OUT
Shutdown
20
12
V
L
T
3
IN
9
15
T
3
OUT
7
Rev. 6/25/03
SP3203
Copyright 2003 Sipex Corporation
DESCRIPTION
The SP3203 is a 3-driver/2-receiver device that
can be operated as a full duplex, RS-232 serial
transceiver with the 3rd driver acting as a control
line allowing a Ring Indicator (RI) signal to alert
the UART on the PC.
This transceiver meet the EIA/TIA-232 and ITU-
T V.28/V.24 communication protocols and can
be implemented in battery-powered, portable, or
hand-held applications such as notebook or
palmtop computers, PDA's and cell phones. The
SP3203 devices feature Sipex's proprietary and
patented (U.S.
#5,306,954) on-board charge pump
circuitry that generates
5.5V RS-232 voltage
levels from a single +3.0V to +5.5V power
supply. The SP3203 devices can operate at a
minimum data range of 250kbps, driving a single
driver. The SP3203 is a 3-driver/2-receiver
device.
THEORY OF OPERATION
The SP3203 contains four basic circuit blocks:
1. drivers, 2. receivers, 3. a Sipex proprietary
charge pump and 4. V
L
circuitry.
Drivers
The drivers are inverting level transmitters that
convert TTL or CMOS logic levels to 5.0V EIA/
TIA-232 levels with an inverted sense relative to
the input logic levels. Typically, the RS-232
output voltage swing is +5.4V with no load and
+5V minimum fully loaded. The driver outputs
are protected against infinite short-circuits to
ground without degradation in reliability. These
drivers comply with the EIA-TIA-232F and all
previous RS-232 versions. The driver output
stages are turned off (High Impedance) when the
device is in shutdown mode.
The drivers typically can operate at a data rate
of 250Kbps. The drivers can guarantee a data
rate of 120Kbps fully loaded with 3K
in
parallel with 1000pF, ensuring compatibility
with PC-to-PC communication software.
The slew rate of the driver output is internally
limited to a maximum of 30V/
s in order to
meet the EIA standards (EIA RS-232D 2.1.7,
Paragraph 5). The transition of the loaded
output from HIGH to LOW also meets the
monotonicity requirements of the standard.
The SP3203 driver can maintain high data rates
up to 250Kbps with a single driver loaded. Fig-
ure 9 shows a loopback test circuit used to test
the RS-232 Drivers. Figure 10 shows the test
results of the loopback circuit with all three
drivers active at 120Kbps with typical RS-232
loads in parallel with 1000pF capacitors. Figure
11 shows the test results where one driver was
active at 250Kbps and all three drivers loaded
with an RS-232 receiver in parallel with a 1000pF
capacitor. The transmitter inputs do not have
pull-up resistors. Connect unused inputs to
ground or V
L
Receivers
The receivers convert
5.0V EIA/TIA-232
levels to TTL or CMOS logic output levels.
Receivers are disabled when in shutdown. The
truth table logic of the SP3203 driver and re-
ceiver outputs can be found in Table 1.
Since receiver input is usually from a transmis-
sion line where long cable lengths and system
interference can degrade the signal, the inputs
have a typical hysteresis margin of 500mV. This
ensures that the receiver is immune to noisy
transmission lines. Should an input be left un-
connected, an internal 5K
pulldown resistor to
ground will commit the output of the receiver to
a HIGH state.
Charge Pump
The charge pump is a Sipexpatented design
(U.S. #5,306,954) and uses a unique approach
compared to older lessefficient designs. The
charge pump still requires four external
capacitors, but uses a fourphase voltage
shifting technique to attain symmetrical 5.5V
power supplies. The internal power supply
Rev. 6/25/03
SP3203
Copyright 2003 Sipex Corporation
8
consists of a regulated dual charge pump that
provides output voltages of 5.5V regardless of
the input voltage (V
CC
) over the +3.0V to +5.5V
range. This is important to maintain compliant
RS-232 levels regardless of power supply
fluctuations.
The charge pump operates in a discontinuous
mode using an internal oscillator. If the output
voltages are less than a of 5.5V, the charge
pump is enabled. If the output voltages exceed
a of 5.5V, the charge pump is disabled. This
oscillator controls the four phases of the voltage
shifting (Figure 12). A description of each phase
follows.
V
SS
Charge Storage-Phase 1(Figure 13)
During this phase of the clock cycle, the positive
side of capacitors C
1
and C
2
are initially charged
to V
CC
. C
l+
is then switched to GND and the
charge in C
1
is transferred to C
2
. Since C
2+
is
connected to V
CC
, the voltage potential across
capacitor C
2
is now 2 times V
CC
.
Table 1. SHUTDOWN Truth Table.
(Note: When device in shutdown, the SP3203's charge pump is turned off
and V+ decays to V
CC.
V- is pulled to ground and the transmitter outputs
are disabled as High Impendance).
Figure 9. Loopback Test Circuit for RS-232 Driver Data
Transmission Rates
V
SS
Transfer-Phase 2 (Figure 14)
Phase two of the clock connects the negative
terminal of C
2
to the V
SS
storage capacitor and
the positive terminal of C
2
to GND. This
transfers a negative generated voltage to C
3
.
This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the voltage
to C
3
, the positive side of capacitor C
1
is
switched to V
CC
and the negative side is
connected to GND
.
V
DD
Charge Storage-Phase 3 (Figure 15)
The third phase of the clock is identical to the
first phase -- the charge transferred in C
1
pro-
Figure 10. Loopback Test Circuit Result at 120Kbps
(All Drivers Fully Loaded)
Figure 11. Loopback Test Circuit result at 250Kbps
(All Drivers Fully Loaded)
SP3203
1
3
5
4
2
6
19
GND
T
1
IN
T
X
IN
C1+
C1-
C2+
C2-
V+
V-
V
CC
0.1
F
0.1
F
0.1
F
+
C2
C5
C1
+
+
C3
C4
+
+
0.1
F
0.1
F
TTL/CMOS
INPUTS
+3V to +5V
18
SHUTDOWN
20
5K
R
1
OUT
5K
R
X
IN
R
X
OUT
TTL/CMOS
OUTPUTS
R
1
IN
T
X
OUT
T
1
OUT
V
CC
1000pF
1000pF
12
V L
+3V to +5.5V
Ch1
Ch3
3
1
2
T
T
T
T
[
]
T1 IN
T1 OUT
R1 OUT
5.00V
Ch2 5.00V M 5.00
s Ch1
0V
5.00V
3
1
2
T
T
T
T
[
]
T1 IN
T1 OUT
R1 OUT
Ch1
Ch3
5.00V
Ch2 5.00V M 2.50
s Ch1
0V
5.00V
3
0
2
3
P
S
:
E
C
I
V
E
D
N
W
O
D
T
U
H
S
T
X
T
U
O
R
X
T
U
O
e
g
r
a
h
C
p
m
u
P
0
Z
-
h
g
i
H
Z
-
h
g
i
H
e
v
i
t
c
a
n
I
1
e
v
i
t
c
A
e
v
i
t
c
A
e
v
i
t
c
A
9
Rev. 6/25/03
SP3203
Copyright 2003 Sipex Corporation
duces V
CC
in the negative terminal of C
1
, which
is applied to the negative side of capacitor C
2
.
Since C
2+
is at V
CC
, the voltage potential across
C
2
is 2 times V
CC
.
V
DD
Transfer-Phase 4 (Figure 16)
The fourth phase of the clock connects the nega-
tive terminal of C
2
to GND, and transfers this
positive generated voltage across C
2
to C
4
, the
V
DD
storage capacitor. This voltage is regulated
to +5.5V. At this voltage, the internal oscillator
is disabled. Simultaneous with the transfer of the
voltage to C
4
, positive side of capacitor C
1
is
switched to V
CC
and the negative side is con-
nected to GND, allowing the charge pump cycle
to begin again. The charge pump cycle will
continue as long as the operational conditions for
the internal oscillator are present.
Since both V
+
and V
are separately generated
from V
CC
, in a noload condition, V
+
and V
will
be symmetrical. Older charge pump approaches
that generate V
from V
+
will show a decrease in
the magnitude of V
compared to V
+
due to the
inherent ineffiencies in the design.
The clock rate for the charge pump is typically
operates at 250kHz. The external capacitors are
usually 0.1
F with a 16V breakdown voltage
rating.
V
L
Supply Level
Current RS-232 serial tranceivers are designed
with fixed 5V or 3.3V TTL input/output voltages
levels. The V
L
function in the SP3203 allows the
end user to set the TTL input/output voltage
levels independent of V
CC
. By connecting V
L
to
the main logic bus of system, the TTL input/
output limits and threshold are reset to interface
with the on board low voltage logic circuity.
:
e
l
b
a
T
n
o
i
t
c
e
l
e
S
r
o
t
i
c
a
p
a
C
V
C
C
)
V
(
(
1
C
)
F
(
4
C
-
2
C
)
F
6
.
3
o
t
0
.
3
1
.
0
1
.
0
5
.
5
o
t
5
.
4
7
4
0
.
0
3
3
.
0
5
.
5
o
t
0
.
3
2
2
.
0
1
Rev. 6/25/03
SP3203
Copyright 2003 Sipex Corporation
10
Figure 14. Charge Pump -- Phase 3 - V
SS
Charge Transfer
Figure 12. Charge Pump Waveforms
Figure 15. Charge Pump -- Phase 2 - V
DD
Charge Storage
Figure 16. Charge Pump -- Phase 1 - V
DD
Charge Transfer
Figure 13. Charge Pump -- Phase 4 - V
SS
Charge Storage
Ch1 2.00V
Ch2
2.00V M 1.00
s Ch1 1.96V
2
1
T
T
[
]
T
2
+6V
a) C
2+
b) C
2
-
-6V
0V
0V
11
Rev. 6/25/03
SP3203
Copyright 2003 Sipex Corporation
Figure 17. Circuit for the connectivity of the SP3203 with a DB-9 connector
6
7
8
9
1
2
3
4
5
DB-9
Connector
6. DCE Ready
7. Request to Send
8. Clear to Send
9. Ring Indicator
DB-9 Connector Pins:
1. Received Line Signal Detector
2. Received Data
3. Transmitted Data
4. Data Terminal Ready
5. Signal Ground (Common)
SP3203
1
3
5
4
2
6
19
GND
C1+
C1-
C2+
C2-
V+
V-
V
CC
7
8
9
11
10
0.1F
0.1F
0.1F
+
C2
C5
C1
+
+
C3
C4
+
+
0.1F
0.1F
17
16
15
14
13
18
T
1
IN
R
1
OUT
R
1
IN
T
2
OUT
T
2
IN
T
3
IN
T
3
OUT
T
1
OUT
R
2
IN
R
2
OUT
12
V
L
Shutdown
20
Rev. 6/25/03
SP3203
Copyright 2003 Sipex Corporation
12
ESD TOLERANCE
The SP3203 incorporates ruggedized ESD cells
on all driver output and receiver input pins.
The Human Body Model has been the generally
accepted ESD testing method for semiconductors.
This method is also specified in MIL-STD-883,
Method 3015.7 for ESD testing. The premise of
this ESD test is to simulate the human body's
potential to store electro-static energy and
Figure 18. ESD Test Circuit for Human Body Model
R
R
C
C
C
C
S
S
R
R
S
S
SW1
SW1
SW2
SW2
R
C
Device
Under
Test
DC Power
Source
C
S
R
S
SW1
SW2
discharge it to an integrated circuit. The
simulation is performed by using a test model as
shown in Figure 18. This method will test the
IC's capability to withstand an ESD transient
during normal handling such as in manufacturing
areas where the ICs tend to be handled frequently.
For the Human Body Model, the current limiting
resistor (R
S
) and the source capacitor (C
S
) are
15k
and 100pF, respectively.
13
Rev. 6/25/03
SP3203
Copyright 2003 Sipex Corporation
Gage
Plane
1.0 OIA
e
0.169 (4.30)
0.177 (4.50)
0.252 BSC (6.4 BSC)
0'-8' 12'REF
0.039 (1.0)
e/2
0.039 (1.0)
0.126 BSC (3.2 BSC)
0.007 (0.19)
0.012 (0.30)
0.033 (0.85)
0.037 (0.95)
0.002 (0.05)
0.006 (0.15)
0.043 (1.10) Max
(
3)
1.0 REF
0.020 (0.50)
0.026 (0.75)
(
1)
0.004 (0.09) Min
0.004 (0.09) Min
0.010 (0.25)
(
2)
0.008 (0.20)
DIMENSIONS
in inches (mm)
Minimum/Maximum
Symbol
20 Lead
D
0.252/0.260
(6.40/6.60)
e
0.026 BSC
(0.65 BSC)
D
PACKAGE: PLASTIC THIN SMALL OUTLINE (TSSOP)
Rev. 6/25/03
SP3203
Copyright 2003 Sipex Corporation
14
Model
Temperature Range
Package Types
SP3203CY
0
C to +70
C
20-pin TSSOP
SP3203EY
-40
C to +85
C
20-pin TSSOP
ORDERING INFORMATION
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Please consult the factory for pricing and availability on a Tape-On-Reel option.
Corporation
ANALOG EXCELLENCE
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sales Office
22 Linnell Circle
Billerica, MA 01821
TEL: (978) 667-8700
FAX: (978) 670-9001
e-mail: sales@sipex.com
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